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Every ESP32-S3 build gets a 1 ms tick and LVGL-sized caches - #164
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A display added to a board after flashing gets the same speed as one that shipped with it. The settings move from the LCD-4.3, LCD-7 and T-Embed variants into variants/esp32/sdkconfig.esp32s3, with the measurements from all three boards.
bdbarnett
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Every ESP32-S3 build now gets a 1 ms FreeRTOS tick and caches sized for LVGL (a 32 KB instruction cache, a 64 KB data cache, 64-byte lines), whether or not the board shipped with a display, so a display added after flashing gets the same speed. The settings move from the LCD-4.3, LCD-7 and T-Embed variants into
variants/esp32/sdkconfig.esp32s3. The P4 is unchanged.lv_test_timer's kit run, median of three, port defaults against these settings:
blit_rectcall takes 1.5 ms instead of 2.0 ms. At the standard 33 ms period it's pinned at 30 fps either way.The caches take 48 KB of internal RAM. With the display up, the T-Embed's free internal RAM went from 175,867 to 161,295 B. A 36-minute Wi-Fi and TLS soak on the LCD-4.3 never had less than 94 KB free.
Built locally:
ESP32_GENERIC_S3(8 MB),LCD_4_3andT_EMBED, each with--modules all. All three resolved configs carry the four settings. The T-Embed image was flashed and runs its display, audio in and out, and Wi-Fi.