Conversation
* Added build flags for compiling DPDK on ARM * Added sse2neon as a submodule for translating Intel SSE intrinsics to Arm/Aarch64 NEON implementation: https://github.com/DLTcollab/sse2neon * Implemented SSE4.2 _mm_cmpstri as not supported by sse2neon. Adapted from: https://github.com/apache/impala/blob/master/be/src/util/sse-util.h * Added equivalent arm64 asm for x86_64 asm.
|
FYI: recently SSE2NEON supports |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Arm/Aarch64 NEON implementation.
from: https://github.com/apache/impala/blob/master/be/src/util/sse-util.h
All tests passed except
TscToUs.Frequencyas on ARM reported tsc_hz is 50MHz (cross checked withmrs x0, cntfrq_el0instruction which returns Timer Counter Frequency register). This is failing as the test requires frequency >= 500MHz.Closes #1028