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Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
for more information, see https://pre-commit.ci
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
for more information, see https://pre-commit.ci
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
…ped_backup_g2r Take the refactored quantize_bidimensional_mxfp8_g2r (explicit ROWWISE/COLWISE/dtype constexprs instead of a config) and the internal PACK_SIZE/WAVES/THREADS_PER_BANK of quantize_rowwise_mxfp8. Adapt the grouped kernels to both: the grouped g2r kernel passes its config's fields to the tile function, and reduce_rowwise_dbias uses the same fixed constants as quantize_rowwise_mxfp8. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
…ped_backup_g2r
Adapt the grouped kernels to the renamed single-tensor modules and helpers
(g2s_general / g2r_bidim, _quantize_{rowwise,colwise}_mxfp8,
quantize_mxfp8_gmem_tile_bidimensional with its new act/dact arguments), and
keep reduce_rowwise_dbias as a shared helper for the grouped kernel.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
The more_cutedsl_mxfp8_specialized base was squash-merged as NVIDIA#3642, so CuTeDSL conflicts were resolved by 3-way merging against dba8dbf, the last base-branch commit merged here. CuTeDSL/__init__.py: register both get_mxfp8_group_quantization_function and NVIDIA#3560's get_mxfp8_requantization_function. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
for more information, see https://pre-commit.ci
[Medium impact] The change affects grouped MXFP8 quantization across supported CuTeDSL callers. The PR appears safe to merge, with a non-blocking correction needed in the grouped PyTorch comparisons. Findings
SummaryAdds CuTeDSL kernels for grouped MXFP8 quantization.
Diagram%%{init: {'theme': 'neutral'}}%%
flowchart TD
A[Grouped MXFP8 call] --> B{CuTeDSL enabled and supported?}
B -- No --> C[Existing CUDA kernel]
B -- Yes --> D{Single-tensor view eligible?}
D -- Yes --> E[Existing single-tensor kernel]
D -- No --> F{Grouped register kernel eligible?}
F -- Yes --> G[Grouped register kernel]
F -- No --> H[General grouped kernel]
H --> I[Reduce partial bias sums when requested]
Reviews (1) · Last reviewed commit: "[pre-commit.ci] auto fixes from pre-comm..." · Reviewed by Greptile |
| parts["rowwise data"] = out.rowwise_data.view(torch.uint8).clone() | ||
| parts["rowwise scales"] = out.scale_inv.view(torch.uint8).clone() | ||
| if columnwise: | ||
| parts["colwise data"] = out.columnwise_data.view(torch.uint8).clone() | ||
| parts["colwise scales"] = out.columnwise_scale_inv.view(torch.uint8).clone() |
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extract_group_quantized_output compares raw FP8 bytes, but the reused CuTeDSL conversion helpers preserve negative zero where CUDA's grouped conversion can produce positive zero. Small negative inputs that round to zero can therefore fail these tests even though both outputs have the same value.
Fold 0x80 into 0x00 for grouped data, as extract_quantized_output already does. Keep the scale comparisons unchanged.
Description
Add CuTeDSL kernels for MXFP8 grouped quantization
Type of change
Changes
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