I'm an Electronics & Computer Engineering student interested in building digital systems from RTL to working hardware.

My primary interests are RTL Design, Computer Architecture, FPGA Systems, SoC Design, and ASIC/VLSI. Most of my work revolves around understanding how complete digital systems fit together rather than treating individual RTL blocks in isolation.

I'm currently building a RISC-V-based SoC incrementally, starting from processor microarchitecture and moving through memory systems, DMA, interconnects, fault injection, FPGA implementation, and eventually ASIC implementation flows.

My main ongoing project is a system-level RV32I SoC, developed and verified incrementally on FPGA.

The system currently includes work across:

• 5-stage RV32I pipeline — IF / ID / EX / MEM / WB
• Data forwarding and hazard detection
• Load-use stalls and branch flushing
• Direct-mapped cache controller
• Scatter-gather DMA engine
• AXI4-based memory interfaces
• CDC FIFOs and arbitration
• Multi-master / multi-slave AXI interconnect
• Fault injection targeting CPU pipeline state
• FPGA synthesis and hardware verification

The processor has been hardware-tested running programs such as bubble sort, with results verified over UART.

The broader goal of this project is to understand the architectural decisions involved in building and integrating an SoC rather than stopping at CPU RTL.

Designed an AXI-Lite slave peripheral with a register file, datapath, and control FSM.

The accelerator was synthesized in Vivado, verified using directed SystemVerilog testbenches, and controlled from bare-metal firmware through MMIO on FPGA.

SystemVerilog AXI-Lite MMIO FSM Bare-Metal C

Developing a 3-channel FPGA signal-processing architecture combining SPI acquisition, AXI-Lite accelerators, FIR filtering, arbitration, and a central DSP core.

The goal is to perform deterministic on-fabric signal processing without depending on a host processor.

SystemVerilog SPI AXI-Lite FIR DSP

Built a mixed-signal FPGA acquisition pipeline consisting of:

SPI ADC → FIFO → UART

The design supports deterministic 1 kHz streaming, with FIFO-based decoupling between acquisition and communication logic and verification through ModelSim.

Verilog SPI FIFO CDC UART ModelSim

I'm currently expanding from FPGA-centric RTL development into the ASIC implementation flow.

I'm exploring:

• RTL synthesis
• Static timing concepts
• Constraints
• Floorplanning
• Placement & routing
• Clock-tree implementation
• Timing closure
• Physical verification
• OpenLane
• SKY130

I'm also planning my major project around a low-power clock recovery IC for a high-speed serial link, with the objective of taking the design through an RTL-to-GDS flow and, where feasible, toward tapeout.

SystemVerilog Verilog VHDL RTL Design FSMs Pipelining CDC AXI4 AXI-Lite MMIO FIFO Design

RISC-V RV32I Cache Design DMA Interconnects Computer Architecture

Vivado ModelSim Cadence OpenLane SKY130

C C++ Bare-Metal Programming FreeRTOS SPI UART

Python Git Linux MATLAB

I'm particularly interested in engineering problems involving:

• RTL & Digital Design
• CPU / SoC Microarchitecture
• FPGA Engineering
• ASIC Design
• Hardware/Software Interfaces
• High-Speed Digital Systems
• Physical Design & RTL-to-GDS

Long term, I'm interested in developing the breadth needed to understand digital systems across the stack — from microarchitecture and RTL through FPGA validation and physical implementation.

Building: RISC-V SoC Learning: ASIC physical implementation & RTL-to-GDS Exploring: High-speed serial-link architectures Looking for: RTL, FPGA, SoC and Physical Design opportunities

Feel free to explore my repositories or reach out if you're working on similar hardware.