INIYAVAN S INIYA-1010

🧠 About Me

module about_me (
  output reg [7:0] passion,
  output reg       ready_for_internship
);

  // Personal Info
  localparam NAME      = "INIYAVAN S";
  localparam LOCATION  = "Namakkal, Tamil Nadu, India";
  localparam DEGREE    = "B.E Electronics Engg (VLSI Design & Technology)";
  localparam COLLEGE   = "K.S. Rangasamy College of Technology";
  localparam CGPA      = 8.18;

  // Tech Stack
  reg [63:0] stack [0:5];
  initial begin
    stack[0] = "Verilog HDL / RTL Design";
    stack[1] = "RISC-V Architecture (RV32IMC)";
    stack[2] = "Synopsys VCS + DC + SpyGlass";
    stack[3] = "APB / UART Protocols";
    stack[4] = "Functional Verification";
    stack[5] = "Xilinx Vivado + ModelSim";
  end

  // Currently Leveling Up
  reg [63:0] learning [0:2];
  initial begin
    learning[0] = "SystemVerilog & UVM";
    learning[1] = "Static Timing Analysis";
    learning[2] = "Advanced CDC Techniques";
  end

  // Fun Fact & Motto
  task fun_fact;
    $display("I debugged a CDC violation at 2AM and felt great about it.");
  endtask

  task motto;
    $display("Simulate. Synthesize. Tape Out. Repeat.");
  endtask

  always @(*) begin
    passion             = 8'hFF;
    ready_for_internship = 1'b1;
  end

endmodule

🛠️ Tech Stack & Tools

Hardware Design & Protocols

EDA Tools

Programming & OS

📊 GitHub Stats

🔥 Streak Stats

📈 Activity Graph

🏆 Trophy Wall

💼 Work Experience

🏢 Digital Design & Verification Intern — 4-Week Internship (Verilog HDL)

🔧 Developed RTL designs and performed functional verification using Verilog HDL across multiple design modules
⚡ Designed and simulated both combinational and sequential digital circuits, building practical RTL skills
🐧 Gained exposure to the complete frontend VLSI design flow — including Linux environment, EDA toolchain usage, and DFT fundamentals
📐 Strengthened understanding of design correctness validation through directed simulation and waveform analysis

🚀 Featured Projects

Project	Stack	Highlights
🔬 RISC-V SoC Design	`Verilog HDL` `Synopsys VCS` `DC Compiler` `SpyGlass`	Designed RV32IMC SoC integrating CPU core with UART & memory-mapped I/O; full RTL-to-synthesis flow covering lint, CDC, logic synthesis & timing analysis
📡 Multi-Clock UART Transceiver	`Verilog` `APB Protocol` `ModelSim` `VCS`	Full-duplex UART with configurable baud rate, multi-clock domain support; APB slave interface for AMBA register-mapped control; TX/RX integrity validated across CDC
🏗️ Real-Time Object Detection on PYNQ-Z2	`Xilinx Vivado` `Python` `PYNQ-Z2` `FPGA`	FPGA-accelerated inference pipeline with hardware-software co-design; camera I/O pipeline optimized for real-time low-latency performance
🛗 Smart Elevator Controller	`Verilog` `FSM` `ModelSim`	FSM-based multi-floor elevator controller with priority-based request scheduling; verified all state transitions under multiple test scenarios

🏅 Achievements & Certifications

🎖️	Achievement	Details
🏆	C-DAC 1-TOPS Semiconductor Tape-Out Program	Cleared Round 1 and attended interview — national-level semiconductor SoC design program
🌐	Bharat AI-SoC Student Challenge	Participated in national-level semiconductor design challenge — FPGA-based AI SoC
🎓	NPTEL — Introduction to Semiconductor Devices	Certified by IIT/NIT via NPTEL MOOC platform
🌐	NPTEL — Introduction to Internet of Things	Certified by IIT/NIT via NPTEL MOOC platform
🔌	PCB Skill Development — Invocrux Technologies	Industrial training on PCB Design & Fabrication
🧪	VLSI Mentors Workshop	Digital Design using Multi-Vt Libraries — standard cell library concepts

🎓 Education

📚 Degree	🏫 Institution	📅 Year	🎯 Score
B.E Electronics Engineering (VLSI Design & Technology)	K.S. Rangasamy College of Technology, Anna University	Sep 2023 – Jun 2027	CGPA: 8.18
Higher Secondary Education (Bio-Maths)	Sri Vidya Mandir Matric Hr. Sec. School, State Board	Jul 2019 – Mar 2020	57%

📡 Currently Learning

🧱 SystemVerilog       → Interfaces, Clocking Blocks, Assertions (SVA)
🔬 UVM Methodology     → Agents, Sequencers, Scoreboards, Coverage
⏱️ Static Timing Analysis → Setup/Hold Paths, Slack Optimization
🔄 Advanced CDC        → Handshaking, FIFO-based synchronizers, Formal CDC
🔧 Synopsys DC Adv.    → Constraint writing, multi-corner synthesis
📐 STA with PrimeTime  → Path-based analysis, CRPR, AOCV

🌟 Areas of Interest

"Simulate. Synthesize. Tape Out. Repeat."

📫 Reach me at: iniyavansoundar2002@gmail.com | 📍 Namakkal, Tamil Nadu

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