I am an Electronics and Communication Engineering student focused on digital VLSI design, RTL development, processor microarchitecture, and FPGA-based systems.

My approach is simple: understand the architecture, write clean synthesizable RTL, verify the behavior with focused testbenches, and document the design flow clearly.

• RTL Design: Verilog HDL, synthesizable modular design, FSMs, datapaths
• Processor Design: RV32I RISC-V, 5-stage pipelining, control and memory interfaces
• FPGA / SoC: Zynq-7000, AXI4, AXI4-Stream, AXI VDMA, DDR and VGA systems
• Verification: RTL testbenches, simulation, waveform-based debugging
• VLSI Flow: RTL → synthesis → timing analysis → physical-design fundamentals
• Open Source: Practical RTL/FPGA/HLS issue investigation and upstream contributions

A modular 32-bit RV32I processor in Verilog HDL with a classic IF → ID → EX → MEM → WB pipeline, dedicated control/datapath blocks, instruction/data memory models, and module-level verification.

Focus: RTL architecture • Pipelining • Control Logic • Memory Operations • Simulation

A hardware/software video pipeline using the Zynq-7000 processing system, AXI VDMA, DDR frame buffering, VTC, AXI4-Stream video, and VGA output.

Focus: FPGA/SoC Integration • AXI • DMA • DDR • Video Timing • Embedded Hardware/Software

A fork used to study and contribute to an open-source HLS-to-hardware toolchain, with emphasis on reproducible issues, targeted fixes, regression coverage, and clear engineering documentation.

• RTL-to-GDSII design flow
• Static Timing Analysis and timing-closure concepts
• Synthesis constraints and reporting
• Advanced RTL verification and regression testing
• Open-source EDA and hardware-development workflows

• Prefer reproducible bugs and measurable fixes over cosmetic activity
• Keep project scope and claims aligned with the current implementation
• Document architecture, assumptions, simulation steps, and known limitations
• Treat GitHub as an engineering portfolio, not a commit counter

Verilog HDL SystemVerilog RISC-V RV32I Vivado Icarus Verilog GTKWave Zynq-7000 AXI4 AXI4-Stream AXI VDMA VGA Git GitHub

• Email: afhamurrahman@gmail.com
• LinkedIn: LinkedIn
• GitHub: GITTYCAT12