Add explanatory comment for portFPU_REG_OFFSET in RISC-V port

[wanghengZzz]

Description

Clarify FPU context offset calculation in RISC-V portContext.h

This PR adds an explanatory comment to portFPU_REG_OFFSET() in portContext.h for the RISC-V port to improve code readability and maintainability.

In portContext.h, the macro portFPU_REG_OFFSET( regIndex ) uses ( 2 * portWORD_SIZE ) as the base offset for saving floating-point registers. Without documentation, this offset design is not immediately obvious to developers reading the kernel porting code.

The ( 2 * portWORD_SIZE ) reservation serves two critical purposes:

1. FCSR Storage: Holds the 32-bit Floating-Point Control and Status Register (fcsr).
2. Alignment Guarantee: Ensures proper memory/stack alignment across architectures:
   • RV32D: Provides 8-byte natural alignment required for 64-bit double-precision floating-point load/store instructions (fld/fsd).
   • RV64: Maintains the 16-byte stack alignment mandated by the RISC-V ELF PSABI.

Checklist:

• I have tested my changes. No regression in existing tests.
• I have modified and/or added unit-tests to cover the code changes in this Pull Request.

Related Issue

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[sonarqubecloud]

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

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