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Merged
miczyg1 merged 15 commits into from
Jan 17, 2025
Merged

Changes for Heads on NovaCustom V560TU #609

miczyg1 merged 15 commits into from
Jan 17, 2025

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@mkopec
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@mkopec mkopec commented Jan 15, 2025 •
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  • Fix building with FSP from dasharo-blobs
  • Add PR0 lockdown in SMM
  • Enable S3 on MTL
  • Fixes for HAP on MTL
  • Always pull FSP submodule, to ensure SplitFspBin is present
  • Move IOE_P2SB below 4G to reduce MTRR fragmentation (faster boot on 64 and 96 GB RAM configs)
  • Always put I2C and framebuffer below 4G when built for IA32, to make sure we can use them in coreboot
  • Fix for FSP GOP not initializing internal panel if an external display with res < 1920x1200 is connected
  • JPEG patches for bootsplash, previously maintaned downstream in Heads

mkopec and others added 7 commits January 15, 2025 17:01
@mkopec
vc/intel/fsp/fsp2_0/iot/meteorlake: add missing MemInfoHob from clien…
e8a3f7e 
…t vc dir

Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
@shuoliu0 @mkopec
soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP
9443006 
In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.

Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
@miczyg1 @mkopec
soc/intel/lockdown: Allow locking down SPI and LPC in SMM
a4f9bd2 
Heads payload uses APM_CNT_FINALIZE SMI to set and lock down the SPI
controller with PR0 flash protection for pre-Skylake platforms.

Add new option to skip LPC and FAST SPI lock down in coreboot and move
it to APM_CNT_FINALIZE SMI handler. Reuse the INTEL_CHIPSET_LOCKDOWN
option to prevent issuing APM_CNT_FINALIZE SMI on normal boot path,
like it was done on pre-Skylake platforms. As the locking on modern
SOCs became more complicated, separate the SPI and LPC locking into
new modules to make linking to SMM easier.

The expected configuration to leverage the feautre is to unselect
INTEL_CHIPSET_LOCKDOWN and select SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM.

Testing various microarchitectures happens on heads repository:
linuxboot/heads#1818

TEST=Lock the SPI flash using APM_CNT_FINALIZE in heads on Alder Lake
(Protectli VP66xx) and Comet Lake (Protectli VP46xx) platforms. Check
if flash is unlocked in the heads recovery console. Check if flash is
locked in the kexec'ed OS.

Change-Id: Icbcc6fcde90e5b0a999aacb720e2e3dc2748c838
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
@mkopec
soc/intel/mtl/fsp_params.c: wire up sleep mode option
092267f 
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
@mkopec
clevo/mtl-h/ramstage.c: implement sleep mode option
9f5143b 
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
@mkopec
soc/intel/cmn/blk/cse/cse.c: skip me_enable while ME is in Debug mode
8d960e9 
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
@mkopec
Makefile.mk: Always pull FSP submodule
3138e53 
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
@macpijan macpijan requested a review from miczyg1 January 15, 2025 16:06
@mkopec
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mkopec commented Jan 15, 2025

Should go in before linuxboot/heads#1846

miczyg1
miczyg1 requested changes Jan 16, 2025
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While we are at limiting the necessary resources to 32bit, can you please limit it on the CSE HECI device as well? That way the allocation could work also for other builds than heads, where ME is active.

mkopec added 2 commits January 16, 2025 12:03
@mkopec
soc/intel/cmn/blk/graphics: ensure framebuffer is allocated <4G
b890d38 
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
@mkopec
soc/intel/cmn/blk/i2c: ensure resources are allocated <4G
c4edf10 
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
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mkopec commented Jan 16, 2025 •
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While we are at limiting the necessary resources to 32bit, can you please limit it on the CSE HECI device as well? That way the allocation could work also for other builds than heads, where ME is active.

Done 5a313c7 (builds, but untested on a platform with ME enabled)

mkopec added 2 commits January 16, 2025 12:18
@mkopec
soc/intel/cmn/blk/cse/cse.c: ensure resources are allocated <4G
5a313c7 
Without this patch, if RESOURCE_ALLOCATION_TOP_DOWN is enabled and
coreboot is compiled for IA32, the HECI device becomes inaccessible
after resource allocation.

Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
@mkopec
mb/clevo/mtl-h: Set MMIO size to 2.5GB
40e8d1a 
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
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mkopec commented Jan 16, 2025

@miczyg1 can you take another look?

mkopec and others added 4 commits January 16, 2025 12:59
@mkopec
soc/intel/mtl: move IOE P2SB BAR below 4G
d047598 
This frees up two MTRRs for SPI flash caching

IOM_BASE_ADDR has to be hardcoded, otherwise iasl throws an error while
building

```
dsdt.asl   1374:     0x1600,,,)
Error    6050 -          ^ Length is not equal to fixed Min/Max window
```

It seems like IASL can't perform arithmetic operations inside
QWordMemory definitions.

See https://review.coreboot.org/c/coreboot/+/84216

Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
@nigeltao @mkopec
lib/jpeg: avoid calling malloc and free
21058cb 
Since commit 1d029b4 ("lib/jpeg: Replace decoder with Wuffs'
implementation"), a relatively large heap allocation is needed to decode
many JPEGs for use as work area. The prior decoder did not need this,
but also had many limitations in the JPEGs it could decode, was not as
memory-safe and quickly crashed under fuzzing.

This commit keeps using Wuffs' JPEG decoder, but it no longer requires
any heap allocation (and thus configuring the heap size depending on how
big a bootsplash image you want to support).

Change-Id: Ie4c52520cbce498539517c4898ff765365a6beba
Signed-off-by: Nigel Tao <nigeltao@golang.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
@nigeltao @mkopec
vc/wuffs: upgrade to Wuffs 0.4.0-alpha.8
d8b2452 
We were previously at Wuffs 0.4.0-alpha.2. The C file was copied from
https://github.com/google/wuffs-mirror-release-c and its hash matches
https://github.com/google/wuffs-mirror-release-c/blob/90e4d81a6a8b7b601e8e568da32a105d7f7705e5/sync.txt#L9-L10

$ sha256sum src/vendorcode/wuffs/wuffs-v0.4.c
6c22caff4af929112601379a73f72461bc4719a5215366bcc90d599cbc442bb6  src/vendorcode/wuffs/wuffs-v0.4.c

Change-Id: Ie90d989384e0db2b23d7d1b3d9a57920ac8a95a2
Signed-off-by: Nigel Tao <nigeltao@golang.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83894
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
@mkopec
mb/clevo/mtl-h/variants/igpu/data.vbt: Disable secondary display feature
048ca83 
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
@miczyg1 miczyg1 merged commit 048ca83 into dasharo Jan 17, 2025
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@miczyg1 miczyg1 deleted the mtl_heads branch January 17, 2025 11:57
@mkopec mkopec mentioned this pull request Jan 17, 2025
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@mkopec mkopec mentioned this pull request Feb 4, 2025
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@mkopec @macpijan @miczyg1 @shuoliu0 @nigeltao