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WIP: opt: optimize EVM-to-dMIR compilation for reduced instruction count a…#400

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WIP: opt: optimize EVM-to-dMIR compilation for reduced instruction count a…#400
zoowii wants to merge 1 commit intoDTVMStack:mainfrom
zoowii:opt/opt_dmir

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@zoowii zoowii commented Mar 11, 2026

…nd register pressure

  • Replace select-chain patterns in SHL/SHR/SAR with scratch-based indexed loads, reducing ~120 dMIR instructions to ~20 per shift operation
  • Add SBB (subtract-with-borrow) dMIR instruction and use SUB/SBB chains for multi-limb subtraction, cutting x86 output from ~36 to ~12 instructions
  • Optimize unsigned LT/GT comparisons using SUB/SBB chain + ADC(0,0) to capture the borrow flag, replacing multi-limb select chains
  • Specialize MUL for small constant operands with a 1-limb fast path (~80% reduction) and full constant folding when both operands are known
  • Optimize SIGNEXTEND with compile-time constant index fast path and scratch-based sign-bit extraction for runtime indices
  • Add peephole constant folding for PUSH+arithmetic/bitwise sequences (ADD, SUB, AND, OR, XOR) using intx::uint256
  • Remove SHL/SHR/SAR from RA-expensive opcode list; update MIR_OPCODE_WEIGHT for SUB (20->12) and LT/GT (12->8) to reflect efficiency gains

Made-with: Cursor

1. Does this PR affect any open issues?(Y/N) and add issue references (e.g. "fix #123", "re #123".):

  • N
  • Y

2. What is the scope of this PR (e.g. component or file name):

3. Provide a description of the PR(e.g. more details, effects, motivations or doc link):

  • Affects user behaviors
  • Contains CI/CD configuration changes
  • Contains documentation changes
  • Contains experimental features
  • Performance regression: Consumes more CPU
  • Performance regression: Consumes more Memory
  • Other

4. Are there any breaking changes?(Y/N) and describe the breaking changes(e.g. more details, motivations or doc link):

  • N
  • Y

5. Are there test cases for these changes?(Y/N) select and add more details, references or doc links:

  • Unit test
  • Integration test
  • Benchmark (add benchmark stats below)
  • Manual test (add detailed scripts or steps below)
  • Other

6. Release note

None

…nd register pressure

- Replace select-chain patterns in SHL/SHR/SAR with scratch-based indexed loads,
  reducing ~120 dMIR instructions to ~20 per shift operation
- Add SBB (subtract-with-borrow) dMIR instruction and use SUB/SBB chains for
  multi-limb subtraction, cutting x86 output from ~36 to ~12 instructions
- Optimize unsigned LT/GT comparisons using SUB/SBB chain + ADC(0,0) to capture
  the borrow flag, replacing multi-limb select chains
- Specialize MUL for small constant operands with a 1-limb fast path (~80%
  reduction) and full constant folding when both operands are known
- Optimize SIGNEXTEND with compile-time constant index fast path and scratch-based
  sign-bit extraction for runtime indices
- Add peephole constant folding for PUSH+arithmetic/bitwise sequences (ADD, SUB,
  AND, OR, XOR) using intx::uint256
- Remove SHL/SHR/SAR from RA-expensive opcode list; update MIR_OPCODE_WEIGHT for
  SUB (20->12) and LT/GT (12->8) to reflect efficiency gains

Made-with: Cursor
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⚡ Performance Regression Check Results

⚠️ Performance Regression Detected (interpreter)

No benchmark summary available.


⚠️ Performance Regression Detected (multipass)

No benchmark summary available.


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