WIP: opt: optimize EVM-to-dMIR compilation for reduced instruction count a…#400
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WIP: opt: optimize EVM-to-dMIR compilation for reduced instruction count a…#400zoowii wants to merge 1 commit intoDTVMStack:mainfrom
zoowii wants to merge 1 commit intoDTVMStack:mainfrom
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…nd register pressure - Replace select-chain patterns in SHL/SHR/SAR with scratch-based indexed loads, reducing ~120 dMIR instructions to ~20 per shift operation - Add SBB (subtract-with-borrow) dMIR instruction and use SUB/SBB chains for multi-limb subtraction, cutting x86 output from ~36 to ~12 instructions - Optimize unsigned LT/GT comparisons using SUB/SBB chain + ADC(0,0) to capture the borrow flag, replacing multi-limb select chains - Specialize MUL for small constant operands with a 1-limb fast path (~80% reduction) and full constant folding when both operands are known - Optimize SIGNEXTEND with compile-time constant index fast path and scratch-based sign-bit extraction for runtime indices - Add peephole constant folding for PUSH+arithmetic/bitwise sequences (ADD, SUB, AND, OR, XOR) using intx::uint256 - Remove SHL/SHR/SAR from RA-expensive opcode list; update MIR_OPCODE_WEIGHT for SUB (20->12) and LT/GT (12->8) to reflect efficiency gains Made-with: Cursor
⚡ Performance Regression Check Results
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…nd register pressure
Made-with: Cursor
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