feat: estimate cycles#17
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- feat: add cycle estimation based on LUT
- fix(callgrind): make Capstone cycle-estimation build and link
- chore: wip [skip ci]
Merging this PR will not alter performance
Warning Please fix the performance issues or acknowledge them on CodSpeed. Performance Changes
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Add callgrind/lut-gen/ (offline generators for the --cycle-estimation cost tables) and the regenerated x86_caps_lut.inc / arm64_caps_lut.inc. - lib/: sigkey.py (Python mirror of sigkey.h's packed-key contract) and gen_common.py (shared measurement parsing, collision collapse, emit). - x86/gen_x86_lut.py: Zen4-tuned table from uops.info instructions.xml. - arm64/: measured Cortex-A72 table from ocxtal/insn_bench_aarch64 via insn_bench_to_xml.py -> gen_arm64_lut.py -> merge_arm64_lut.py, with a hand-frozen guide supplement for ops insn_bench does not benchmark. - test_lut.py: validates the committed tables against the runtime keying contract and asserts sigkey.py stays in lockstep with sigkey.h.
Add the --cycle-estimation=yes runtime: decode each guest instruction with Capstone and look its reciprocal-throughput cost up in the generated cost table (x86/arm64_caps_lut.inc), accumulating a per-instruction Cy event. - cycledecode.c/.h: isolated Capstone decode + LUT lookup behind a plain-C ABI (no Valgrind tool headers, to avoid type clashes); freestanding libc shims since the tool links -nodefaultlibs. - sigkey.h: packed (insn-id, signature) key contract shared with the offline LUT generators in lut-gen/. - main.c/sim.c/bbcc.c/global.h/clo.c: wire Cy through callgrind (CLI option, EventSet, self + inclusive cost, fallback warning when an instruction has no table match). - configure.ac/Makefile.am: build cycledecode against Capstone. Emits only Cy (reciprocal throughput); no latency event.
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