clock_stm32_u5: Voltage regulator high ranges cannot be selected when running at low clock frequency

[petrosyan-van]

Summary

On STM32U585 (custom board), migrating to Zephyr v4.3.0-rc1 and the USB device stack “next”, as the current stack is flagged as deprecated. My application runs at HCLK = 40 MHz for power savings. The STM32U5 clock driver currently sets VOS3 whenever HCLK is below ~55 MHz. The new STM32 UDC driver checks the regulator voltage scaling and refuses to initialize the USB device peripheral unless VOS ≥ 2. As a result, USBD init fails, even though the same hardware/clock configuration worked with the old USB device stack.

Current behavior

• With HCLK = 40 MHz, clock driver selects VOS3.
• During USBD bring-up, UDC checks VOS and fails with an error similar to:

/* Check that power range is 1 or 2 */
if (LL_PWR_GetRegulVoltageScaling() < LL_PWR_REGU_VOLTAGE_SCALE2) {
	LOG_ERR("Wrong Power range to use USB OTG HS");
	return -EIO;
}

Describe the solution you'd like

Provide a supported way to run STM32U5 USB device (FS) at low HCLK (e.g., 40 MHz) while selecting VOS2, at least when USB is active, without patching Zephyr source locally and without having to raise HCLK above 55 MHz.

Why this matters

• We have devices in the field that are already configured for 40 MHz HCLK for power consumption reasons, and I would be also scared a bit to do an OTA that affects the clock in the app, considering that bootloader will still be with old clock
• The legacy USB stack is being deprecated; we need to adopt the “next” stack

A potential solution can be introducing a small runtime hook so peripherals that require higher VOS (e.g., USB device) can request VOS2 during activation and release it on suspend/disconnect (reference-counted, like the pm runtime).

Alternatives

No response

Additional Context

No response

[mathieuchopstm]

For self reference: root cause is regulator scale select is hardcoded based on HCLK frequency here

zephyr/drivers/clock_control/clock_stm32_ll_u5.c

Lines 433 to 446 in 0f5e03f

	static void set_regu_voltage(uint32_t hclk_freq)
	{
	if (hclk_freq < MHZ(25)) {
	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE4);
	} else if (hclk_freq < MHZ(55)) {
	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE3);
	} else if (hclk_freq < MHZ(110)) {
	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
	} else {
	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
	}
	while (LL_PWR_IsActiveFlag_VOS() == 0) {
	}
	}

Solution ==> PWR driver + DTS node

[mathieuchopstm]

Following #99171 merge, this shouldn't be too difficult to implement:

1. add a property
2. in clock_stm32_ll_u5.c, something along the lines of:

static void set_regu_voltage(uint32_t hclk_freq) 
{
	bool invalid_user_scale = false;
	uint32_t requested = /* from property */;
	uint32_t applied = INVALID;
	if (/* property provided */) {
		if (requested == SCALE4 && hclk_freq > MHZ(25)) {
			invalid_scale = true;
		} else if (requested == SCALE3 && hclk_freq > MHZ(55)) {
			invalid_scale = true;
		} else if (requested == SCALE2 && hclk_freq > MHZ(110)) {
			invalid_scale = true;
		} else {
			applied = requested;
		}
	}

	if (applied == INVALID) {
		if (hclk_freq < MHZ(25)) { 
			applied = LL_PWR_REGU_VOLTAGE_SCALE4); 
		} else if (hclk_freq < MHZ(55)) { 
	 		applied = LL_PWR_REGU_VOLTAGE_SCALE3); 
		} else if (hclk_freq < MHZ(110)) { 
			applied = LL_PWR_REGU_VOLTAGE_SCALE2); 
		} else { 
			applied = LL_PWR_REGU_VOLTAGE_SCALE1); 
		} 
	}

	if (invalid_user_scale) {
		LOG_ERR("Invalid scale requested %u (HCLK=%u MHz)", requested, hclk_freq);
	};

	LL_PWR_SetRegulVoltageScaling(applied);
 	while (LL_PWR_IsActiveFlag_VOS() == 0) { 
	} 
 }