dts: silabs: Add NWP boot configuration properties

Add new Devicetree properties under the SiWx91x NWP node to describe
hardware-specific boot configuration options.

The properties are documented in the SiWx91x NWP YAML binding.

Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>

Author: ArunmaniAlagarsamy2710

dts/arm/silabs/siwg917.dtsi

@@ -81,6 +81,10 @@
 		interrupt-parent = <&nvic>;
 		interrupts = <30 0>, <74 0>;
 		interrupt-names = "nwp_stack", "nwp_irq";
+		antenna-selection = "ext-gpios";
+		support-1p8v;
+		enable-xtal-correction;
+		qspi-80mhz-clk;
 		status = "okay";
 
 		bt_hci0: bt_hci {

dts/bindings/net/wireless/silabs,siwx91x-nwp.yaml

@@ -31,3 +31,49 @@ properties:
       - deep-sleep-without-ram-retention
       - deep-sleep-with-ram-retention
     required: true
+
+  support-1p8v:
+    type: boolean
+    description: |
+      Enables 1.8 V operation support.
+
+  enable-xtal-correction:
+    type: boolean
+    description: |
+      Enables automatic 40 MHz XTAL frequency correction.
+      Disable this when using a custom or uncalibrated XTAL and manual tuning is required.
+
+  qspi-80mhz-clk:
+    type: boolean
+    description: |
+      Enables 80 MHz QSPI clock mode for the NWP flash interface to improve
+      throughput. Enable this if the external flash device supports 80 MHz
+      operation; otherwise, keep it disabled.
+  # Note:
+  # Zephyr typically manages clocks via a clock-controller driver.
+  # However, the NWP is not yet fully compatible with that model.
+  # This property is kept as a temporary solution for NWP-specific configuration.
+
+  antenna-selection:
+    type: string
+    description: |
+      Selects the front-end (antenna) switch configuration for the NWP.
+
+      This property determines how the RF path is controlled:
+        - "none": Reserved or unused configuration.
+        - "ext-gpios": Use external ULP GPIOs (4, 5, and 0) as ANT_SEL control lines
+          for the external RF switch network.
+        - "internal": Use the internal on-chip RF switch logic. No external GPIO
+          control is required. Recommended for boards without an external RF
+          switch circuit.
+
+      The value maps directly to bits [30:29] of the SL_SI91X_EXT_FEAT register:
+        - 00b: Reserved
+        - 01b: External GPIOs (ULP_GPIO4/5/0)
+        - 10b: Internal front-end switch
+        - 11b: Reserved
+    enum:
+      - "none"
+      - "ext-gpios"
+      - "internal"
+    required: true