diff --git a/boards/pic32cz_curiosity_ultra/board.c b/boards/pic32cz_curiosity_ultra/board.c
index 637a09a..58e18d7 100644
--- a/boards/pic32cz_curiosity_ultra/board.c
+++ b/boards/pic32cz_curiosity_ultra/board.c
@@ -17,9 +17,6 @@ whal_Clock g_whalClock = {
     .cfg = &(whal_Pic32czClock_Cfg) {
         /* 300MHz clock */
         .oscCtrlCfg = &(whal_Pic32czClockPll_OscCtrlCfg) {
-            .supplyCtrl = &g_whalSupply,
-            .supply = &(whal_Pic32czSupc_Supply){WHAL_PIC32CZ_SUPPLY_PLL},
-
             .pllInst = WHAL_PIC32CZ_PLL0,
             .refSel = WHAL_PIC32CZ_REFSEL_DFLL48M,
             .bwSel = WHAL_PIC32CZ_BWSEL_10MHz_TO_20MHz,
@@ -48,6 +45,18 @@ whal_Clock g_whalClock = {
     },
 };
 
+/* Peripheral clocks */
+static const whal_Pic32czClock_Clk g_peripheralClocks[] = {
+    { /* SERCOM 4 (UART) */
+        .gclkPeriphChannel = 25,
+        .gclkPeriphSrc = 0, /* GEN 0 */
+        .mclkEnableInst = 1,
+        .mclkEnableMask = (1UL << 3),
+        .mclkEnablePos = 3,
+    },
+};
+#define PERIPHERAL_CLOCK_COUNT (sizeof(g_peripheralClocks) / sizeof(g_peripheralClocks[0]))
+
 /* GPIO */
 whal_Gpio g_whalGpio = {
     WHAL_PIC32CZ_GPIO_DEVICE,
@@ -78,20 +87,10 @@ whal_Gpio g_whalGpio = {
 };
 
 /* UART */
-static whal_Pic32czClock_Clk uartClk = {
-    .gclkPeriphChannel = 25, /* SERCOM 4 */
-    .gclkPeriphSrc = 0, /* GEN 0 */
-    .mclkEnableInst = 1, /* Peripheral BUS Clock Enable Mask1 Register */
-    .mclkEnableMask = (1UL << 3), /* SERCOM 4 enable mask */
-    .mclkEnablePos = 3,
-};
-
 whal_Uart g_whalUart = {
     WHAL_PIC32CZ_SERCOM4_UART_DEVICE,
 
     .cfg = &(whal_Pic32czUart_Cfg) {
-        .clkCtrl = &g_whalClock,
-        .clk = &uartClk,
         .baud = WHAL_PIC32CZ_UART_BAUD(115200, 300000000),
         .txPad = WHAL_PIC32CZ_UART_TXPO_PAD0,
         .rxPad = WHAL_PIC32CZ_UART_RXPO_PAD1,
@@ -156,11 +155,25 @@ whal_Error Board_Init(void)
         return err;
     }
 
+    /* Enable PLL power supply before clock init */
+    err = whal_Supply_Enable(&g_whalSupply,
+                             &(whal_Pic32czSupc_Supply){WHAL_PIC32CZ_SUPPLY_PLL});
+    if (err) {
+        return err;
+    }
+
     err = whal_Clock_Init(&g_whalClock);
     if (err) {
         return err;
     }
 
+    /* Enable peripheral clocks */
+    for (size_t i = 0; i < PERIPHERAL_CLOCK_COUNT; i++) {
+        err = whal_Clock_Enable(&g_whalClock, &g_peripheralClocks[i]);
+        if (err)
+            return err;
+    }
+
     err = whal_Gpio_Init(&g_whalGpio);
     if (err) {
         return err;
@@ -218,6 +231,13 @@ whal_Error Board_Deinit(void)
         return err;
     }
 
+    /* Disable peripheral clocks */
+    for (size_t i = 0; i < PERIPHERAL_CLOCK_COUNT; i++) {
+        err = whal_Clock_Disable(&g_whalClock, &g_peripheralClocks[i]);
+        if (err)
+            return err;
+    }
+
     err = whal_Clock_Deinit(&g_whalClock);
     if (err) {
         return err;
diff --git a/boards/stm32wb55xx_nucleo/board.c b/boards/stm32wb55xx_nucleo/board.c
index b52a327..cc63eaa 100644
--- a/boards/stm32wb55xx_nucleo/board.c
+++ b/boards/stm32wb55xx_nucleo/board.c
@@ -34,9 +34,6 @@ whal_Clock g_whalClock = {
     WHAL_STM32WB55_RCC_PLL_DEVICE,
 
     .cfg = &(whal_Stm32wbRcc_Cfg) {
-        .flash = &g_whalFlash,
-        .flashLatency = WHAL_STM32WB_FLASH_LATENCY_3,
-
         .sysClkSrc = WHAL_STM32WB_RCC_SYSCLK_SRC_PLL,
         .sysClkCfg = &(whal_Stm32wbRcc_PllClkCfg)
         {
@@ -51,6 +48,16 @@ whal_Clock g_whalClock = {
     },
 };
 
+static const whal_Stm32wbRcc_Clk g_flashClock = {WHAL_STM32WB55_FLASH_CLOCK};
+
+static const whal_Stm32wbRcc_Clk g_peripheralClocks[] = {
+    {WHAL_STM32WB55_GPIOB_CLOCK},
+    {WHAL_STM32WB55_UART1_CLOCK},
+    {WHAL_STM32WB55_RNG_CLOCK},
+    {WHAL_STM32WB55_AES1_CLOCK},
+};
+#define PERIPHERAL_CLOCK_COUNT (sizeof(g_peripheralClocks) / sizeof(g_peripheralClocks[0]))
+
 /* GPIO */
 enum {
     LED_PIN,
@@ -62,12 +69,6 @@ whal_Gpio g_whalGpio = {
     WHAL_STM32WB55_GPIO_DEVICE,
 
     .cfg = &(whal_Stm32wbGpio_Cfg) {
-        .clkCtrl = &g_whalClock,
-        .clk = (const void *[1]) {
-            &(whal_Stm32wbRcc_Clk){WHAL_STM32WB55_GPIOB_CLOCK},
-        },
-        .clkCount = 1,
-
         .pinCfg = (whal_Stm32wbGpio_PinCfg[3]) {
             [LED_PIN] = { /* LED */
                 .port = WHAL_STM32WB_GPIO_PORT_B,
@@ -117,11 +118,9 @@ whal_Uart g_whalUart = {
     WHAL_STM32WB55_UART1_DEVICE,
 
     .cfg = &(whal_Stm32wbUart_Cfg) {
-        .clkCtrl = &g_whalClock,
-        .clk = &(whal_Stm32wbRcc_Clk) {WHAL_STM32WB55_UART1_CLOCK},
         .timeout = &g_whalTimeout,
 
-        .baud = 115200,
+        .brr = WHAL_STM32WB_UART_BRR(64000000, 115200),
     },
 };
 
@@ -130,8 +129,6 @@ whal_Flash g_whalFlash = {
     WHAL_STM32WB55_FLASH_DEVICE,
 
     .cfg = &(whal_Stm32wbFlash_Cfg) {
-        .clkCtrl = &g_whalClock,
-        .clk = &(whal_Stm32wbRcc_Clk) {WHAL_STM32WB55_FLASH_CLOCK},
         .timeout = &g_whalTimeout,
 
         .startAddr = 0x08000000,
@@ -144,8 +141,6 @@ whal_Rng g_whalRng = {
     WHAL_STM32WB55_RNG_DEVICE,
 
     .cfg = &(whal_Stm32wbRng_Cfg) {
-        .clkCtrl = &g_whalClock,
-        .clk = &(whal_Stm32wbRcc_Clk) {WHAL_STM32WB55_RNG_CLOCK},
         .timeout = &g_whalTimeout,
     },
 };
@@ -167,8 +162,6 @@ whal_Crypto g_whalCrypto = {
     .opsCount = BOARD_CRYPTO_OP_COUNT,
 
     .cfg = &(whal_Stm32wbAes_Cfg) {
-        .clkCtrl = &g_whalClock,
-        .clk = &(whal_Stm32wbRcc_Clk) {WHAL_STM32WB55_AES1_CLOCK},
         .timeout = &g_whalTimeout,
     },
 };
@@ -196,6 +189,17 @@ whal_Error Board_Init(void)
 {
     whal_Error err;
 
+    /* Enable flash clock and set latency before increasing clock speed */
+    err = whal_Clock_Enable(&g_whalClock, &g_flashClock);
+    if (err) {
+        return err;
+    }
+
+    err = whal_Stm32wbFlash_Ext_SetLatency(&g_whalFlash, WHAL_STM32WB_FLASH_LATENCY_3);
+    if (err) {
+        return err;
+    }
+
     err = whal_Clock_Init(&g_whalClock);
     if (err) {
         return err;
@@ -207,6 +211,13 @@ whal_Error Board_Init(void)
         return err;
     }
 
+    /* Enable peripheral clocks */
+    for (size_t i = 0; i < PERIPHERAL_CLOCK_COUNT; i++) {
+        err = whal_Clock_Enable(&g_whalClock, &g_peripheralClocks[i]);
+        if (err)
+            return err;
+    }
+
     err = whal_Gpio_Init(&g_whalGpio);
     if (err) {
         return err;
@@ -284,6 +295,13 @@ whal_Error Board_Deinit(void)
         return err;
     }
 
+    /* Disable peripheral clocks */
+    for (size_t i = 0; i < PERIPHERAL_CLOCK_COUNT; i++) {
+        err = whal_Clock_Disable(&g_whalClock, &g_peripheralClocks[i]);
+        if (err)
+            return err;
+    }
+
     err = whal_Stm32wbRcc_Ext_EnableHsi48(&g_whalClock, 0);
     if (err) {
         return err;
@@ -294,5 +312,16 @@ whal_Error Board_Deinit(void)
         return err;
     }
 
+    /* Reduce flash latency then disable flash clock */
+    err = whal_Stm32wbFlash_Ext_SetLatency(&g_whalFlash, WHAL_STM32WB_FLASH_LATENCY_0);
+    if (err) {
+        return err;
+    }
+
+    err = whal_Clock_Disable(&g_whalClock, &g_flashClock);
+    if (err) {
+        return err;
+    }
+
     return WHAL_SUCCESS;
 }
diff --git a/docs/adding_a_board.md b/docs/adding_a_board.md
index c8be036..08da55a 100644
--- a/docs/adding_a_board.md
+++ b/docs/adding_a_board.md
@@ -53,7 +53,6 @@ on failure.
 static whal_MyplatformGpio_PinCfg pinCfg[] = { /* ... */ };
 
 static whal_MyplatformGpio_Cfg gpioConfig = {
-    .clkCtrl = &g_whalClock,
     .pinCfg  = pinCfg,
     .pinCount = sizeof(pinCfg) / sizeof(pinCfg[0]),
 };
@@ -63,34 +62,61 @@ whal_Gpio g_whalGpio = {
     .cfg = &gpioConfig,
 };
 
+static const MyPlatformClk g_peripheralClocks[] = {
+    {MY_PLATFORM_GPIO_CLOCK},
+    {MY_PLATFORM_UART_CLOCK},
+};
+#define PERIPHERAL_CLOCK_COUNT \
+    (sizeof(g_peripheralClocks) / sizeof(g_peripheralClocks[0]))
+
 whal_Error Board_Init(void)
 {
     whal_Error err;
 
     err = whal_Clock_Init(&g_whalClock);
-    if (err != WHAL_SUCCESS) return err;
+    if (err)
+        return err;
+
+    for (size_t i = 0; i < PERIPHERAL_CLOCK_COUNT; i++) {
+        err = whal_Clock_Enable(&g_whalClock, &g_peripheralClocks[i]);
+        if (err)
+            return err;
+    }
 
     err = whal_Gpio_Init(&g_whalGpio);
-    if (err != WHAL_SUCCESS) return err;
+    if (err)
+        return err;
 
     err = whal_Uart_Init(&g_whalUart);
-    if (err != WHAL_SUCCESS) return err;
+    if (err)
+        return err;
 
     err = whal_Timer_Init(&g_whalTimer);
-    if (err != WHAL_SUCCESS) return err;
+    if (err)
+        return err;
 
     err = whal_Timer_Start(&g_whalTimer);
-    if (err != WHAL_SUCCESS) return err;
+    if (err)
+        return err;
 
     return WHAL_SUCCESS;
 }
 
 whal_Error Board_Deinit(void)
 {
+    whal_Error err;
+
     whal_Timer_Stop(&g_whalTimer);
     whal_Timer_Deinit(&g_whalTimer);
     whal_Uart_Deinit(&g_whalUart);
     whal_Gpio_Deinit(&g_whalGpio);
+
+    for (size_t i = 0; i < PERIPHERAL_CLOCK_COUNT; i++) {
+        err = whal_Clock_Disable(&g_whalClock, &g_peripheralClocks[i]);
+        if (err)
+            return err;
+    }
+
     whal_Clock_Deinit(&g_whalClock);
     return WHAL_SUCCESS;
 }
diff --git a/docs/getting_started.md b/docs/getting_started.md
index 8fb39d1..d99c9d6 100644
--- a/docs/getting_started.md
+++ b/docs/getting_started.md
@@ -97,12 +97,6 @@ whal_Gpio g_whalGpio = {
     WHAL_STM32WB55_GPIO_DEVICE,
 
     .cfg = &(whal_Stm32wbGpio_Cfg) {
-        .clkCtrl = &g_whalClock,
-        .clk = (const void *[1]) {
-            &(whal_Stm32wbRcc_Clk){WHAL_STM32WB55_GPIOB_CLOCK},
-        },
-        .clkCount = 1,
-
         .pinCfg = (whal_Stm32wbGpio_PinCfg[]) {
             { /* LED */
                 .port = WHAL_STM32WB_GPIO_PORT_B,
@@ -117,17 +111,15 @@ whal_Gpio g_whalGpio = {
 };
 ```
 
-A UART driver might need just a clock reference and baud rate:
+A UART driver might need a pre-computed baud rate register value and a timeout:
 
 ```c
 whal_Uart g_whalUart = {
     WHAL_STM32WB55_UART1_DEVICE,
 
     .cfg = &(whal_Stm32wbUart_Cfg) {
-        .clkCtrl = &g_whalClock,
-        .clk = &(whal_Stm32wbRcc_Clk){WHAL_STM32WB55_UART1_CLOCK},
         .timeout = &g_whalTimeout,
-        .baud = 115200,
+        .brr = WHAL_STM32WB_UART_BRR(64000000, 115200),
     },
 };
 ```
@@ -137,38 +129,65 @@ of configuration options for each driver.
 
 ## Initialization
 
-Peripherals must be initialized in dependency order. The clock controller comes
-first since other peripherals need it to enable their clocks. A typical
-initialization sequence:
+The board is responsible for initializing peripherals in dependency order.
+Drivers do not enable their own clocks or power supplies — the board must
+handle these prerequisites explicitly before calling a driver's Init.
+
+A typical initialization sequence:
+
+1. Do any pre-clock-controller initialization (e.g., flash wait states,
+   power supplies)
+2. Initialize the clock controller
+3. Enable peripheral clocks
+4. Initialize peripheral drivers
+5. Start timers
 
 ```c
-#include <wolfHAL/wolfHAL.h>
+static const MyPlatformClk g_peripheralClocks[] = {
+    {MY_PLATFORM_GPIOB_CLOCK},
+    {MY_PLATFORM_UART1_CLOCK},
+};
+#define PERIPHERAL_CLOCK_COUNT \
+    (sizeof(g_peripheralClocks) / sizeof(g_peripheralClocks[0]))
 
 whal_Error Board_Init(void)
 {
     whal_Error err;
 
     err = whal_Clock_Init(&g_whalClock);
-    if (err != WHAL_SUCCESS) return err;
+    if (err)
+        return err;
+
+    /* Enable peripheral clocks */
+    for (size_t i = 0; i < PERIPHERAL_CLOCK_COUNT; i++) {
+        err = whal_Clock_Enable(&g_whalClock, &g_peripheralClocks[i]);
+        if (err)
+            return err;
+    }
 
+    /* Initialize peripherals */
     err = whal_Gpio_Init(&g_whalGpio);
-    if (err != WHAL_SUCCESS) return err;
+    if (err)
+        return err;
 
     err = whal_Uart_Init(&g_whalUart);
-    if (err != WHAL_SUCCESS) return err;
+    if (err)
+        return err;
 
     err = whal_Timer_Init(&g_whalTimer);
-    if (err != WHAL_SUCCESS) return err;
+    if (err)
+        return err;
 
     err = whal_Timer_Start(&g_whalTimer);
-    if (err != WHAL_SUCCESS) return err;
+    if (err)
+        return err;
 
     return WHAL_SUCCESS;
 }
 ```
 
-On platforms with a supply controller (e.g., PIC32CZ), the supply must be
-initialized before the clock if the PLL depends on it.
+See the board examples in `boards/` for complete initialization sequences
+including platform-specific steps.
 
 ## Using the API
 
@@ -256,13 +275,9 @@ whal_Stm32wbGpio_Set(&g_whalGpio, BOARD_LED_PIN, 1);
 This eliminates the vtable indirection and lets the compiler inline or optimize
 the calls more aggressively.
 
-**Be careful with this approach:** some drivers call other drivers internally
-through the wolfHAL API. For example, a GPIO driver's Init may call
-`whal_Clock_Enable()` to gate the peripheral clock. If you bypass the vtable
-for the clock driver, those internal calls will still go through the vtable
-unless you also modify the driver source. Make sure the drivers your code
-depends on still have a working dispatch path for any functions they call
-internally.
+Register-level drivers do not call other drivers internally, so this works
+without any caveats. Bus-device drivers (e.g., SPI flash) still call their
+bus driver through the vtable.
 
 ## Next Steps
 
diff --git a/docs/writing_a_driver.md b/docs/writing_a_driver.md
index 23f5247..34abbdd 100644
--- a/docs/writing_a_driver.md
+++ b/docs/writing_a_driver.md
@@ -49,6 +49,21 @@ static whal_Error whal_MyplatformFoo_Init(whal_Foo *fooDev)
 }
 ```
 
+### No Cross-Driver Calls
+
+Register-level drivers must not call other wolfHAL drivers. A UART driver
+must not call the clock driver to enable its own clock, and a clock driver
+must not call the flash driver to set wait states. The board is responsible
+for all cross-peripheral dependencies — enabling clocks, configuring power
+supplies, and setting flash latency — before calling a driver's Init.
+
+This ensures drivers are pure register-level abstractions with no hidden
+dependencies, making them usable with or without the vtable dispatch layer.
+
+Bus-device drivers (e.g., SPI flash) are the exception — they inherently
+need to call their underlying bus driver (SPI, I2C) to communicate with the
+device.
+
 ### Register Access
 
 wolfHAL provides register access helpers in `wolfHAL/regmap.h`:
@@ -216,9 +231,6 @@ ordering requirements.
 
 Configure and start the system clock source. This usually involves:
 
-- Setting flash wait states **before** increasing the clock frequency (critical
-  for correct operation — the CPU will fault if flash is too slow for the new
-  clock speed)
 - Configuring the clock source (oscillator parameters, PLL multipliers and
   dividers, etc.)
 - Enabling the clock source and waiting for it to stabilize (e.g., polling a
@@ -226,6 +238,10 @@ Configure and start the system clock source. This usually involves:
 - Switching the system clock mux to the new source
 - Configuring any required clock dividers (CPU, bus, peripheral)
 
+The board is responsible for setting flash wait states and enabling power
+supplies before calling Init. The clock driver should only touch clock
+registers.
+
 The configuration struct should contain all parameters needed to fully describe
 the desired clock tree (source selection, divider values, PLL coefficients,
 etc.).
@@ -237,7 +253,8 @@ Shut down the clock source safely. This typically means:
 - Switching back to a safe default clock source (e.g., an internal RC
   oscillator) before disabling the active source
 - Disabling PLLs or high-speed oscillators
-- Reducing flash wait states to match the slower clock
+
+The board is responsible for reducing flash wait states after Deinit returns.
 
 ### Enable
 
@@ -276,19 +293,20 @@ index in that table (not raw hardware pin/port numbers).
 Configure all pins described in the device's configuration. For each pin this
 typically involves:
 
-- Enabling the clock for the pin's GPIO port (via the clock driver)
 - Setting the pin mode (input, output, alternate function, analog)
 - Configuring output type (push-pull or open-drain), speed, and pull
   resistors as applicable
 - Setting the alternate function mux if the pin is in alternate function mode
   (e.g., for UART TX/RX or SPI signals)
 
+The board must enable GPIO port clocks before calling Init.
+
 If any pin configuration fails, Init should stop and return an error.
 
 ### Deinit
 
-Disable GPIO port clocks. Pin registers do not need to be explicitly reset
-since disabling the clock effectively resets the port.
+Reset GPIO pin configurations as needed. The board is responsible for
+disabling GPIO port clocks after Deinit.
 
 ### Get
 
@@ -320,14 +338,15 @@ does not return until all requested bytes have been received.
 
 Configure and enable the UART peripheral:
 
-- Enable the peripheral clock (via the clock driver)
-- Query the clock frequency to calculate the baud rate register value. Some
-  platforms require a simple division (e.g., BRR = clock / baud), while others
-  use a more complex formula involving oversampling ratios
+- Write the baud rate register value from the configuration. The board
+  pre-computes this value from the clock frequency and desired baud rate
+  (e.g., `BRR = clockFreq / baud`)
 - Configure word length, stop bits, and parity as needed
 - Enable the transmitter and receiver
 - Enable the UART peripheral
 
+The board must enable the peripheral clock before calling Init.
+
 On platforms with synchronization requirements (e.g., Microchip SERCOM), the
 driver must poll synchronization busy flags after writing to certain registers
 before proceeding.
@@ -338,7 +357,6 @@ Disable the UART peripheral:
 
 - Disable the transmitter and receiver
 - Clear the baud rate register
-- Disable the peripheral clock
 
 ### Send
 
@@ -375,16 +393,19 @@ peripheral.
 
 Configure and enable the SPI peripheral:
 
-- Enable the peripheral clock
 - Set master mode and configure slave select management (typically software-
   managed via GPIO)
 - Set the data frame size (usually 8-bit)
 - Do not configure mode or baud rate here — these are applied per-transfer via
   `spiComCfg`
 
+The board must enable the peripheral clock before calling Init. The
+configuration struct should include the peripheral clock frequency so the
+driver can compute baud rate prescalers during transfers.
+
 ### Deinit
 
-Disable the SPI peripheral and its clock.
+Disable the SPI peripheral.
 
 ### SendRecv
 
@@ -423,13 +444,13 @@ protection that the driver must handle.
 
 ### Init
 
-Initialize the flash controller. This typically just enables the flash
-interface clock. Some platforms may also need to clear error flags or release
-hardware mutex locks.
+Initialize the flash controller. This may involve clearing error flags or
+releasing hardware mutex locks. The board must enable the flash interface clock
+before calling Init.
 
 ### Deinit
 
-Release flash controller resources and disable the clock.
+Release flash controller resources.
 
 ### Lock
 
@@ -539,13 +560,13 @@ hardware typically uses an analog entropy source to produce true random numbers.
 
 ### Init
 
-Initialize the RNG hardware. This usually involves enabling the peripheral
-clock. Some platforms may require enabling additional clock sources that feed
-the RNG's entropy source (e.g., a dedicated internal oscillator).
+Initialize the RNG hardware. The board must enable the peripheral clock (and
+any additional clock sources the RNG's entropy source requires) before calling
+Init.
 
 ### Deinit
 
-Shut down the RNG hardware and disable its clock.
+Shut down the RNG hardware.
 
 ### Generate
 
@@ -596,8 +617,8 @@ table.
 
 ### Init / Deinit
 
-Init should enable the peripheral clock. Deinit should disable the AES
-peripheral and its clock.
+The board must enable the peripheral clock before calling Init. Deinit should
+disable the crypto accelerator peripheral.
 
 ### Operations
 
@@ -658,9 +679,9 @@ pointer to a supply descriptor (typically containing a register offset and bit
 mask). The driver sets the appropriate enable bit in the supply control
 register.
 
-Supply enable is often a prerequisite for other driver initialization — for
-example, a PLL's analog voltage regulator must be enabled before the PLL can be
-configured and locked.
+The board calls Supply Enable before initializing peripherals that depend on
+the supply — for example, enabling a PLL's analog voltage regulator before
+calling Clock Init.
 
 ### Disable
 
diff --git a/src/clock/pic32cz_clock.c b/src/clock/pic32cz_clock.c
index dd969cf..c7c0b58 100644
--- a/src/clock/pic32cz_clock.c
+++ b/src/clock/pic32cz_clock.c
@@ -104,7 +104,7 @@ whal_Error whal_Pic32czClockPll_Init(whal_Clock *clkDev)
     size_t PLLxPOSTDIVA_REG;
     size_t status;
 
-    if (!clkDev) {
+    if (!clkDev || !clkDev->cfg) {
         return WHAL_EINVAL;
     }
 
@@ -118,9 +118,6 @@ whal_Error whal_Pic32czClockPll_Init(whal_Clock *clkDev)
     PLLxREFDIV_REG = OSCCTRL_PLLxREFDIV_REG(oscCtrlCfg->pllInst);
     PLLxPOSTDIVA_REG = OSCCTRL_PLLxPOSTDIVA_REG(oscCtrlCfg->pllInst);
 
-    /* Enable power supply for the PLL */
-    whal_Supply_Enable(oscCtrlCfg->supplyCtrl, oscCtrlCfg->supply);
-
     /* Configure PLL feedback divider (sets VCO multiplication factor) */
     whal_Reg_Update(clkDev->regmap.base, PLLxFBDIV_REG, OSCCTRL_PLLxFBDIV_Msk,
                     whal_SetBits(OSCCTRL_PLLxFBDIV_Msk, OSCCTRL_PLLxFBDIV_Pos, oscCtrlCfg->fbDiv));
diff --git a/src/clock/stm32wb_rcc.c b/src/clock/stm32wb_rcc.c
index 94da36d..0a13a5a 100644
--- a/src/clock/stm32wb_rcc.c
+++ b/src/clock/stm32wb_rcc.c
@@ -1,7 +1,6 @@
 #include <wolfHAL/error.h>
 #include <wolfHAL/clock/clock.h>
 #include <wolfHAL/clock/stm32wb_rcc.h>
-#include <wolfHAL/flash/stm32wb_flash.h>
 #include <wolfHAL/regmap.h>
 #include <wolfHAL/bitops.h>
 
@@ -142,7 +141,6 @@
 
 whal_Error whal_Stm32wbRccPll_Init(whal_Clock *clkDev)
 {
-    whal_Error err;
     whal_Stm32wbRcc_Cfg *cfg;
 
     if (!clkDev || !clkDev->cfg) {
@@ -152,15 +150,6 @@ whal_Error whal_Stm32wbRccPll_Init(whal_Clock *clkDev)
     cfg = (whal_Stm32wbRcc_Cfg *)clkDev->cfg;
     whal_Stm32wbRcc_PllClkCfg *pllCfg = cfg->sysClkCfg;
 
-    /*
-     * Flash latency must be set BEFORE increasing clock speed to ensure
-     * the flash can keep up with the new frequency.
-     */
-    err = whal_Stm32wbFlash_Ext_SetLatency(cfg->flash, cfg->flashLatency);
-    if (err) {
-        return err;
-    }
-
     /* Select system clock source (PLL in this case) */
     whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk,
                     whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, cfg->sysClkSrc));
@@ -186,7 +175,6 @@ whal_Error whal_Stm32wbRccPll_Init(whal_Clock *clkDev)
 
 whal_Error whal_Stm32wbRccMsi_Init(whal_Clock *clkDev)
 {
-    whal_Error err;
     whal_Stm32wbRcc_Cfg *cfg;
 
     if (!clkDev || !clkDev->cfg) {
@@ -196,12 +184,6 @@ whal_Error whal_Stm32wbRccMsi_Init(whal_Clock *clkDev)
     cfg = (whal_Stm32wbRcc_Cfg *)clkDev->cfg;
     whal_Stm32wbRcc_MsiClkCfg *msiCfg = cfg->sysClkCfg;
 
-    /* Set flash latency for target MSI frequency */
-    err = whal_Stm32wbFlash_Ext_SetLatency(cfg->flash, cfg->flashLatency);
-    if (err) {
-        return err;
-    }
-
     /* Select MSI as system clock source */
     whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk,
                     whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, WHAL_STM32WB_RCC_SYSCLK_SRC_MSI));
@@ -215,14 +197,10 @@ whal_Error whal_Stm32wbRccMsi_Init(whal_Clock *clkDev)
 
 whal_Error whal_Stm32wbRccPll_Deinit(whal_Clock *clkDev)
 {
-    whal_Stm32wbRcc_Cfg *cfg;
-
-    if (!clkDev || !clkDev->cfg) {
+    if (!clkDev) {
         return WHAL_EINVAL;
     }
 
-    cfg = (whal_Stm32wbRcc_Cfg *)clkDev->cfg;
-
     /* Switch back to MSI before disabling PLL */
     whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk,
                     whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, WHAL_STM32WB_RCC_SYSCLK_SRC_MSI));
@@ -236,30 +214,21 @@ whal_Error whal_Stm32wbRccPll_Deinit(whal_Clock *clkDev)
                     RCC_CR_PLLON_Msk,
                     whal_SetBits(RCC_CR_PLLON_Msk, RCC_CR_PLLON_Pos, 0));
 
-    /* Reduce flash latency now that clock is slower */
-    whal_Stm32wbFlash_Ext_SetLatency(cfg->flash, WHAL_STM32WB_FLASH_LATENCY_0);
-
     return WHAL_SUCCESS;
 }
 
 whal_Error whal_Stm32wbRccMsi_Deinit(whal_Clock *clkDev)
 {
-    whal_Stm32wbRcc_Cfg *cfg;
-
-    if (!clkDev || !clkDev->cfg) {
+    if (!clkDev) {
         return WHAL_EINVAL;
     }
 
-    cfg = (whal_Stm32wbRcc_Cfg *)clkDev->cfg;
-
     whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk,
                     whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, WHAL_STM32WB_RCC_SYSCLK_SRC_MSI));
 
     whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_MSIRANGE_Msk,
                     whal_SetBits(RCC_CR_MSIRANGE_Msk, RCC_CR_MSIRANGE_Pos, WHAL_STM32WB_RCC_MSIRANGE_4MHz));
 
-    whal_Stm32wbFlash_Ext_SetLatency(cfg->flash, WHAL_STM32WB_FLASH_LATENCY_0);
-
     return WHAL_SUCCESS;
 }
 
diff --git a/src/crypto/stm32wb_aes.c b/src/crypto/stm32wb_aes.c
index df71af0..349cde9 100644
--- a/src/crypto/stm32wb_aes.c
+++ b/src/crypto/stm32wb_aes.c
@@ -1,7 +1,6 @@
 #include <stdint.h>
 #include <wolfHAL/crypto/stm32wb_aes.h>
 #include <wolfHAL/crypto/crypto.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/error.h>
 #include <wolfHAL/regmap.h>
 #include <wolfHAL/bitops.h>
@@ -152,43 +151,23 @@ static whal_Error WaitForCCF(size_t base, whal_Timeout *timeout)
 
 whal_Error whal_Stm32wbAes_Init(whal_Crypto *cryptoDev)
 {
-    whal_Error err;
-    const whal_Stm32wbAes_Cfg *cfg;
-
     if (!cryptoDev || !cryptoDev->cfg) {
         return WHAL_EINVAL;
     }
 
-    cfg = (const whal_Stm32wbAes_Cfg *)cryptoDev->cfg;
-
-    err = whal_Clock_Enable(cfg->clkCtrl, cfg->clk);
-    if (err != WHAL_SUCCESS) {
-        return err;
-    }
-
     return WHAL_SUCCESS;
 }
 
 whal_Error whal_Stm32wbAes_Deinit(whal_Crypto *cryptoDev)
 {
-    whal_Error err;
-    const whal_Stm32wbAes_Cfg *cfg;
-
     if (!cryptoDev || !cryptoDev->cfg) {
         return WHAL_EINVAL;
     }
 
-    cfg = (const whal_Stm32wbAes_Cfg *)cryptoDev->cfg;
-
     /* Disable AES peripheral */
     whal_Reg_Update(cryptoDev->regmap.base, AES_CR_REG, AES_CR_EN_Msk,
                     whal_SetBits(AES_CR_EN_Msk, AES_CR_EN_Pos, 0));
 
-    err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk);
-    if (err != WHAL_SUCCESS) {
-        return err;
-    }
-
     return WHAL_SUCCESS;
 }
 
diff --git a/src/flash/pic32cz_flash.c b/src/flash/pic32cz_flash.c
index d975120..e9c5008 100644
--- a/src/flash/pic32cz_flash.c
+++ b/src/flash/pic32cz_flash.c
@@ -246,16 +246,17 @@ whal_Error whal_Pic32czFlash_Read(whal_Flash *flashDev, size_t addr, uint8_t *da
                              size_t dataSz)
 {
     const whal_Regmap *reg;
-    whal_Pic32czFlash_Cfg *cfg = flashDev->cfg;
+    whal_Pic32czFlash_Cfg *cfg;
     uint8_t *flashAddr = (uint8_t *)addr;
     whal_Error err;
     size_t i;
 
-    if (!flashDev || !data) {
+    if (!flashDev || !flashDev->cfg || !data) {
         return WHAL_EINVAL;
     }
 
     reg = &flashDev->regmap;
+    cfg = flashDev->cfg;
 
 
     err = whal_Pic32czFlash_MutexLock(reg, cfg->timeout);
@@ -276,15 +277,17 @@ whal_Error whal_Pic32czFlash_Write(whal_Flash *flashDev, size_t addr, const uint
                               size_t dataSz)
 {
     const whal_Regmap *reg;
-    whal_Pic32czFlash_Cfg *cfg = flashDev->cfg;
+    whal_Pic32czFlash_Cfg *cfg;
     const uint32_t *src;
     whal_Error err;
     size_t offset = 0;
 
-    if (!flashDev || !data) {
+    if (!flashDev || !flashDev->cfg || !data) {
         return WHAL_EINVAL;
     }
 
+    cfg = flashDev->cfg;
+
     /* Require double-word alignment */
     if ((addr & 0x7) || (dataSz & 0x7)) {
         return WHAL_EINVAL;
@@ -353,15 +356,16 @@ whal_Error whal_Pic32czFlash_Write(whal_Flash *flashDev, size_t addr, const uint
 whal_Error whal_Pic32czFlash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz)
 {
     const whal_Regmap *reg;
-    whal_Pic32czFlash_Cfg *cfg = flashDev->cfg;
+    whal_Pic32czFlash_Cfg *cfg;
     whal_Error err;
     size_t pageAddr;
     size_t endAddr;
 
-    if (!flashDev) {
+    if (!flashDev || !flashDev->cfg) {
         return WHAL_EINVAL;
     }
 
+    cfg = flashDev->cfg;
     reg = &flashDev->regmap;
 
     /* Align down to page boundary */
diff --git a/src/flash/stm32wb_flash.c b/src/flash/stm32wb_flash.c
index b2ee071..cdc1bde 100644
--- a/src/flash/stm32wb_flash.c
+++ b/src/flash/stm32wb_flash.c
@@ -1,6 +1,4 @@
 #include <stdint.h>
-#include <wolfHAL/clock/clock.h>
-#include <wolfHAL/clock/stm32wb_rcc.h>
 #include <wolfHAL/flash/stm32wb_flash.h>
 #include <wolfHAL/flash/flash.h>
 #include <wolfHAL/error.h>
@@ -92,36 +90,30 @@
 
 whal_Error whal_Stm32wbFlash_Init(whal_Flash *flashDev)
 {
-    whal_Error err;
-    whal_Stm32wbFlash_Cfg *cfg = flashDev->cfg;
-
-    err = whal_Clock_Enable(cfg->clkCtrl, cfg->clk);
-    if (err) {
-        return err;
-    }
+    (void)flashDev;
 
     return WHAL_SUCCESS;
 }
 
 whal_Error whal_Stm32wbFlash_Deinit(whal_Flash *flashDev)
 {
-    whal_Error err;
-    whal_Stm32wbFlash_Cfg *cfg = flashDev->cfg;
-
-    err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk);
-    if (err) {
-        return err;
-    }
+    (void)flashDev;
 
     return WHAL_SUCCESS;
 }
 
 whal_Error whal_Stm32wbFlash_Lock(whal_Flash *flashDev, size_t addr, size_t len)
 {
+    const whal_Regmap *regmap;
+
     (void)addr;
     (void)len;
 
-    const whal_Regmap *regmap = &flashDev->regmap;
+    if (!flashDev) {
+        return WHAL_EINVAL;
+    }
+
+    regmap = &flashDev->regmap;
 
     /* Setting LOCK bit prevents further flash modifications until next unlock */
     whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_LOCK_Msk,
@@ -132,10 +124,16 @@ whal_Error whal_Stm32wbFlash_Lock(whal_Flash *flashDev, size_t addr, size_t len)
 
 whal_Error whal_Stm32wbFlash_Unlock(whal_Flash *flashDev, size_t addr, size_t len)
 {
+    const whal_Regmap *regmap;
+
     (void)addr;
     (void)len;
 
-    const whal_Regmap *regmap = &flashDev->regmap;
+    if (!flashDev) {
+        return WHAL_EINVAL;
+    }
+
+    regmap = &flashDev->regmap;
 
     /*
      * Unlock sequence: write KEY1 then KEY2 to KEYR register.
@@ -169,11 +167,18 @@ whal_Error whal_Stm32wbFlash_Read(whal_Flash *flashDev, size_t addr, uint8_t *da
 static whal_Error whal_Stm32wbFlash_WriteOrErase(whal_Flash *flashDev, size_t addr, const uint8_t *data,
                                             size_t dataSz, uint8_t write)
 {
-    whal_Stm32wbFlash_Cfg *cfg = flashDev->cfg;
-    const whal_Regmap *regmap = &flashDev->regmap;
+    whal_Stm32wbFlash_Cfg *cfg;
+    const whal_Regmap *regmap;
     size_t bsy;
     size_t pesd;
 
+    if (!flashDev || !flashDev->cfg) {
+        return WHAL_EINVAL;
+    }
+
+    cfg = flashDev->cfg;
+    regmap = &flashDev->regmap;
+
     /* Validate address alignment and bounds */
     if (addr & 0xf || addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) {
         return WHAL_EINVAL;
diff --git a/src/gpio/pic32cz_gpio.c b/src/gpio/pic32cz_gpio.c
index 6729e18..3b61cb9 100644
--- a/src/gpio/pic32cz_gpio.c
+++ b/src/gpio/pic32cz_gpio.c
@@ -53,7 +53,7 @@
 
 whal_Error whal_Pic32czGpio_Init(whal_Gpio *gpioDev)
 {
-    if (!gpioDev) {
+    if (!gpioDev || !gpioDev->cfg) {
         return WHAL_EINVAL;
     }
 
@@ -133,11 +133,16 @@ whal_Error whal_Pic32czGpio_Deinit(whal_Gpio *gpioDev)
 
 whal_Error whal_Pic32czGpio_Get(whal_Gpio *gpioDev, size_t pin, size_t *value)
 {
-    if (!gpioDev || !value) {
+    if (!gpioDev || !gpioDev->cfg || !value) {
         return WHAL_EINVAL;
     }
 
     const whal_Pic32czGpio_Cfg *cfg = gpioDev->cfg;
+
+    if (pin >= cfg->pinCfgCount) {
+        return WHAL_EINVAL;
+    }
+
     whal_Pic32czGpio_PinCfg *pinCfg = &cfg->pinCfg[pin];
     size_t pinMask = (1UL << (pinCfg->pin));
     size_t reg;
@@ -161,11 +166,16 @@ whal_Error whal_Pic32czGpio_Get(whal_Gpio *gpioDev, size_t pin, size_t *value)
 
 whal_Error whal_Pic32czGpio_Set(whal_Gpio *gpioDev, size_t pin, size_t value)
 {
-    if (!gpioDev) {
+    if (!gpioDev || !gpioDev->cfg) {
         return WHAL_EINVAL;
     }
 
     const whal_Pic32czGpio_Cfg *cfg = gpioDev->cfg;
+
+    if (pin >= cfg->pinCfgCount) {
+        return WHAL_EINVAL;
+    }
+
     whal_Pic32czGpio_PinCfg *pinCfg = &cfg->pinCfg[pin];
     size_t pinMask = (1UL << (pinCfg->pin));
 
diff --git a/src/gpio/stm32wb_gpio.c b/src/gpio/stm32wb_gpio.c
index 433da0c..a2f063b 100644
--- a/src/gpio/stm32wb_gpio.c
+++ b/src/gpio/stm32wb_gpio.c
@@ -109,14 +109,6 @@ whal_Error whal_Stm32wbGpio_Init(whal_Gpio *gpioDev)
     cfg = (whal_Stm32wbGpio_Cfg *)gpioDev->cfg;
     pinCfg = cfg->pinCfg;
 
-    for (size_t i = 0; i < cfg->clkCount; ++i) {
-        /* Enable GPIO port clock before accessing registers */
-        err = whal_Clock_Enable(cfg->clkCtrl, cfg->clk[i]);
-        if (err) {
-            return err;
-        }
-    }
-
     /* Initialize each pin in the configuration array */
     for (size_t pin = 0; pin < cfg->pinCount; ++pin) {
         err = whal_Stm32wbGpio_InitPin(gpioDev, &pinCfg[pin]);
@@ -130,18 +122,7 @@ whal_Error whal_Stm32wbGpio_Init(whal_Gpio *gpioDev)
 
 whal_Error whal_Stm32wbGpio_Deinit(whal_Gpio *gpioDev)
 {
-    whal_Error err;
-    whal_Stm32wbGpio_Cfg *cfg;
-
-    cfg = (whal_Stm32wbGpio_Cfg *)gpioDev->cfg;
-
-    for (size_t i = 0; i < cfg->clkCount; ++i) {
-        /* Disable GPIO port clock */
-        err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk[i]);
-        if (err) {
-            return err;
-        }
-    }
+    (void)gpioDev;
 
     return WHAL_SUCCESS;
 }
diff --git a/src/rng/stm32wb_rng.c b/src/rng/stm32wb_rng.c
index 685cf6d..7fccf09 100644
--- a/src/rng/stm32wb_rng.c
+++ b/src/rng/stm32wb_rng.c
@@ -1,7 +1,6 @@
 #include <stdint.h>
 #include <wolfHAL/rng/stm32wb_rng.h>
 #include <wolfHAL/rng/rng.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/error.h>
 #include <wolfHAL/regmap.h>
 #include <wolfHAL/bitops.h>
@@ -44,57 +43,40 @@
 
 whal_Error whal_Stm32wbRng_Init(whal_Rng *rngDev)
 {
-    whal_Error err;
-    whal_Stm32wbRng_Cfg *cfg;
-
     if (!rngDev || !rngDev->cfg) {
         return WHAL_EINVAL;
     }
 
-    cfg = (whal_Stm32wbRng_Cfg *)rngDev->cfg;
-
-    err = whal_Clock_Enable(cfg->clkCtrl, cfg->clk);
-    if (err != WHAL_SUCCESS) {
-        return err;
-    }
-
     return WHAL_SUCCESS;
 }
 
 whal_Error whal_Stm32wbRng_Deinit(whal_Rng *rngDev)
 {
-    whal_Error err;
-
     if (!rngDev || !rngDev->cfg) {
         return WHAL_EINVAL;
     }
 
-    whal_Stm32wbRng_Cfg *cfg = (whal_Stm32wbRng_Cfg *)rngDev->cfg;
-
-    err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk);
-    if (err) {
-        return err;
-    }
-
     return WHAL_SUCCESS;
 }
 
 whal_Error whal_Stm32wbRng_Generate(whal_Rng *rngDev, uint8_t *rngData, size_t rngDataSz)
 {
-
     whal_Error err = WHAL_SUCCESS;
-    whal_Stm32wbRng_Cfg *cfg = (whal_Stm32wbRng_Cfg *)rngDev->cfg;
-    const whal_Regmap *reg = &rngDev->regmap;
+    whal_Stm32wbRng_Cfg *cfg;
+    const whal_Regmap *reg;
     size_t sr;
     size_t offset = 0;
-#ifdef WHAL_CFG_NO_TIMEOUT
-    (void)(cfg);
-#endif
 
-    if (!rngDev || !rngData) {
+    if (!rngDev || !rngDev->cfg || !rngData) {
         return WHAL_EINVAL;
     }
 
+    cfg = (whal_Stm32wbRng_Cfg *)rngDev->cfg;
+    reg = &rngDev->regmap;
+#ifdef WHAL_CFG_NO_TIMEOUT
+    (void)(cfg);
+#endif
+
     /* Enable the RNG peripheral */
     whal_Reg_Update(reg->base, RNG_CR_REG, RNG_CR_RNGEN_Msk,
                     whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 1));
diff --git a/src/spi/stm32wb_spi.c b/src/spi/stm32wb_spi.c
index 779cbd0..e4b9a5b 100644
--- a/src/spi/stm32wb_spi.c
+++ b/src/spi/stm32wb_spi.c
@@ -1,7 +1,6 @@
 #include <stdint.h>
 #include <wolfHAL/spi/stm32wb_spi.h>
 #include <wolfHAL/spi/spi.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/error.h>
 #include <wolfHAL/regmap.h>
 #include <wolfHAL/bitops.h>
@@ -93,16 +92,9 @@ static void whal_Stm32wbSpi_ApplyComCfg(const whal_Regmap *reg,
                                         whal_Stm32wbSpi_Cfg *cfg,
                                         whal_Stm32wbSpi_ComCfg *comCfg)
 {
-    whal_Error err;
-    size_t pclk;
     uint32_t cpol, cpha, br;
 
-    err = whal_Clock_GetRate(cfg->clkCtrl, &pclk);
-    if (err) {
-        return;
-    }
-
-    br = whal_Stm32wbSpi_CalcBr(pclk, comCfg->baud);
+    br = whal_Stm32wbSpi_CalcBr(cfg->pclk, comCfg->baud);
 
     cpol = (comCfg->mode >> 1) & 1;
     cpha = comCfg->mode & 1;
@@ -125,8 +117,6 @@ static void whal_Stm32wbSpi_ApplyComCfg(const whal_Regmap *reg,
 
 whal_Error whal_Stm32wbSpi_Init(whal_Spi *spiDev)
 {
-    whal_Error err;
-    whal_Stm32wbSpi_Cfg *cfg;
     const whal_Regmap *reg;
 
     if (!spiDev || !spiDev->cfg) {
@@ -134,12 +124,6 @@ whal_Error whal_Stm32wbSpi_Init(whal_Spi *spiDev)
     }
 
     reg = &spiDev->regmap;
-    cfg = (whal_Stm32wbSpi_Cfg *)spiDev->cfg;
-
-    err = whal_Clock_Enable(cfg->clkCtrl, cfg->clk);
-    if (err != WHAL_SUCCESS) {
-        return err;
-    }
 
     /* Master mode with software slave management */
     whal_Reg_Update(reg->base, SPI_CR1_REG,
@@ -159,26 +143,18 @@ whal_Error whal_Stm32wbSpi_Init(whal_Spi *spiDev)
 
 whal_Error whal_Stm32wbSpi_Deinit(whal_Spi *spiDev)
 {
-    whal_Error err;
     const whal_Regmap *reg;
-    whal_Stm32wbSpi_Cfg *cfg;
 
     if (!spiDev || !spiDev->cfg) {
         return WHAL_EINVAL;
     }
 
     reg = &spiDev->regmap;
-    cfg = (whal_Stm32wbSpi_Cfg *)spiDev->cfg;
 
     /* Disable SPI */
     whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk,
                     whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0));
 
-    err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk);
-    if (err) {
-        return err;
-    }
-
     return WHAL_SUCCESS;
 }
 
diff --git a/src/uart/pic32cz_uart.c b/src/uart/pic32cz_uart.c
index 8b398e0..d3e9b47 100644
--- a/src/uart/pic32cz_uart.c
+++ b/src/uart/pic32cz_uart.c
@@ -1,7 +1,6 @@
 #include <stdint.h>
 #include <wolfHAL/uart/pic32cz_uart.h>
 #include <wolfHAL/uart/uart.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/error.h>
 #include <wolfHAL/regmap.h>
 #include <wolfHAL/bitops.h>
@@ -166,19 +165,13 @@ whal_Error whal_Pic32czUart_Init(whal_Uart *uartDev)
     whal_Pic32czUart_Cfg *cfg;
     const whal_Regmap *reg;
 
-    if (!uartDev) {
+    if (!uartDev || !uartDev->cfg) {
         return WHAL_EINVAL;
     }
 
     reg = &uartDev->regmap;
     cfg = (whal_Pic32czUart_Cfg *)uartDev->cfg;
 
-    /* Enable peripheral clock */
-    err = whal_Clock_Enable(cfg->clkCtrl, cfg->clk);
-    if (err != WHAL_SUCCESS) {
-        return err;
-    }
-
     /* Configure CTRLA: internal clock, async mode, LSB first, 16x sampling */
     whal_Reg_Update(reg->base, USART_CTRLA_REG,
                     USART_CTRLA_MODE_Msk |
@@ -248,7 +241,7 @@ whal_Error whal_Pic32czUart_Deinit(whal_Uart *uartDev)
     const whal_Regmap *reg;
     whal_Pic32czUart_Cfg *cfg;
 
-    if (!uartDev) {
+    if (!uartDev || !uartDev->cfg) {
         return WHAL_EINVAL;
     }
 
@@ -278,12 +271,6 @@ whal_Error whal_Pic32czUart_Deinit(whal_Uart *uartDev)
     if (err != WHAL_SUCCESS)
         return err;
 
-    /* Disable peripheral clock */
-    err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk);
-    if (err != WHAL_SUCCESS) {
-        return err;
-    }
-
     return WHAL_SUCCESS;
 }
 
@@ -294,7 +281,7 @@ whal_Error whal_Pic32czUart_Send(whal_Uart *uartDev, const void *data, size_t da
     const uint8_t *buf = data;
     whal_Error err;
 
-    if (!uartDev || !data) {
+    if (!uartDev || !uartDev->cfg || !data) {
         return WHAL_EINVAL;
     }
 
@@ -336,7 +323,7 @@ whal_Error whal_Pic32czUart_Recv(whal_Uart *uartDev, void *data, size_t dataSz)
     whal_Pic32czUart_Cfg *cfg;
     uint8_t *buf = data;
 
-    if (!uartDev || !data) {
+    if (!uartDev || !uartDev->cfg || !data) {
         return WHAL_EINVAL;
     }
 
diff --git a/src/uart/stm32wb_uart.c b/src/uart/stm32wb_uart.c
index 16bfc2e..75f4b8a 100644
--- a/src/uart/stm32wb_uart.c
+++ b/src/uart/stm32wb_uart.c
@@ -1,7 +1,6 @@
 #include <stdint.h>
 #include <wolfHAL/uart/stm32wb_uart.h>
 #include <wolfHAL/uart/uart.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/error.h>
 #include <wolfHAL/regmap.h>
 #include <wolfHAL/bitops.h>
@@ -41,25 +40,18 @@
 
 whal_Error whal_Stm32wbUart_Init(whal_Uart *uartDev)
 {
-    whal_Error err;
     whal_Stm32wbUart_Cfg *cfg;
-    const whal_Regmap *reg = &uartDev->regmap;
-    size_t clockFreq;
+    const whal_Regmap *reg;
     uint32_t brr;
 
-    cfg = (whal_Stm32wbUart_Cfg *)uartDev->cfg;
-
-    err = whal_Clock_Enable(cfg->clkCtrl, cfg->clk);
-    if (err != WHAL_SUCCESS) {
-        return err;
+    if (!uartDev || !uartDev->cfg) {
+        return WHAL_EINVAL;
     }
 
-    err = whal_Clock_GetRate(cfg->clkCtrl, &clockFreq);
-    if (err != WHAL_SUCCESS) {
-        return err;
-    }
+    reg = &uartDev->regmap;
+    cfg = (whal_Stm32wbUart_Cfg *)uartDev->cfg;
 
-    brr = (clockFreq / cfg->baud);
+    brr = cfg->brr;
 
     whal_Reg_Update(reg->base, UART_BRR_REG,
                     UART_BRR_Msk,
@@ -73,45 +65,15 @@ whal_Error whal_Stm32wbUart_Init(whal_Uart *uartDev)
     return WHAL_SUCCESS;
 }
 
-whal_Error whal_Stm32wbLpuart_Init(whal_Uart *uartDev)
+whal_Error whal_Stm32wbUart_Deinit(whal_Uart *uartDev)
 {
-    whal_Error err;
-    whal_Stm32wbUart_Cfg *cfg;
-    const whal_Regmap *reg = &uartDev->regmap;
-    size_t clockFreq;
-    uint32_t brr;
-
-    cfg = (whal_Stm32wbUart_Cfg *)uartDev->cfg;
-
-    err = whal_Clock_Enable(cfg->clkCtrl, cfg->clk);
-    if (err != WHAL_SUCCESS) {
-        return err;
-    }
+    const whal_Regmap *reg;
 
-    err = whal_Clock_GetRate(cfg->clkCtrl, &clockFreq);
-    if (err != WHAL_SUCCESS) {
-        return err;
+    if (!uartDev) {
+        return WHAL_EINVAL;
     }
 
-    brr = (clockFreq / cfg->baud) * 256;
-
-    whal_Reg_Update(reg->base, UART_BRR_REG,
-                    UART_BRR_Msk,
-                    whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, brr));
-    whal_Reg_Update(reg->base, UART_CR1_REG,
-                    UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk,
-                    whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) |
-                    whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) |
-                    whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 1));
-
-    return WHAL_SUCCESS;
-}
-
-whal_Error whal_Stm32wbUart_Deinit(whal_Uart *uartDev)
-{
-    whal_Error err;
-    const whal_Regmap *reg = &uartDev->regmap;
-    whal_Stm32wbUart_Cfg *cfg = (whal_Stm32wbUart_Cfg *)uartDev->cfg;
+    reg = &uartDev->regmap;
 
     whal_Reg_Update(reg->base, UART_CR1_REG,
                     UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk,
@@ -123,20 +85,22 @@ whal_Error whal_Stm32wbUart_Deinit(whal_Uart *uartDev)
                           UART_BRR_Msk,
                           whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, 0));
 
-    err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk);
-    if (err) {
-        return err;
-    }
-
     return WHAL_SUCCESS;
 }
 
 whal_Error whal_Stm32wbUart_Send(whal_Uart *uartDev, const void *data, size_t dataSz)
 {
-    const whal_Regmap *reg = &uartDev->regmap;
-    whal_Stm32wbUart_Cfg *cfg = (whal_Stm32wbUart_Cfg *)uartDev->cfg;
+    const whal_Regmap *reg;
+    whal_Stm32wbUart_Cfg *cfg;
     const uint8_t *buf = data;
 
+    if (!uartDev || !uartDev->cfg || !data) {
+        return WHAL_EINVAL;
+    }
+
+    reg = &uartDev->regmap;
+    cfg = (whal_Stm32wbUart_Cfg *)uartDev->cfg;
+
     for (size_t i = 0; i < dataSz; ++i) {
         whal_Error err;
         whal_Reg_Update(reg->base, UART_TDR_REG, UART_TDR_Msk,
@@ -153,9 +117,16 @@ whal_Error whal_Stm32wbUart_Send(whal_Uart *uartDev, const void *data, size_t da
 
 whal_Error whal_Stm32wbUart_Recv(whal_Uart *uartDev, void *data, size_t dataSz)
 {
-    const whal_Regmap *reg = &uartDev->regmap;
-    whal_Stm32wbUart_Cfg *cfg = (whal_Stm32wbUart_Cfg *)uartDev->cfg;
+    const whal_Regmap *reg;
+    whal_Stm32wbUart_Cfg *cfg;
     uint8_t *buf = data;
+
+    if (!uartDev || !uartDev->cfg || !data) {
+        return WHAL_EINVAL;
+    }
+
+    reg = &uartDev->regmap;
+    cfg = (whal_Stm32wbUart_Cfg *)uartDev->cfg;
     size_t d;
 
     for (size_t i = 0; i < dataSz; ++i) {
@@ -181,9 +152,3 @@ const whal_UartDriver whal_Stm32wbUart_Driver = {
     .Recv = whal_Stm32wbUart_Recv,
 };
 
-const whal_UartDriver whal_Stm32wbLpuart_Driver = {
-    .Init = whal_Stm32wbLpuart_Init,
-    .Deinit = whal_Stm32wbUart_Deinit,
-    .Send = whal_Stm32wbUart_Send,
-    .Recv = whal_Stm32wbUart_Recv,
-};
diff --git a/wolfHAL/clock/pic32cz_clock.h b/wolfHAL/clock/pic32cz_clock.h
index 2c0efbd..780f99e 100644
--- a/wolfHAL/clock/pic32cz_clock.h
+++ b/wolfHAL/clock/pic32cz_clock.h
@@ -4,7 +4,6 @@
 #include <stdint.h>
 #include <wolfHAL/bitops.h>
 #include <wolfHAL/clock/clock.h>
-#include <wolfHAL/supply/supply.h>
 
 /*
  * @file pic32cz_clock.h
@@ -138,9 +137,6 @@ typedef struct whal_Pic32czClockPll_OutCfg {
  *   f_out = 900MHz / 3 = 300MHz
  */
 typedef struct whal_Pic32czClockPll_OscCtrlCfg {
-    whal_Supply *supplyCtrl; /* Supply controller for PLL power */
-    void *supply;            /* Supply instance handle */
-
     whal_Pic32czClockPll_Inst pllInst;   /* PLL0 or PLL1 */
     whal_Pic32czClockPll_RefSel refSel;  /* Reference clock source */
     whal_Pic32czClockPll_BwSel bwSel;    /* Loop filter bandwidth */
diff --git a/wolfHAL/clock/stm32wb_rcc.h b/wolfHAL/clock/stm32wb_rcc.h
index 8badbec..378850b 100644
--- a/wolfHAL/clock/stm32wb_rcc.h
+++ b/wolfHAL/clock/stm32wb_rcc.h
@@ -3,7 +3,6 @@
 
 #include <stdint.h>
 #include <wolfHAL/clock/clock.h>
-#include <wolfHAL/flash/stm32wb_flash.h>
 #include <stddef.h>
 
 /*
@@ -121,12 +120,8 @@ typedef struct whal_Stm32wbRcc_Clk {
  * @brief RCC driver configuration.
  *
  * Contains all parameters needed to configure the system clock.
- * Flash latency must be set appropriately for the target frequency.
  */
 typedef struct whal_Stm32wbRcc_Cfg {
-    whal_Flash *flash;                       /* Flash device for latency config */
-    whal_Stm32wbFlash_Latency flashLatency;  /* Required flash wait states */
-
     whal_Stm32wbRcc_SysClockSrc sysClkSrc;   /* System clock source */
     void *sysClkCfg; /* Pointer to PllClkCfg or MsiClkCfg based on driver */
 } whal_Stm32wbRcc_Cfg;
diff --git a/wolfHAL/crypto/stm32wb_aes.h b/wolfHAL/crypto/stm32wb_aes.h
index 37da851..faeab83 100644
--- a/wolfHAL/crypto/stm32wb_aes.h
+++ b/wolfHAL/crypto/stm32wb_aes.h
@@ -3,7 +3,6 @@
 
 #include <stdint.h>
 #include <wolfHAL/crypto/crypto.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/timeout.h>
 
 /*
@@ -19,8 +18,6 @@
  * @brief AES device configuration.
  */
 typedef struct {
-    whal_Clock *clkCtrl;
-    const void *clk;
     whal_Timeout *timeout;
 } whal_Stm32wbAes_Cfg;
 
diff --git a/wolfHAL/flash/pic32cz_flash.h b/wolfHAL/flash/pic32cz_flash.h
index 00679c3..3f27d07 100644
--- a/wolfHAL/flash/pic32cz_flash.h
+++ b/wolfHAL/flash/pic32cz_flash.h
@@ -2,7 +2,6 @@
 #define WHAL_PIC32CZ_FLASH_H
 
 #include <wolfHAL/flash/flash.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/timeout.h>
 
 /*
diff --git a/wolfHAL/flash/stm32wb_flash.h b/wolfHAL/flash/stm32wb_flash.h
index e5e2d0b..9a29f09 100644
--- a/wolfHAL/flash/stm32wb_flash.h
+++ b/wolfHAL/flash/stm32wb_flash.h
@@ -2,7 +2,6 @@
 #define WHAL_STM32WB_FLASH_H
 
 #include <wolfHAL/flash/flash.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/timeout.h>
 
 /*
@@ -25,8 +24,6 @@
  * @brief Flash device configuration.
  */
 typedef struct whal_Stm32wbFlash_Cfg {
-    whal_Clock *clkCtrl;  /* Clock controller for flash interface clock */
-    const void *clk;      /* Clock descriptor */
     size_t startAddr;     /* Flash base address (typically 0x08000000) */
     size_t size;          /* Flash size in bytes */
     whal_Timeout *timeout;
diff --git a/wolfHAL/gpio/stm32wb_gpio.h b/wolfHAL/gpio/stm32wb_gpio.h
index 2ceb2da..4e12d3c 100644
--- a/wolfHAL/gpio/stm32wb_gpio.h
+++ b/wolfHAL/gpio/stm32wb_gpio.h
@@ -3,8 +3,6 @@
 
 #include <stdint.h>
 #include <wolfHAL/gpio/gpio.h>
-#include <wolfHAL/clock/clock.h>
-#include <wolfHAL/clock/stm32wb_rcc.h>
 #include <wolfHAL/regmap.h>
 
 /*
@@ -103,10 +101,6 @@ typedef struct {
  * Contains clock control references and an array of pin configurations.
  */
 typedef struct {
-    whal_Clock *clkCtrl; /* Clock controller for enabling GPIO clock */
-    const void **clk;    /* Array of clock descriptors */
-    size_t clkCount;     /* Number of clock descriptors */
-
     whal_Stm32wbGpio_PinCfg *pinCfg; /* Array of pin configurations */
     size_t pinCount;                  /* Number of pins to configure */
 } whal_Stm32wbGpio_Cfg;
diff --git a/wolfHAL/platform/st/stm32wb55xx.h b/wolfHAL/platform/st/stm32wb55xx.h
index ca05c17..1692e1b 100644
--- a/wolfHAL/platform/st/stm32wb55xx.h
+++ b/wolfHAL/platform/st/stm32wb55xx.h
@@ -21,7 +21,7 @@
         .base = 0x40008000,             \
         .size = 0x400,                  \
     },                                  \
-    .driver = &whal_Stm32wbLpuart_Driver
+    .driver = &whal_Stm32wbUart_Driver
 
 #define WHAL_STM32WB55_SPI1_DEVICE      \
     .regmap = {                         \
diff --git a/wolfHAL/rng/stm32wb_rng.h b/wolfHAL/rng/stm32wb_rng.h
index 305e5f4..6dc2763 100644
--- a/wolfHAL/rng/stm32wb_rng.h
+++ b/wolfHAL/rng/stm32wb_rng.h
@@ -3,7 +3,6 @@
 
 #include <stdint.h>
 #include <wolfHAL/rng/rng.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/timeout.h>
 
 /*
@@ -19,8 +18,6 @@
  * @brief RNG device configuration.
  */
 typedef struct whal_Stm32wbRng_Cfg {
-    whal_Clock *clkCtrl; /* Clock controller for RNG peripheral clock */
-    const void *clk;     /* Clock descriptor */
     whal_Timeout *timeout;
 } whal_Stm32wbRng_Cfg;
 
diff --git a/wolfHAL/spi/stm32wb_spi.h b/wolfHAL/spi/stm32wb_spi.h
index 4415409..026ea75 100644
--- a/wolfHAL/spi/stm32wb_spi.h
+++ b/wolfHAL/spi/stm32wb_spi.h
@@ -4,7 +4,6 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <wolfHAL/spi/spi.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/timeout.h>
 
 /*
@@ -34,8 +33,7 @@ typedef enum {
  * @brief SPI device configuration.
  */
 typedef struct whal_Stm32wbSpi_Cfg {
-    whal_Clock *clkCtrl;  /* Clock controller for SPI peripheral clock */
-    const void *clk;      /* Clock descriptor */
+    uint32_t pclk;        /* Peripheral clock frequency in Hz */
     whal_Timeout *timeout;
 } whal_Stm32wbSpi_Cfg;
 
diff --git a/wolfHAL/uart/pic32cz_uart.h b/wolfHAL/uart/pic32cz_uart.h
index ba25441..d13071d 100644
--- a/wolfHAL/uart/pic32cz_uart.h
+++ b/wolfHAL/uart/pic32cz_uart.h
@@ -3,7 +3,6 @@
 
 #include <stdint.h>
 #include <stddef.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/uart/uart.h>
 #include <wolfHAL/timeout.h>
 
@@ -38,8 +37,6 @@ typedef enum {
  * @brief PIC32CZ SERCOM USART configuration parameters.
  */
 typedef struct whal_Pic32czUart_Cfg {
-    whal_Clock *clkCtrl;
-    void *clk;
     uint32_t baud;
     whal_Pic32czUart_TxPad txPad;
     whal_Pic32czUart_RxPad rxPad;
diff --git a/wolfHAL/uart/stm32wb_uart.h b/wolfHAL/uart/stm32wb_uart.h
index 99b94b2..5157b7b 100644
--- a/wolfHAL/uart/stm32wb_uart.h
+++ b/wolfHAL/uart/stm32wb_uart.h
@@ -2,7 +2,6 @@
 #define WHAL_STM32WB_UART_H
 
 #include <stdint.h>
-#include <wolfHAL/clock/clock.h>
 #include <wolfHAL/uart/uart.h>
 #include <wolfHAL/timeout.h>
 #include <stddef.h>
@@ -12,13 +11,21 @@
  * @brief STM32 UART driver configuration.
  */
 
+/*
+ * @brief Compute UART BRR register value.
+ */
+#define WHAL_STM32WB_UART_BRR(clk, baud)   ((clk) / (baud))
+
+/*
+ * @brief Compute LPUART BRR register value.
+ */
+#define WHAL_STM32WB_LPUART_BRR(clk, baud) ((uint32_t)(((uint64_t)(clk) * 256) / (baud)))
+
 /*
  * @brief STM32 UART configuration parameters.
  */
 typedef struct whal_Stm32wbUart_Cfg {
-    whal_Clock *clkCtrl;
-    void *clk;
-    uint32_t baud;
+    uint32_t brr;
     whal_Timeout *timeout;
 } whal_Stm32wbUart_Cfg;
 
@@ -26,7 +33,6 @@ typedef struct whal_Stm32wbUart_Cfg {
  * @brief Driver instance for STM32 UART peripheral.
  */
 extern const whal_UartDriver whal_Stm32wbUart_Driver;
-extern const whal_UartDriver whal_Stm32wbLpuart_Driver;
 
 /*
  * @brief Initialize the STM32 UART peripheral.
@@ -37,15 +43,6 @@ extern const whal_UartDriver whal_Stm32wbLpuart_Driver;
  * @retval WHAL_EINVAL  Invalid arguments.
  */
 whal_Error whal_Stm32wbUart_Init(whal_Uart *uartDev);
-/*
- * @brief Initialize the STM32 UART peripheral.
- *
- * @param uartDev UART device instance to initialize.
- *
- * @retval WHAL_SUCCESS Initialization completed.
- * @retval WHAL_EINVAL  Invalid arguments.
- */
-whal_Error whal_Stm32wbLpuart_Init(whal_Uart *uartDev);
 /*
  * @brief Deinitialize the STM32 UART peripheral.
  *