diff --git a/.codespellrc b/.codespellrc index 80931e7dec7..29c576f1673 100644 --- a/.codespellrc +++ b/.codespellrc @@ -5,6 +5,8 @@ skip = ./build, *.pdf, *.svg, *.log, + *.vqm, + *.blif, # External projects that do not belong to us. ./libs/EXTERNAL, ./parmys, @@ -16,7 +18,6 @@ skip = ./build, ./verilog_preprocessor, # WIP spelling cleanups. ./vtr_flow, - ./utils/vqm2blif, # Temporary as we wait for some PRs to merge. *_graph_uxsdcxx_capnp.h, ./vpr/src/route/rr_graph_generation/rr_graph.cpp, @@ -37,10 +38,12 @@ ignore-words-list = subtile, FPT, Synopsys, inout, + inouts, INOUT, Dout, dout, DATIN, + ACCout, ShowIn, # Special case: pres fac / pres cost for example. Pres, diff --git a/utils/vqm2blif/README.txt b/utils/vqm2blif/README.txt index 8afc01e4086..994143c7d61 100644 --- a/utils/vqm2blif/README.txt +++ b/utils/vqm2blif/README.txt @@ -1,5 +1,5 @@ ------------------------------------- - VQM to BLIF Convertor + VQM to BLIF Converter ------------------------------------- Created By: S. Whitty @@ -238,7 +238,7 @@ Architecture file containing the constinuent primitives of the circuit [e.g. ../ -multiclock_primitives By default the tool will attempt to identify netlist primitives with multiple clocks, and then - drop the extra clocks from the primtive. This is a work-around for VPR, since VPR currently + drop the extra clocks from the primitive. This is a work-around for VPR, since VPR currently does not support multiple clocks per primitive. If this option is provided, the tool will keep (i.e. not drop) extra clocks from netlist primitives. @@ -256,7 +256,7 @@ Architecture file containing the constinuent primitives of the circuit [e.g. ../ VII. VQM GENERATION ------------------------ NOTE: If using VQM2BLIF as part of Titan, see scripts/titan_flow.py and scripts/q2_flow.tcl as - they automate this process. This section is maintained for referrence. + they automate this process. This section is maintained for reference. This method uses a Linux Shell environment to generate a VQM file using Quartus II. Other methods, such as using a Windows environment or the Quartus II GUI, are not covered here. @@ -319,7 +319,7 @@ IX. LUT RECOGNITION BLIF netlist has low-level WYSIWYG blackboxes that do not have any configurability; their functionality is predetermined and static and only their connectivity can be varied. A VQM primitive, on the other hand, has associated parameter information that defines lower-level functionality than that which is explicitly -described. Thus, this convertor must bridge the gap between these two levels. For most blocks, (e.g. RAMs, +described. Thus, this converter must bridge the gap between these two levels. For most blocks, (e.g. RAMs, DSPs, etc.) this involves approximating the configuration by appending a code to the name of the block to essentially split the single initial type of block into multiple similar but differently-functioning ones. diff --git a/utils/vqm2blif/src/base/cleanup.cpp b/utils/vqm2blif/src/base/cleanup.cpp index 2efbe9af5dd..7a7550d9d96 100644 --- a/utils/vqm2blif/src/base/cleanup.cpp +++ b/utils/vqm2blif/src/base/cleanup.cpp @@ -280,7 +280,7 @@ void remove_one_lut_nodes ( busvec* buses, std::unordered_map - Srivatsan Srinivasan, September 2021: - removed the function parameters "original_num_nodes" and "nodes". These values can be from the "module" parameter and are now assigned internally within this function. - Srivatsan Srinivasan, August 2021: - - Moved the incrementing of the "oneluts_elim" variable to this fuction from the "remove_node" function. The purpose of this change was to localise any vairable attached to removing one lut nodes within this function. Additionally, now the "remove_node" function is generalized and is not limited to be only used by "remove_one_lut_nodes". + - Moved the incrementing of the "oneluts_elim" variable to this function from the "remove_node" function. The purpose of this change was to localise any variable attached to removing one lut nodes within this function. Additionally, now the "remove_node" function is generalized and is not limited to be only used by "remove_one_lut_nodes". */ oneluts_elim = 0; @@ -639,7 +639,7 @@ void verify_netlist ( t_node** nodes, int num_nodes, busvec* buses, std::unorder cout << "\t>> Verifying netlist...\n" ; - //Step 0: Construct child_count "matrix" corresponding to the net indeces. + //Step 0: Construct child_count "matrix" corresponding to the net indices. // The children of each net will be counted as the netlist is verified, // then compared against the number of children stored in the net. vector < vector > child_count; @@ -663,7 +663,7 @@ void verify_netlist ( t_node** nodes, int num_nodes, busvec* buses, std::unorder for (int j = 0; (unsigned int)j < temp_bus->size(); j++){ temp_net = &(temp_bus->at(j)); - VTR_ASSERT((temp_net->bus_index == i)&&(temp_net->wire_index == j)); //indeces must line up + VTR_ASSERT((temp_net->bus_index == i)&&(temp_net->wire_index == j)); //indices must line up VTR_ASSERT(ref_pin == temp_net->pin); //all nets in a common bus share a pin if (temp_net->driver == CONST){ @@ -726,7 +726,7 @@ void verify_netlist ( t_node** nodes, int num_nodes, busvec* buses, std::unorder VTR_ASSERT(temp_bus->size() > 0); for (int j = 0; (unsigned int)j < temp_bus->size(); j++){ temp_net = &(temp_bus->at(j)); - VTR_ASSERT((temp_net->bus_index == i)&&(temp_net->wire_index == j)); //indeces must line up + VTR_ASSERT((temp_net->bus_index == i)&&(temp_net->wire_index == j)); //indices must line up VTR_ASSERT(child_count[i][j] == temp_net->num_children); } } @@ -855,7 +855,7 @@ void reorganize_module_node_list(t_module* module) Please refer to the example below: - Inital Node array: + Initial Node array: ------ ------ ------ ------ |LUT 1| --> |LUT 2| --> --> |LUT 3| --> |LUT 4| ------ ------ ------ ------ @@ -871,7 +871,7 @@ void reorganize_module_node_list(t_module* module) Change Log: - Srivatsan Srinivasan, August 2021: - created this function to reorganize node arrays with gaps inside of them. - - Initially the feature provided by this function was embedded indide the "remove_one_lut_nodes" function. By creating a seperate function, we are now not restricted to only removing one-lut nodes. + - Initially the feature provided by this function was embedded inside the "remove_one_lut_nodes" function. By creating a separate function, we are now not restricted to only removing one-lut nodes. - Now we can remove any types of nodes and then run this function to reorganize the node array. */ // assign module related parameters diff --git a/utils/vqm2blif/src/base/cleanup.h b/utils/vqm2blif/src/base/cleanup.h index 7d8a8095ecf..b1cbf50d37e 100644 --- a/utils/vqm2blif/src/base/cleanup.h +++ b/utils/vqm2blif/src/base/cleanup.h @@ -44,7 +44,7 @@ void remove_node ( t_node* node, t_node** nodes, int original_num_nodes ); * this function fills in those gaps so that the array is continuous. * * Parameters: -* module - the module that contains a node list with elemets within it deleted +* module - the module that contains a node list with elements within it deleted * */ void reorganize_module_node_list(t_module* module); diff --git a/utils/vqm2blif/src/base/hard_block_recog.cpp b/utils/vqm2blif/src/base/hard_block_recog.cpp index f16f8ebfa3d..02f1a0c2558 100644 --- a/utils/vqm2blif/src/base/hard_block_recog.cpp +++ b/utils/vqm2blif/src/base/hard_block_recog.cpp @@ -197,7 +197,7 @@ bool sort_hard_blocks_by_valid_connections(t_hard_block, t_hard_block); /** * @details This function is the main controller and executes all the - * processing steps involved in indentifying new types of hard + * processing steps involved in identifying new types of hard * blocks within the design and adding them to the netlist. * * The following steps are performed: @@ -262,7 +262,7 @@ void add_hard_blocks_to_netlist(t_module* main_module, t_arch* main_arch, std::v /* We catch any errors that occur during the procedure of reading the - netlist and inserting custom hard blocks whereever necessary. + netlist and inserting custom hard blocks wherever necessary. All the errors in this step are related to the provided .vqm netlist file, so once we catch the error, we append the netlist file location and throw another error to force program termination. */ @@ -311,7 +311,7 @@ void add_hard_blocks_to_netlist(t_module* main_module, t_arch* main_arch, std::v * within the list. The ports and their indexing is stored. * * @param main_arch This contains all the information regarding the FPGA - * architeture that the design will be mapped to. + * architecture that the design will be mapped to. * * @param hard_block_type_names A list of the hard block names that need * to be properly added to the netlist. @@ -553,7 +553,7 @@ static void create_hard_block_port_info_structure(t_hard_block_recog* storage_of * The port information for all new types of hard blocks * can be found within the FPGA architecture. For each hard block, * the ports info can be found in a structure called 't_model_ports' - * (found in 'logic_types.h'). The ports are arranged in a linked lsit + * (found in 'logic_types.h'). The ports are arranged in a linked list * structure. * * THis function goes through the 't_model_ports' and stores them @@ -569,7 +569,7 @@ static void create_hard_block_port_info_structure(t_hard_block_recog* storage_of * store ports in the form of a 't_node_port_association' array. * Additionally, for ports that are bussed, initially, they were * represented as a single 't_model_port' structure with the size - * of the port included, whereas they need to be seperated into + * of the port included, whereas they need to be separated into * individual ports (which is also done here). * * @param storage_of_hard_block_info This is a data structure of type @@ -648,11 +648,11 @@ static t_array_ref* convert_hard_block_model_port_to_hard_block_node_port(t_mode //create memory to store the port array port_array = create_and_initialize_t_array_ref_struct(); - // if a port is a bus, we need to create seperate port structures for each and every signal of the bus + // if a port is a bus, we need to create separate port structures for each and every signal of the bus for (int port_index = 0; port_index < port_size; port_index++) { // hard blocks will not have indexed wire assignments - // doesnt do anything different I think + // doesn't do anything different I think curr_hard_block_node_port = create_unconnected_node_port_association(curr_hard_block_model_port_name, port_index, PORT_WIRE_NOT_INDEXED); // store the newly created specific port index within the entire port @@ -842,7 +842,7 @@ static int find_hard_block_instance(t_hard_block_recog* module_hard_block_node_r /* if we previously found a module node that represented a different port of the same hard block instance, we would have already created the node to represent the hard block instance. Search the current list of already created hard block instances for the hard block instance the current node is a part (remember that the current node represents a port for a hard block). - We are using hard block names to idetify each instance.*/ + We are using hard block names to identify each instance.*/ curr_hard_block_instance_index_ref = module_hard_block_node_refs_and_info->hard_block_instance_name_to_index.find(curr_hard_block_instance_name); // now check the search result to see whether the hard block instance the current node is a part of was already created (if it exists in our internal list) @@ -856,7 +856,7 @@ static int find_hard_block_instance(t_hard_block_recog* module_hard_block_node_r else { // if we are here then the the hard block instance the current node is a port of already exists. - //so we store its index to identify it from all the other hard block instaces found in the netlist (all hard block instances are stored in a vector within 't_hard_block_recog') + //so we store its index to identify it from all the other hard block instances found in the netlist (all hard block instances are stored in a vector within 't_hard_block_recog') hard_block_instance_index = curr_hard_block_instance_index_ref->second; } @@ -982,7 +982,7 @@ static void assign_net_to_hard_block_instance_port(t_node* curr_module_node, t_p port_to_assign_index = identify_port_index_within_hard_block_type_port_array(&(curr_hard_block_type_port_info->second), curr_module_node_info, curr_module_node); - // assign the net to the crresponding hard block instance port // + // assign the net to the corresponding hard block instance port // handle_net_assignment(curr_module_node, curr_hard_block_instance, port_to_assign_index, curr_module_node_port_connected_to_hard_block_instance_net, curr_module_node_info); return; @@ -1148,7 +1148,7 @@ static int identify_port_index_within_hard_block_type_port_array(t_hard_block_po index: 0 1 2 3 port_array: port_1[0] port_1[1] port_1[2] port_1[2] - Now if we want the index of port_1[1], the base port index would be 0, then we need to increment by 1. This is why the increment is requried. + Now if we want the index of port_1[1], the base port index would be 0, then we need to increment by 1. This is why the increment is required. If the port is not vectored, the increment value would be 0. So the case is handled */ @@ -1158,13 +1158,13 @@ static int identify_port_index_within_hard_block_type_port_array(t_hard_block_po // now we check whether the port index is within the port range // // if the port size of the current port (using internal mapping structure found in the hard block port info struct) - // this should result in a valid value as we already verfied whether the port exists + // this should result in a valid value as we already verified whether the port exists found_port_size = curr_hard_block_type_port_info->port_name_to_port_size.find(curr_module_node_info->hard_block_port_name); // calculate port end index port_end_index = found_port_start_index->second + (found_port_size->second - 1); - // verify if the current port index is out of ranged by chekcing if it is larger than the maximum index for the port + // verify if the current port index is out of ranged by checking if it is larger than the maximum index for the port if (identified_port_index > port_end_index) { // port index is out of range, so throw an error and indicate it to the user @@ -1217,7 +1217,7 @@ static void handle_net_assignment(t_node* curr_module_node, t_hard_block* curr_h t_node_port_association* port_to_assign = curr_hard_block_instance->hard_block_instance_node_reference->array_of_ports[port_to_assign_index]; - // need to check whether the current port was previouly assigned to a net + // need to check whether the current port was previously assigned to a net if ((port_to_assign->associated_net) == NULL) { // port was not assigned to a net previously // @@ -1232,7 +1232,7 @@ static void handle_net_assignment(t_node* curr_module_node, t_hard_block* curr_h } else { - // the port was already assigned previouly, this is an error, since we cannot have multiple nets connected to the same port + // the port was already assigned previously, this is an error, since we cannot have multiple nets connected to the same port // so report an error throw vtr::VtrError("The vqm netlist node '" + curr_module_node_name + "' represents a port: '" + curr_module_node_info->hard_block_port_name +"' within hard block model: '" + curr_module_node_info->hard_block_type + "'. But this port was already represented previously, therefore the current netlist node is a duplication of the port. A port can only have one netlist node representing it."); } @@ -1459,14 +1459,14 @@ static int store_new_hard_block_instance_info(t_hard_block_recog* module_hard_bl // since we added the new hard block instance (t_hard_block struct) at the end of vector, the index will be the last position with the list new_hard_block_instance_index = module_hard_block_node_refs_and_info->hard_block_instances.size() - 1; - /* now create a mapping between the new hard block instance name and the index it is located in with the list of all hard block instances, so we can find it quicly using just the hard block instance name*/ + /* now create a mapping between the new hard block instance name and the index it is located in with the list of all hard block instances, so we can find it quickly using just the hard block instance name*/ module_hard_block_node_refs_and_info->hard_block_instance_name_to_index.insert(std::pair(curr_module_node_info->hard_block_name,new_hard_block_instance_index)); return new_hard_block_instance_index; } /** - * @details Given an arbritary array of pointers, this function + * @details Given an arbitrary array of pointers, this function * stores the array and its properties into a * 't_array_ref' structure. * @@ -1519,7 +1519,7 @@ static t_parsed_hard_block_port_info extract_hard_block_port_info_from_module_no { std::string curr_module_node_name = curr_module_node->name; - // container to hold all the names of the different hierachy levels found for the current node in the netlist(refer to 'split_node_name function' for more info) + // container to hold all the names of the different hierarchy levels found for the current node in the netlist(refer to 'split_node_name function' for more info) std::vector components_of_module_node_name; int index_of_node_name_component_with_hard_block_type_info = 0; @@ -1530,8 +1530,8 @@ static t_parsed_hard_block_port_info extract_hard_block_port_info_from_module_no split_node_name(curr_module_node_name, &components_of_module_node_name, VQM_NODE_NAME_DELIMITER); - // if the node name does not have atleast two hierarhcy levels, then it cannot be a hard block port so we cannot extract any more information. - // a hard block port in the vqm netlist must have atleast the port information and the next top level block name it is connected to. As shown below: + // if the node name does not have at least two hierarchy levels, then it cannot be a hard block port so we cannot extract any more information. + // a hard block port in the vqm netlist must have at least the port information and the next top level block name it is connected to. As shown below: // For example, \router:test_noc_router|payload[8]~QIC_DANGLING_PORT_I is a hard block payload port connected to a router block. // \Add0~9_I is not a hard block port if ((components_of_module_node_name.size()) >= 2) @@ -1579,10 +1579,10 @@ static t_parsed_hard_block_port_info extract_hard_block_port_info_from_module_no * * @param original_node_name The name of a node within the module (netlist). * - * @param node_name_components A list of strings that are seperated components + * @param node_name_components A list of strings that are separated components * of the original_node_name string. * - * @param delimiter A character that will be used to seperate the + * @param delimiter A character that will be used to separate the * original_node_name string above into multiple * pieces. * @@ -1605,7 +1605,7 @@ static void split_node_name(std::string original_node_name, std::vectorpush_back(original_node_name.substr(start_of_current_node_name_component, end_of_current_node_name_component - start_of_current_node_name_component)); return; @@ -1646,7 +1646,7 @@ static std::string identify_hard_block_type(std::vector* hard_block /* If a node belongs to a hard block, then the hard block name is generally followed by a colon operator, which is why need to append it. for a 'router' block we can expect something like this: - \router:test_noc_router|sc_flit[8]~reg0_I, where router is follwed by : + \router:test_noc_router|sc_flit[8]~reg0_I, where router is followed by : This also helps ignore invalid cases where a block instantiation has a hard block name within it, even though the block is not of that hard @@ -1673,11 +1673,11 @@ static std::string identify_hard_block_type(std::vector* hard_block /** * @details Given a list of strings, this function combines the strings - * together using a delimitter and generates a combined string. + * together using a delimiter and generates a combined string. * * @param node_name_components A list of strings that will be combined * together to generate a single string output. - * @param delimiter A character that will be used to seperate the list elements + * @param delimiter A character that will be used to separate the list elements * above in the generated string output. * */ @@ -1735,7 +1735,7 @@ static std::string construct_hard_block_name(std::vector*node_name_ */ static void identify_hard_block_port_name_and_index (t_parsed_hard_block_port_info* curr_hard_block_port, std::string curr_node_name_component) { - // identifer to check whether the port defined in the current node name is a bus (ex. payload[1]~QIC_DANGLING_PORT_I) + // identifier to check whether the port defined in the current node name is a bus (ex. payload[1]~QIC_DANGLING_PORT_I) std::regex port_is_a_bus ("(.*)[[]([0-9]*)\\]~(?:.*)"); // identifier to check whether the current port defined in the current node name isn't a bus (ex. value~9490_I) diff --git a/utils/vqm2blif/src/base/hard_block_recog.h b/utils/vqm2blif/src/base/hard_block_recog.h index c24d7bd76cd..190cf1a0292 100644 --- a/utils/vqm2blif/src/base/hard_block_recog.h +++ b/utils/vqm2blif/src/base/hard_block_recog.h @@ -56,12 +56,12 @@ #define HARD_BLOCK_WITH_NO_PORTS 0 #define DEFAULT_PORT_INDEX 0 -// unique identifier that seperates a hard block type name (module name), from the specific instance name +// unique identifier that separates a hard block type name (module name), from the specific instance name #define HARD_BLOCK_TYPE_NAME_SEPERATOR ":" // a node name in reference to a hard block port (dffeas and stratic_lcell blocks) in the vqm netlist file consists of multiple hierarchy levels. // for example we can have the following name: \router_interconnect:test_router_interconnect|router:noc_router|id[2]~QIC_DANGLING_PORT_I (this has 3 hierarchy levels) -// each level of hierarchy (module within module) is seperated by the delimiter character defined below. The last level of hierarchy is the output net of the block +// each level of hierarchy (module within module) is separated by the delimiter character defined below. The last level of hierarchy is the output net of the block #define VQM_NODE_NAME_DELIMITER "|" // a port that is a bus is a vectored port. So a single port name with multiple indices. @@ -84,7 +84,7 @@ /* -* The port information (in an array) for an arbritary user defined +* The port information (in an array) for an arbitrary user defined * hard block in the design is stored in s_hard_block_port_info. Then a * mapping is provided which can * help identify the specific location within the port array @@ -135,10 +135,10 @@ typedef struct s_hard_block /* * Below is the main data structure used for hard block -* identification and creation. This data strcuture contains +* identification and creation. This data structure contains * the names and port info of every type of user defined hard blocks. It * also stores all hard blocks that were instantiated within -* the user design and an accompanying data strcuture to quickly identify +* the user design and an accompanying data structure to quickly identify * a specific hard block instance. All functions will primarily interact * with this data structure. */ @@ -188,7 +188,7 @@ typedef struct s_hard_block_recog * (for more info refer to 'hard_block_recog.cpp'). The generated names found * in the .vqm file for the two previous blocks contain a lot of information * about the hard block. The structure below is used to store the information, -* which includes the hard block name, hard block type, the specfic hard +* which includes the hard block name, hard block type, the specific hard * block port and if the port is a bus, then the specific index. */ typedef struct s_parsed_hard_block_port_info diff --git a/utils/vqm2blif/src/base/lut_recog.cpp b/utils/vqm2blif/src/base/lut_recog.cpp index 10d24ef3fc7..ff4aec695bc 100644 --- a/utils/vqm2blif/src/base/lut_recog.cpp +++ b/utils/vqm2blif/src/base/lut_recog.cpp @@ -4,7 +4,7 @@ * S. Whitty * October 27th, 2011 * -* This file determines the ability of the vqm2blif convertor to recognize and subsequently +* This file determines the ability of the vqm2blif converter to recognize and subsequently * elaborate a VQM Primitive that represents a LUT into a corresponding BLIF ".names" structure. * * BACKGROUND diff --git a/utils/vqm2blif/src/base/lut_recog.h b/utils/vqm2blif/src/base/lut_recog.h index 047a0985f94..96026c79b56 100644 --- a/utils/vqm2blif/src/base/lut_recog.h +++ b/utils/vqm2blif/src/base/lut_recog.h @@ -1,6 +1,6 @@ /********************************************************************************************* * lut_recog.h -* Header file allowing the vqm2blif convertor to recognize certain VQM primitives as LUTs +* Header file allowing the vqm2blif converter to recognize certain VQM primitives as LUTs * so it can elaborate them into the BLIF standard ".names" structure. * * For more, see lut_recog.cpp @@ -18,4 +18,4 @@ extern lut_support_map supported_luts; void setup_lut_support_map (); bool is_lut (t_node* vqm_node); -#endif \ No newline at end of file +#endif diff --git a/utils/vqm2blif/src/base/lut_stats.cpp b/utils/vqm2blif/src/base/lut_stats.cpp index 57c7d9f5f18..699df644890 100644 --- a/utils/vqm2blif/src/base/lut_stats.cpp +++ b/utils/vqm2blif/src/base/lut_stats.cpp @@ -157,7 +157,7 @@ map carry_chain_lengths(t_module* module, vector start map chain_lengths; //Build a net to node map for the cin port - // This is required to avoid slow reverse look-ups from cout net to assoicated cin nodes + // This is required to avoid slow reverse look-ups from cout net to associated cin nodes map net_to_node_map; for(int i = 0; i < module->number_of_nodes; i++) { t_node* temp_node = module->array_of_nodes[i]; diff --git a/utils/vqm2blif/src/base/lutmask.h b/utils/vqm2blif/src/base/lutmask.h index 871561d7943..c735047ec4b 100644 --- a/utils/vqm2blif/src/base/lutmask.h +++ b/utils/vqm2blif/src/base/lutmask.h @@ -18,8 +18,8 @@ class BlifLut { bitset <6> col_mask; - string inports[6]; - string outport; + string in_ports[6]; + string out_port; public: @@ -37,12 +37,12 @@ class BlifLut { void set_lutmask ( const char* ); //sets the lutmask and elaborates the truth table void set_col_mask ( const char* ); //sets the column mask to a specified const char* - void set_inport ( int, const char* ); //assigns an inport name and sets the column mask - void set_outport ( const char* ); //assigns the outport name + void set_in_port ( int, const char* ); //assigns an in-port name and sets the column mask + void set_out_port ( const char* ); //assigns the outport name void reset_ports(); //empties all port names and resets the column mask - string get_inport( int ); - string get_outport(); + string get_in_port( int ); + string get_out_port(); // *****PRINT FUNCTIONS***** // - Each print the LUT data in to a different source in a specified format. @@ -89,34 +89,34 @@ BlifLut::BlifLut ( const char* lmask, const char* a, const char* b, const char* * lmask: * LUTmask string to be evaluated into a truth table for the LUT. * a, b, c, d, e, f: - * Inport names. If a port is to be left unused, pass "". The column mask is updated accordingly. + * In-port names. If a port is to be left unused, pass "". The column mask is updated accordingly. */ set_lutmask ( lmask ); - //NOTE: At least two inports must be set before printing. + //NOTE: At least two in-ports must be set before printing. if (strlen(a) > 0){ - set_inport( 5, a ); + set_in_port( 5, a ); } if (strlen(b) > 0){ - set_inport( 4, b ); + set_in_port( 4, b ); } if (strlen(c) > 0){ - set_inport( 3, c ); + set_in_port( 3, c ); } if (strlen(d) > 0){ - set_inport( 2, d ); + set_in_port( 2, d ); } if (strlen(e) > 0){ - set_inport( 1, e ); + set_in_port( 1, e ); } if (strlen(f) > 0){ - set_inport( 0, f ); + set_in_port( 0, f ); } //NOTE: The outport is the only mandatory port. If left open, it must be set using set_outport(). if (strlen(out) > 0){ - set_outport( out ); + set_out_port( out ); } } @@ -131,7 +131,7 @@ void BlifLut::set_lutmask ( const char* lmask ){ * * ARGUMENTS: * lmask - * A 16-character string of hexidecimal numbers detailing the truth table of a LUT. + * A 16-character string of hexadecimal numbers detailing the truth table of a LUT. */ VTR_ASSERT(strlen(lmask) == 16); //Currently, only 6-input LUTs are supported. @@ -193,12 +193,12 @@ void BlifLut::set_col_mask ( const char* cmask ){ //============================================================================================ //============================================================================================ -void BlifLut::set_inport (int index, const char* name){ +void BlifLut::set_in_port (int index, const char* name){ //NOTE: Ports are printed as ".names [5] [4] [3] [2] [1] [0] out" VTR_ASSERT((index >= 0)&&(index <= 5)); VTR_ASSERT(strlen(name) > 0); - inports[index] = name; //assign the name of the port + in_ports[index] = name; //assign the name of the port col_mask.set(index); //indicate in the column mask that it's been used } @@ -206,11 +206,11 @@ void BlifLut::set_inport (int index, const char* name){ //============================================================================================ //============================================================================================ -void BlifLut::set_outport (const char* name){ +void BlifLut::set_out_port (const char* name){ //NOTE: Ports are printed as ".names [5] [4] [3] [2] [1] [0] out" VTR_ASSERT(strlen(name) > 0); - outport = name; + out_port = name; } @@ -219,27 +219,27 @@ void BlifLut::set_outport (const char* name){ void BlifLut::reset_ports(){ for (int i = 0; i < 6; i++ ){ - inports[i].clear(); //empty all the inport names + in_ports[i].clear(); //empty all the in-port names } - outport.clear(); //empty the outport name + out_port.clear(); //empty the outport name col_mask.reset(); //set the column mask to "000000" } //============================================================================================ //============================================================================================ -string BlifLut::get_inport (int index){ - if (inports[index].length() > 0) - return inports[index]; +string BlifLut::get_in_port (int index){ + if (in_ports[index].length() > 0) + return in_ports[index]; return ""; } //============================================================================================ //============================================================================================ -string BlifLut::get_outport (){ - if (outport.length() > 0) - return outport; +string BlifLut::get_out_port (){ + if (out_port.length() > 0) + return out_port; return ""; } @@ -275,8 +275,8 @@ void BlifLut::print (lp_mode print_mode, ostream& out_file, t_boolean eblif_form for (int i = 5; i >= 0; i--){ //only print used ports if (col_mask.test(i)){ - if (!inports[i].empty()){ - out_file << inports[i] << " "; + if (!in_ports[i].empty()){ + out_file << in_ports[i] << " "; } else { cout << "ERROR: LUT Input used and not named." << endl; exit(1); @@ -285,8 +285,8 @@ void BlifLut::print (lp_mode print_mode, ostream& out_file, t_boolean eblif_form } //Every LUT must have an output! - VTR_ASSERT(!outport.empty()); - out_file << outport << endl; + VTR_ASSERT(!out_port.empty()); + out_file << out_port << endl; //Print the truth table for(tt_vec::iterator it = truth_table.begin(); it != truth_table.end(); it++){ diff --git a/utils/vqm2blif/src/base/preprocess.cpp b/utils/vqm2blif/src/base/preprocess.cpp index 092d8a67180..f0061703b4f 100644 --- a/utils/vqm2blif/src/base/preprocess.cpp +++ b/utils/vqm2blif/src/base/preprocess.cpp @@ -56,7 +56,7 @@ bool is_arithmetic_port(t_node_port_association* node_port); void check_and_fix_clock_to_normal_port_connections(t_module* module, t_arch* arch, t_logical_block_type* arch_types, int num_types, string device); t_pin_def* find_associated_clock_net(t_node* node, t_pin_def* clock_net, t_global_nets clock_nets); -//Functions to identify dual-clock RAMs and split them into seperate blocks +//Functions to identify dual-clock RAMs and split them into separate blocks void decompose_multiclock_blocks(t_module* module, t_arch* arch, t_logical_block_type* arch_types, int num_types); void duplicate_and_split_multiclock_blocks(t_module* module, vector& multiclock_blocks); @@ -116,7 +116,7 @@ void preprocess_netlist(t_module* module, t_arch* arch, t_logical_block_type* ar */ //Clean up 'inout' pins by replacing them with - // seperate 'input' and 'output' pins + // separate 'input' and 'output' pins cout << "\t>> Preprocessing Netlist to decompose inout pins" << endl; decompose_inout_pins(module, arch, device); cout << endl; @@ -217,7 +217,7 @@ void decompose_inout_pins(t_module* module, t_arch* arch, string device){ * * After processing, 'inout_pin' has been split into two * different pins 'new_input_pin' and 'new_output_pin'. - * As thier names imply, 'new_input_pin' and 'new_output_pin' + * As their names imply, 'new_input_pin' and 'new_output_pin' * respectively handle the input and output duties of the * original inout pin * @@ -265,7 +265,7 @@ void decompose_inout_pins(t_module* module, t_arch* arch, string device){ * 2) Blackbox instantiations (nodes) */ - // 1) Check assignments (i.e. verilog assign statments) for driven + // 1) Check assignments (i.e. verilog assign statements) for driven // by and driving pins for(j = 0; j < module->number_of_assignments; j++) { @@ -306,7 +306,7 @@ void decompose_inout_pins(t_module* module, t_arch* arch, string device){ * * We must know this to ensure the port * is connected to the correct pin once - * the inout pin is split into seperate + * the inout pin is split into separate * input and output pins. * * This can be determined by querying the @@ -320,20 +320,20 @@ void decompose_inout_pins(t_module* module, t_arch* arch, string device){ LogicalModelId arch_model_id = find_model_in_architecture(arch->models, node, device); const t_model& arch_model = arch->models.get_model(arch_model_id); - //Find the architecure model port + //Find the architecture model port arch_model_port = find_port_in_architecture_model(arch_model, node_port); if (arch_model_port->dir == IN_PORT) { //It is an input, meaning a sink for node_port if (verbose_mode) { - cout << "\t sink: " << node->name << "." << node_port->port_name << " (" << node->type << " inport)\n"; + cout << "\t sink: " << node->name << "." << node_port->port_name << " (" << node->type << " in-port)\n"; } pin_node_sinks.push_back(node_port); } else if (arch_model_port->dir == OUT_PORT) { //It is an output, meaning a source for pin if (verbose_mode) { - cout << "\t source : " << node->name << "." << node_port->port_name << " (" << node->type << " outport)\n"; + cout << "\t source : " << node->name << "." << node_port->port_name << " (" << node->type << " out-port)\n"; } pin_node_sources.push_back(node_port); @@ -374,7 +374,7 @@ void decompose_inout_pins(t_module* module, t_arch* arch, string device){ LogicalModelId find_model_in_architecture(const LogicalModels& arch_models, t_node* node, string device) { /* - * Finds the archtecture module corresponding to the node type + * Finds the architecture module corresponding to the node type * * arch_models: the head of the linked list of architecture models * node : the VQM node to match @@ -382,7 +382,7 @@ LogicalModelId find_model_in_architecture(const LogicalModels& arch_models, t_no * Returns: A pointer to the corresponding model */ - //The VQM name may not match the architecture name if the architecture contians elaborated modes + //The VQM name may not match the architecture name if the architecture contains elaborated modes // So generate the elaborated mode name for this node string elaborated_name = generate_opname(node, arch_models, device); @@ -423,7 +423,7 @@ t_model_ports* find_port_in_architecture_model(const t_model& arch_model, t_node /* - * First chech the input linked list, if port name is not + * First check the input linked list, if port name is not * there, try the output linked list. It is an error * if port name is not in either list. */ @@ -479,7 +479,7 @@ t_split_inout_pin create_decomposed_pins(t_module* module, t_pin_def* inout_pin) * module->array_of_pins */ - //Only need one additional pin, since we re-use the already + //Only need one additional pin, since we reuse the already // allocated 'inout' pin module->number_of_pins++; @@ -564,7 +564,7 @@ int fix_netlist_connectivity_for_inout_pins(t_split_inout_pin* split_inout_pin, t_assign* assign_stmt = pin_assignment_sources->at(cnt); /* - * Sources of the original pin should now map to thier targets + * Sources of the original pin should now map to their targets * (outputs) to the new output pin * e.g. * assign target_inout = source; @@ -583,7 +583,7 @@ int fix_netlist_connectivity_for_inout_pins(t_split_inout_pin* split_inout_pin, t_assign* assign_stmt = pin_assignment_sinks->at(cnt); /* - * Sinks of the original pin should now map to thier sources + * Sinks of the original pin should now map to their sources * (inputs) to the new input pin * e.g. * assign target = source_inout; @@ -605,7 +605,7 @@ int fix_netlist_connectivity_for_inout_pins(t_split_inout_pin* split_inout_pin, t_node_port_association* node_port = pin_node_sources->at(cnt); /* - * Sources of the original pin should now map to thier outputs + * Sources of the original pin should now map to their outputs * to the new output pin * e.g. * inout pin1; @@ -634,7 +634,7 @@ int fix_netlist_connectivity_for_inout_pins(t_split_inout_pin* split_inout_pin, t_node_port_association* node_port = pin_node_sinks->at(cnt); /* - * Sinks of the original pin should now map to thier inputs + * Sinks of the original pin should now map to their inputs * to the new input pin * e.g. * inout pin1; @@ -675,7 +675,7 @@ void identify_mlab_acting_as_rom(t_module* module) { // //The solution implemented here is to identify ROM mode MLABs, and //manually add an 'operation_mode' parameter which will allow us to - //diferentiate these two cases later in VPR. Note that this operation_mode + //differentiate these two cases later in VPR. Note that this operation_mode //does not exist in the actual VQM, but is manually added by us here. int converted_mlab_count = 0; for(int i = 0; i < module->number_of_nodes; i++) { @@ -770,7 +770,7 @@ void remove_constant_nets(t_module *module) { cout << node_port->port_name << " to " << const_net->name << endl; } - //Delete the connection, by removing the port (unconnected ports are non-existant in VQM) + //Delete the connection, by removing the port (unconnected ports are non-existent in VQM) remove_node_port(node, j); //In-case the element copied over was also connected to a constant @@ -917,7 +917,7 @@ void decompose_carry_chains(t_module* module) { // are configured to route the LUT's logic output to the embedded // adder. To do this properly the LUTMASK will need to be updated! // TODO: We do not update the LUTMASK of the arith_lcell to pass through the datad - // and dataf inputs to the embeded adder. To do this properly the LUTMASK will + // and dataf inputs to the embedded adder. To do this properly the LUTMASK will // need to be updated! char buf[50]; //Buffer for net names @@ -1050,7 +1050,7 @@ void remove_extra_primitive_clocks(t_module *module) { //The port name is not 'clk0' and hence it is added //to the list to be removed // - //'clk' is what most blocks name thier clocks + //'clk' is what most blocks name their clocks //'clkhi' is the single clock we care about on DDIO primitives clock_ports_to_remove.push_back(node_port->port_name); } @@ -1060,7 +1060,7 @@ void remove_extra_primitive_clocks(t_module *module) { //Remove the extra clock ports if we have multiple if(clock_ports_to_remove.size() > 0) { - //We have mulitple clock ports + //We have multiple clock ports num_multiclock_nodes++; if(verbose_mode) @@ -1306,7 +1306,7 @@ void expand_ram_clocks(t_module* module, string device) { } - cout << "\t>> Elaborated " << num_clocks_added << " clocks accross " << num_ram_blocks_processed << " ram blocks" << endl; + cout << "\t>> Elaborated " << num_clocks_added << " clocks across " << num_ram_blocks_processed << " ram blocks" << endl; } @@ -1426,7 +1426,7 @@ void expand_dsp_clocks(t_module* module) { } - cout << "\t>> Elaborated " << num_clocks_added << " clocks accross " << num_ram_blocks_processed << " ram blocks" << endl; + cout << "\t>> Elaborated " << num_clocks_added << " clocks across " << num_ram_blocks_processed << " ram blocks" << endl; } @@ -1600,7 +1600,7 @@ void check_and_fix_clock_to_normal_port_connections(t_module* module, t_arch* ar } } } - cout << "\t>> Removed " << num_clock_pin_connections_removed << " connetions from false clock nets to clock pins" << endl; + cout << "\t>> Removed " << num_clock_pin_connections_removed << " connections from false clock nets to clock pins" << endl; //Re-determine clock nets and remove any remaining data/clock connections clock_nets = identify_global_nets(module, clock_ports); @@ -1770,8 +1770,8 @@ void duplicate_and_split_multiclock_blocks(t_module* module, vector& mu * Breaking things down the following work must be done: * 1) Duplicate orig_ram to create split_orig_ram_b * 2) Rename the block names and types - * 3) Disconnect port b related singals on split_orig_ram_a - * 4) Disconnect port a related singals on split_orig_ram_b + * 3) Disconnect port b related signals on split_orig_ram_a + * 4) Disconnect port a related signals on split_orig_ram_b * 5) Add dummy output to split_orig_ram_a * 6) Add dummy input to split_orig_ram_b */ @@ -2383,7 +2383,7 @@ t_global_nets identify_global_nets(t_module* module, t_global_ports global_ports * If it has global ports, check each port to see if it is in the set of * port strings the value in the global_ports map. * - * If the port is a global port, recored the net it is connected to, as this + * If the port is a global port, record the net it is connected to, as this * will be a global net. */ t_global_nets global_nets; @@ -2519,7 +2519,7 @@ t_net_driver_map identify_net_drivers(t_module* module, t_arch* arch, t_global_p LogicalModelId arch_model_id = find_model_in_architecture(arch->models, node, device); const t_model& arch_model = arch->models.get_model(arch_model_id); - //Find the architecure model port + //Find the architecture model port arch_model_port = find_port_in_architecture_model(arch_model, node_port); if (arch_model_port->dir == IN_PORT) { diff --git a/utils/vqm2blif/src/base/vqm2blif.h b/utils/vqm2blif/src/base/vqm2blif.h index c855dc7b200..5bb734d473e 100644 --- a/utils/vqm2blif/src/base/vqm2blif.h +++ b/utils/vqm2blif/src/base/vqm2blif.h @@ -3,7 +3,7 @@ * This file contains useful structures and functions used by vqm2blif.cpp to * parse a VQM netlist in order to output a corresponding BLIF netlist. * -* VQM to BLIF Convertor V.1.0 +* VQM to BLIF Converter V.1.0 * * Author: S. Whitty * May 20, 2011 @@ -102,7 +102,7 @@ typedef struct s_blif_subckt{ * If a port is left open, it will be mapped to the "hbpad" t_node_port_association. * NOTE: Must map the port's name (string) because a port may be a bus, with multiple * wires having the same portname. All assignments in BLIF must be 1-bit wide, so these - * buses must be flattened and mapped independantly. + * buses must be flattened and mapped independently. */ typedef struct s_blif_model{ diff --git a/utils/vqm2blif/src/base/vqm2blif_util.cpp b/utils/vqm2blif/src/base/vqm2blif_util.cpp index fc5c6864beb..0bb0aad0f51 100644 --- a/utils/vqm2blif/src/base/vqm2blif_util.cpp +++ b/utils/vqm2blif/src/base/vqm2blif_util.cpp @@ -59,11 +59,11 @@ void verify_hard_block_type_name(string curr_hard_block_type_name){ // naming rules have 2 main conditions: // Condition 1: the first charatcer must be a lowercase/uppercase alphabetical character. Or the first character can be a underscore. - // Condition 2: The remaning characters must be a lowercase/uppercase alphabetical character, or a underscore, or a single digit number or the '$' character + // Condition 2: The remaining characters must be a lowercase/uppercase alphabetical character, or a underscore, or a single digit number or the '$' character // the rules above are checked with the identifier below std::regex verilog_VHDL_naming_rules_one ("^[a-zA-Z_][a-zA-Z_\\$0-9]*[a-zA-Z_\\$0-9]$"); - // verilog names can also contain any characters, as long as they are escaped with a '\' at the start of the identifer. For example, \reset- + // verilog names can also contain any characters, as long as they are escaped with a '\' at the start of the identifier. For example, \reset- // we check this using the identifier below std::regex verilog_VHDL_naming_rules_two ("[\\](.*)", std::regex_constants::extended); // need std::regex_constants::extended as it supports '\\' character @@ -197,14 +197,14 @@ string append_index_to_str (string busname, int index){ //============================================================================================ string get_wire_name(t_pin_def* net, int index){ -/* Constructs a wire name based on its indeces and width. +/* Constructs a wire name based on its indices and width. * If index == -1, the entire net is used (multiple wires if the net is a bus). * net->indexed indicates whether the net is declared as a bus or just a wire. */ if (net->indexed == T_FALSE){ return (string)net->name; } else if (index == -1) { - //a wire must only be 1-bit wide!! Check right and left indeces. + //a wire must only be 1-bit wide!! Check right and left indices. VTR_ASSERT(net->left == net->right); return append_index_to_str((string)net->name, net->left); } else { @@ -384,7 +384,7 @@ void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, string& mode_hash) { //If ANY of the input ports are registered, we model all input ports as registered if(dataa_input_reg || datab_input_reg || signa_input_reg || signb_input_reg) { - //In the unsual case of only some inputs being registered, print a warning to the user + //In the unusual case of only some inputs being registered, print a warning to the user //if(verbose_mode) { //if(!dataa_input_reg || !datab_input_reg || !signa_input_reg || !signb_input_reg) { //cout << "Warning: DSP " << vqm_node->type << " '" << vqm_node->name << "' has only some inputs registered."; @@ -815,7 +815,7 @@ void generate_opname_stratix10_dsp (t_node* vqm_node, string& mode_hash, bool ds // // Provided that an input/outputs clock parameter value is 'none', then it is combinational (doesn't use the register) // - // The boolean variable dsp_mode indicates wether the dsp block is in fixed point mode (dsp_mode = 0) or floating point mode (dsp_mode = 1) + // The boolean variable dsp_mode indicates whether the dsp block is in fixed point mode (dsp_mode = 0) or floating point mode (dsp_mode = 1) if(dsp_mode == 0) VTR_ASSERT(strcmp(vqm_node->type, "fourteennm_mac") == 0); else @@ -1054,7 +1054,7 @@ RamInfo get_ram_info(const t_node* vqm_node, string device) { t_node_parameter* port_a_dataout_clear = NULL; t_node_parameter* port_b_dataout_clear = NULL; - //We need to save the ram data and address widths, to identfy the RAM type (singel port, rom, simple dual port, true dual port) + //We need to save the ram data and address widths, to identify the RAM type (single port, rom, simple dual port, true dual port) t_node_parameter* port_a_data_width = NULL; t_node_parameter* port_a_addr_width = NULL; t_node_parameter* port_a_addr2_width = NULL; @@ -1242,7 +1242,7 @@ RamInfo get_ram_info(const t_node* vqm_node, string device) { } if(clk0_port) { - //Not pre-processed, so remap the clocks ourselvs + //Not pre-processed, so remap the clocks ourselves VTR_ASSERT(!clk_portain); VTR_ASSERT(!clk_portaout); VTR_ASSERT(!clk_portbin); @@ -1518,7 +1518,7 @@ DSPInfo get_dsp_info(const t_node* vqm_node) { for (auto const& param : clock_param){ - // set the new register-based clock ports to one of the three clock signals based on the corrosponding parameters + // set the new register-based clock ports to one of the three clock signals based on the corresponding parameters if (param.second) { if (param.second->value.string_value == std::string("0")){ VTR_ASSERT(clk_port[0]); diff --git a/utils/vqm2blif/src/base/vqm2blif_util.h b/utils/vqm2blif/src/base/vqm2blif_util.h index 193ab7a46fe..169f996b46d 100644 --- a/utils/vqm2blif/src/base/vqm2blif_util.h +++ b/utils/vqm2blif/src/base/vqm2blif_util.h @@ -146,7 +146,7 @@ struct DSPInfo { }; // stores relevant information for a given FPGA device -// currently, just storing the strings used to idenitify luts and dff primitives and their ports within the vqm netlist +// currently, just storing the strings used to identify luts and dff primitives and their ports within the vqm netlist // add additional parameters as needed struct DeviceInfo { std::string lut_type_name; @@ -183,11 +183,11 @@ string generate_opname (t_node* vqm_node, const LogicalModels& arch_models, stri void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, string& mode_hash, string device); //mode-hash for RAM blocks string generate_opname_stratixiv (t_node* vqm_node, const LogicalModels& arch_models); //mode-hash for Stratix IV -void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, string& mode_hash); //mode-hash for Stratix IV DSP Multiplers +void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, string& mode_hash); //mode-hash for Stratix IV DSP Multipliers void generate_opname_stratixiv_dsp_out (t_node* vqm_node, string& mode_hash); //mode-hash for Stratix IV DSP Output (MAC) string generate_opname_stratix10 (t_node* vqm_node, const LogicalModels& arch_models); //mode-hash for Stratix 10 -void generate_opname_stratix10_dsp (t_node* vqm_node, string& mode_hash, bool dsp_mode); //mode-hash for Stratix 10 DSP fixed point Multiplers +void generate_opname_stratix10_dsp (t_node* vqm_node, string& mode_hash, bool dsp_mode); //mode-hash for Stratix 10 DSP fixed point Multipliers void generate_opname_stratix10_lut (t_node* vqm_node, string& mode_hash); //mode-hash for Stratix 10 LUTs void remap_lut_ports(t_node* vqm_node); // remaps the input ports of the LUT atom to the ports [dataa-datae] diff --git a/utils/vqm2blif/src/main.cpp b/utils/vqm2blif/src/main.cpp index a8c577ad9a0..18e3f106110 100644 --- a/utils/vqm2blif/src/main.cpp +++ b/utils/vqm2blif/src/main.cpp @@ -3,7 +3,7 @@ * The purpose of this program is to generate a valid .blif netlist by * parsing and interpreting a .vqm file. * -* VQM to BLIF Convertor V.1.2 +* VQM to BLIF Converter V.1.2 * * Author: S. Whitty * June 6, 2011 @@ -129,7 +129,7 @@ t_boolean elaborate_ram_clocks; //user-set flag which controls whether rams have t_boolean single_clock_primitives; //user-set flag which controls whether multiclock blocks have // their extra clocks dropped. This is a work around for - // VPR's limitaiton of one clock per primitive. + // VPR's limitation of one clock per primitive. t_boolean split_carry_chain_logic; //user-set flag which controls whether to decompose carry chain //logic cells into their constituent logic (LUT) and arithmetic @@ -274,7 +274,7 @@ int main(int argc, char* argv[]) // a list which stores all the user supplied custom hard block type names std::vector hard_block_type_name_list; - // indicates the type of device the circuit is targetting + // indicates the type of device the circuit is targeting // we set the default value to the stratix 4 device string device = "stratixiv"; @@ -282,7 +282,7 @@ int main(int argc, char* argv[]) // Begin Conversion //************************************************************************************************* - cout << "********************\nVQM to BLIF Convertor\nS. Whitty 2011\n********************\n" ; + cout << "********************\nVQM to BLIF Converter\nS. Whitty 2011\n********************\n" ; cout << "This parser reads a .vqm file and converts it to .blif format.\n\n" ; //verify command-line is correct, populate input variables and global mode flags. @@ -650,7 +650,7 @@ void cmd_line_parse (int argc, char** argv, string* sourcefile, string* archfile { // When we come here, we need to finish processing further command line arguments for hard block type names. Since we have a different command-line option. - // case one below is when the user didnt provide any hard block type names and just provided the next command-line option + // case one below is when the user didn't provide any hard block type names and just provided the next command-line option if (!insert_custom_hard_blocks) { // since no hard block type names were supplied, we throw an error @@ -816,7 +816,7 @@ void init_blif_models(t_blif_model* my_model, t_module* my_module, t_arch* arch, exit(1); break; default: - //PIN_WIREs don't need to be declared independantly for proper + //PIN_WIREs don't need to be declared independently for proper //BLIF format, they'll appear again in the array_of_assignments. ; } @@ -1200,7 +1200,7 @@ void find_and_map (portmap* map, t_model_ports* to_be_mapped, t_node* node, //map the port to its connectivity data map->insert(portpair(temp_name, node->array_of_ports[i])); - //indicate that the port has been successfuly mapped to + //indicate that the port has been successfully mapped to vqm_ports_found->at(i) = T_TRUE; break; } @@ -1275,14 +1275,14 @@ void push_lut (t_node* vqm_node, lutvec* blif_luts){ portName = get_wire_name(vqm_node->array_of_ports[i]->associated_net, vqm_node->array_of_ports[i]->wire_index); if (which_port < 6){ if (verbose_mode) { - cout << "\t\t Assigning inport " << i << " to " << portName << endl; + cout << "\t\t Assigning in-port " << i << " to " << portName << endl; } - temp_lut.set_inport ( which_port, portName.c_str() ); + temp_lut.set_in_port ( which_port, portName.c_str() ); } else { if (verbose_mode) { - cout << "\t\t Assigning outport to " << portName << endl; + cout << "\t\t Assigning out-port to " << portName << endl; } - temp_lut.set_outport( get_wire_name(vqm_node->array_of_ports[i]->associated_net, vqm_node->array_of_ports[i]->wire_index).c_str() ); + temp_lut.set_out_port( get_wire_name(vqm_node->array_of_ports[i]->associated_net, vqm_node->array_of_ports[i]->wire_index).c_str() ); } } } @@ -1407,7 +1407,7 @@ void dump_portlist (ofstream& outfile, pinvec ports, t_boolean /*debug*/){ * * NOTE: In VQM/Verilog syntax, buses are declared as * {input, output, clock, wire} [ left : right ] - * where left and right are indeces that describe the + * where left and right are indices that describe the * bus width. * * ARGUMENTS @@ -1508,7 +1508,7 @@ void dump_assignments(ofstream& outfile, t_blif_model* model, t_boolean eblif_fo (temp_assign->target->left > temp_assign->target->right)? -1:1, temp_assign->value, debug, temp_assign->inversion); - //dump_bus_assign() calls dump_wire_assign() repeatedly based on the indeces + //dump_bus_assign() calls dump_wire_assign() repeatedly based on the indices //of the target and whether the right or left index is larger. } else { #else @@ -1580,7 +1580,7 @@ void dump_bus_assign(ofstream& outfile, string target_name, int target_left, int * A bus assignment only occurs when the following is in the VQM: * " wire [X:Y] a; * wire [X:Y] b; - * assign a = b; " <-- NOTE: no indeces in the assign statement. + * assign a = b; " <-- NOTE: no indices in the assign statement. * * ARGUMENTS * outfile: @@ -1588,17 +1588,17 @@ void dump_bus_assign(ofstream& outfile, string target_name, int target_left, int * target_name: * Name of the wire being driven by the assign (on the left of the assign). * target_left, target_right: - * Left and right indeces of the target bus, as declared (Left = X, Right = Y) + * Left and right indices of the target bus, as declared (Left = X, Right = Y) * target_dir: - * Directionality of the indeces. +1 if Y > X, -1 if Y < X. + * Directionality of the indices. +1 if Y > X, -1 if Y < X. * is_constant: * Flag indicating whether the assignment is being driven by a constant generator. * source_name: * Name of the driver wire (on the right of the assign). * source_left, source_right: - * Left and right indeces of the driver bus, as declared (Left = X, Right = Y) + * Left and right indices of the driver bus, as declared (Left = X, Right = Y) * source_dir: - * Directionality of the indeces. +1 if Y > X, -1 if Y < X. + * Directionality of the indices. +1 if Y > X, -1 if Y < X. * value: * If the assign is constant, holds the value of the generator. * debug: @@ -1953,7 +1953,7 @@ void dump_subckt_models(const LogicalModels& models, ofstream& outfile, t_boolea //============================================================================================ void dump_subckt_portlist(ofstream& outfile, t_model_ports* port, std::string indent, t_boolean debug){ -/* Dumps the portlist of a subcircuit model at the end of a BLIF, flattening busses as necessary. +/* Dumps the portlist of a subcircuit model at the end of a BLIF, flattening buses as necessary. * * ARGUMENTS * outfile: @@ -1995,7 +1995,7 @@ void dump_subckt_portlist(ofstream& outfile, t_model_ports* port, std::string in //============================================================================================ void all_data_cleanup(){ -/* Frees all allocated memory from the parser and convertor. +/* Frees all allocated memory from the parser and converter. */ vqm_data_cleanup();//found in ../LIB/vqm_dll.h, frees parser-allocated memory @@ -2013,7 +2013,7 @@ void echo_module (char* echo_file, const char* vqm_filename, t_module* my_module * * PIN INFORMATION * All inputs, outputs, inouts, and wires declared in the circuit - * and their indeces, if applicable. Equivalent to the beginning + * and their indices, if applicable. Equivalent to the beginning * declarations in the VQM Module. ("input [31:0] ACCout", "wire gnd", etc.) * * ASSIGNMENT INFORMATION @@ -2062,7 +2062,7 @@ void echo_module_pins (ofstream& outfile, t_module* module){ /* Print all pin information from the VQM module. * Each pin has: * - a name - * - right and left indeces + * - right and left indices * - a type (direction) * * ARGUMENTS diff --git a/utils/vqm2blif/test/scripts/test_vqm2blif.sh b/utils/vqm2blif/test/scripts/test_vqm2blif.sh index 60c217a99e5..435e287c947 100755 --- a/utils/vqm2blif/test/scripts/test_vqm2blif.sh +++ b/utils/vqm2blif/test/scripts/test_vqm2blif.sh @@ -26,7 +26,7 @@ # Finally, the generated blif files have the extension ".test.blif", so please do not name any other files with this extension -## usefule functions ## +## useful functions ## # prints information regarding how to use the script print_usage() { @@ -41,9 +41,9 @@ print_usage() echo "" echo "Optional Arguments:" echo "-h, --help show the usage of the test script" - echo "-vqm2blif_location specify the vqm2blif program executable (defalt: \$VTR_ROOT/build/utils/vqm2blif/vqm2blif" - echo "-netlists specify the netlists used to evalute the vqm2blif program (default: \$VTR_ROOT/utils/vqm2blif/test/netlists/" - echo "-arch specify the architecture file that will be used to evalute the vqm2blif program" + echo "-vqm2blif_location specify the vqm2blif program executable (default: \$VTR_ROOT/build/utils/vqm2blif/vqm2blif" + echo "-netlists specify the netlists used to evaluate the vqm2blif program (default: \$VTR_ROOT/utils/vqm2blif/test/netlists/" + echo "-arch specify the architecture file that will be used to evaluate the vqm2blif program" echo " (default: \$VTR_ROOT/vtr_flow/arch/titan/stratixiv_arch.timing.xml)" echo "-create_golden creates a set of \"golden\" .blif netlists using the vqm2blif program. The generated netlists will have the same" echo " name as the provided .vqm netlists with the extension \"golden.blif\". The generated netlists can be found in the same" @@ -61,7 +61,7 @@ VTR_ROOT_DIR="$(dirname "$0")/../../../../" # location of the vqm program directory VQM_PROGRAM="$VTR_ROOT_DIR/build/utils/vqm2blif/vqm2blif" -# location of the deafult architecture file used when testing the vqm2blif program +# location of the default architecture file used when testing the vqm2blif program ARCH_FILE="$(dirname "$0")/../../../../vtr_flow/arch/titan/stratixiv_arch.timing.xml" # location of the default folder where all the test netlists are located (basic becnchmak tests) @@ -152,7 +152,7 @@ echo "VQM2BLIF Program Check" echo "----------------------" -# start by going through the user supplied directory and identify all the .vqm files. We will recursively go throught the directory and identify these .vqm files. We assume that any file found is going to be a test file. +# start by going through the user supplied directory and identify all the .vqm files. We will recursively go through the directory and identify these .vqm files. We assume that any file found is going to be a test file. find $TEST_FOLDER -name "*.vqm" -print0 | while read -d $'\0' vqm_file do # "create_golden" related variables @@ -186,7 +186,7 @@ do # now we need to run the vqm to blif program. # we only care about any outputs related to errors, so ignore standard output. - # We are running this process in a seperate sub shell to make sure that unwanted error messags are not reported in the terminal + # We are running this process in a separate sub shell to make sure that unwanted error messages are not reported in the terminal # we have two cases, one for testing and one for generating a golden set of outputs if [ $GEN_GOLDEN -eq 0 ]; then