From bcf7729665c7815c37c101ad36f1bba27ef4d87f Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Wed, 9 Jul 2025 14:15:21 -0400 Subject: [PATCH 01/31] Fix slang errors --- vtr_flow/benchmarks/verilog/LU32PEEng.v | 56 ++--- vtr_flow/benchmarks/verilog/LU64PEEng.v | 120 +++++----- vtr_flow/benchmarks/verilog/LU8PEEng.v | 118 +++++----- vtr_flow/benchmarks/verilog/and_latch.v | 4 +- vtr_flow/benchmarks/verilog/arm_core.v | 222 +++++++++--------- vtr_flow/benchmarks/verilog/boundtop.v | 6 +- vtr_flow/benchmarks/verilog/ch_intrinsics.v | 7 +- vtr_flow/benchmarks/verilog/mcml.v | 62 ++--- .../benchmarks/verilog/mkDelayWorker32B.v | 107 ++++----- vtr_flow/benchmarks/verilog/mkPktMerge.v | 27 ++- vtr_flow/benchmarks/verilog/mkSMAdapter4B.v | 22 +- .../verilog/multiclock_output_and_latch.v | 4 +- .../verilog/multiclock_reader_writer.v | 2 +- .../verilog/multiclock_separate_and_latch.v | 4 +- vtr_flow/benchmarks/verilog/or1200.v | 44 ++-- vtr_flow/benchmarks/verilog/raygentop.v | 6 +- vtr_flow/benchmarks/verilog/spree.v | 28 +-- 17 files changed, 430 insertions(+), 409 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/LU32PEEng.v b/vtr_flow/benchmarks/verilog/LU32PEEng.v index 25d12149554..b1d59f4a13d 100644 --- a/vtr_flow/benchmarks/verilog/LU32PEEng.v +++ b/vtr_flow/benchmarks/verilog/LU32PEEng.v @@ -2606,9 +2606,9 @@ assign j = |byteena_a; assign q = subwire | dummy; assign dummy = value_out & 1024'b0; -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( +dual_port_ram + # (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -2650,9 +2650,9 @@ assign j = |byteena_a; assign q = subwire | dummy; assign dummy = value_out & 1024'b0; -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( +dual_port_ram + # (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -2694,9 +2694,9 @@ assign j = |byteena_a; assign q = subwire | dummy; assign dummy = value_out & 1024'b0; -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( +dual_port_ram + # (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -2737,9 +2737,9 @@ assign j = |byteena_a; assign q = subwire | dummy; assign dummy = value_out & 1024'b0; -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( +dual_port_ram + # (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -2779,9 +2779,9 @@ module top_ram ( assign q = sub_wire0 | dummy; assign dummy = junk_output & 32'b0; - defparam inst2.ADDR_WIDTH = 12; - defparam inst2.DATA_WIDTH = 32; - dual_port_ram inst2( +dual_port_ram + # (.ADDR_WIDTH(12), .DATA_WIDTH(32)) +inst2( .clk (clk), .we1(wren), .we2(1'b0), @@ -3324,9 +3324,10 @@ begin // : STATUS_COUNTER else if ((wrreq) && (!rdreq) && (status_cnt != 64 )) status_cnt <= status_cnt + 1'b1; end - defparam ram_addr.ADDR_WIDTH = `rFIFORSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `rFIFOINPUTWIDTH; - dual_port_ram ram_addr( + + dual_port_ram + # (.ADDR_WIDTH(`rFIFORSIZEWIDTH), .DATA_WIDTH(`rFIFOINPUTWIDTH)) +ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input @@ -3454,9 +3455,9 @@ begin // : STATUS_COUNTER end assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0]; - defparam ram_addr.ADDR_WIDTH = `wFIFOSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `wFIFOINPUTWIDTH; - dual_port_ram ram_addr( + dual_port_ram + # (.ADDR_WIDTH(`wFIFOSIZEWIDTH), .DATA_WIDTH(`wFIFOINPUTWIDTH)) +ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input @@ -3531,9 +3532,9 @@ begin // : STATUS_COUNTER status_cnt <= status_cnt + 1; end - defparam ram_addr.ADDR_WIDTH = `aFIFOSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `aFIFOWIDTH; - dual_port_ram ram_addr( + dual_port_ram + # (.ADDR_WIDTH(`aFIFOSIZEWIDTH), .DATA_WIDTH(`aFIFOWIDTH)) +ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input @@ -3603,9 +3604,10 @@ begin // : STATUS_COUNTER else if ((wrreq) && (!rdreq) && (status_cnt != 16 )) status_cnt <= status_cnt + 1'b1; end - defparam ram_addr.ADDR_WIDTH = `mFIFOSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `mFIFOWIDTH; - dual_port_ram ram_addr( + + dual_port_ram + # (.ADDR_WIDTH(`mFIFOSIZEWIDTH), .DATA_WIDTH(`mFIFOWIDTH)) + ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input diff --git a/vtr_flow/benchmarks/verilog/LU64PEEng.v b/vtr_flow/benchmarks/verilog/LU64PEEng.v index e561bb89369..901b7718f10 100644 --- a/vtr_flow/benchmarks/verilog/LU64PEEng.v +++ b/vtr_flow/benchmarks/verilog/LU64PEEng.v @@ -3077,17 +3077,20 @@ module ram ( output [`RAMWIDTH-1:0] q; wire [`RAMWIDTH-1:0] value_out; wire [`RAMWIDTH-1:0] subwire; - assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] dummy; wire [`RAMWIDTH-1:0] uselessdata; - assign uselessdata = 2048'b0; -wire j; -assign j = |byteena_a; - wire [`RAMWIDTH-1:0]dummy; - assign dummy = value_out & 2048'b0; - -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( + wire j; + assign q = subwire | dummy; + + assign uselessdata = 2048'b0; + + assign j = |byteena_a; + + assign dummy = value_out & 2048'b0; + +dual_port_ram + # (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -3120,17 +3123,18 @@ module ram1 ( output [`RAMWIDTH-1:0] q; wire [`RAMWIDTH-1:0] value_out; wire [`RAMWIDTH-1:0] subwire; - assign q = subwire | dummy; wire [`RAMWIDTH-1:0] uselessdata; - assign uselessdata = 2048'b0; -wire j; -assign j = |byteena_a; - wire [`RAMWIDTH-1:0]dummy; - assign dummy = value_out & 2048'b0; - -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( + wire j; + wire [`RAMWIDTH-1:0]dummy; + + assign q = subwire | dummy; + assign uselessdata = 2048'b0; + assign j = |byteena_a; + assign dummy = value_out & 2048'b0; + +dual_port_ram + # (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -3163,17 +3167,18 @@ module ram2 ( output [`RAMWIDTH-1:0] q; wire [`RAMWIDTH-1:0] value_out; wire [`RAMWIDTH-1:0] subwire; - assign q = subwire | dummy; wire [`RAMWIDTH-1:0] uselessdata; - assign uselessdata = 2048'b0; -wire j; -assign j = |byteena_a; - wire [`RAMWIDTH-1:0]dummy; - assign dummy = value_out & 2048'b0; - -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( + wire j; + wire [`RAMWIDTH-1:0] dummy; + + assign q = subwire | dummy; + assign uselessdata = 2048'b0; + assign j = |byteena_a; + assign dummy = value_out & 2048'b0; + +dual_port_ram + # (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -3206,17 +3211,18 @@ module ram3 ( output [`RAMWIDTH-1:0] q; wire [`RAMWIDTH-1:0] value_out; wire [`RAMWIDTH-1:0] subwire; - assign q = subwire | dummy; wire [`RAMWIDTH-1:0] uselessdata; - assign uselessdata = 2048'b0; -wire j; -assign j = |byteena_a; - wire [`RAMWIDTH-1:0]dummy; - assign dummy = value_out & 2048'b0; - -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( + wire j; + wire [`RAMWIDTH-1:0]dummy; + + assign q = subwire | dummy; + assign uselessdata = 2048'b0; + assign j = |byteena_a; + assign dummy = value_out & 2048'b0; + +dual_port_ram + # (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -3252,13 +3258,14 @@ module top_ram ( wire [32-1:0] sub_wire0; wire [32-1:0] q; wire [32-1:0] junk_output; - assign q = sub_wire0 | dummy; wire[32-1:0] dummy; + assign q = sub_wire0 | dummy; assign dummy = junk_output & 32'b0; - defparam inst2.ADDR_WIDTH = 14; - defparam inst2.DATA_WIDTH = 32; - dual_port_ram inst2( + + dual_port_ram + # (.ADDR_WIDTH(14), .DATA_WIDTH(32)) +inst2( .clk (clk), .we1(wren), .we2(1'b0), @@ -3850,9 +3857,9 @@ begin // : STATUS_COUNTER status_cnt <= status_cnt + 1'b1; end - defparam ram_addr.ADDR_WIDTH = `rFIFORSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `rFIFOINPUTWIDTH; - dual_port_ram ram_addr( + dual_port_ram + # (.ADDR_WIDTH(`rFIFORSIZEWIDTH), .DATA_WIDTH(`rFIFOINPUTWIDTH)) +ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input @@ -3994,9 +4001,9 @@ begin // : STATUS_COUNTER end assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0]; - defparam ram_addr.ADDR_WIDTH = `wFIFOSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `wFIFOINPUTWIDTH; - dual_port_ram ram_addr( + dual_port_ram + # (.ADDR_WIDTH(`wFIFORSIZEWIDTH), .DATA_WIDTH(`wFIFOINPUTWIDTH)) +ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input @@ -4071,9 +4078,9 @@ begin // : STATUS_COUNTER status_cnt <= status_cnt + 1; end - defparam ram_addr.ADDR_WIDTH = `aFIFOSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `aFIFOWIDTH; - dual_port_ram ram_addr( + dual_port_ram + # (.ADDR_WIDTH(`aFIFOSIZEWIDTH), .DATA_WIDTH(`aFIFOWIDTH)) +ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input @@ -4143,9 +4150,10 @@ begin // : STATUS_COUNTER else if ((wrreq) && (!rdreq) && (status_cnt != 16 )) status_cnt <= status_cnt + 1'b1; end - defparam ram_addr.ADDR_WIDTH = `mFIFOSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `mFIFOWIDTH; - dual_port_ram ram_addr( + + dual_port_ram + # (.ADDR_WIDTH(`mFIFOSIZEWIDTH), .DATA_WIDTH(`mFIFOWIDTH)) + ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input diff --git a/vtr_flow/benchmarks/verilog/LU8PEEng.v b/vtr_flow/benchmarks/verilog/LU8PEEng.v index 9db3fd8dcf9..030f6a30278 100755 --- a/vtr_flow/benchmarks/verilog/LU8PEEng.v +++ b/vtr_flow/benchmarks/verilog/LU8PEEng.v @@ -2237,17 +2237,19 @@ module ram ( output [`RAMWIDTH-1:0] q; wire [`RAMWIDTH-1:0] value_out; wire [`RAMWIDTH-1:0] subwire; - assign q = subwire | dummy; wire [`RAMWIDTH-1:0] uselessdata; - assign uselessdata = 256'b0; -wire j; -assign j = |byteena_a; - wire [`RAMWIDTH-1:0]dummy; - assign dummy = value_out & 256'b0; - -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( + + wire j; + wire [`RAMWIDTH-1:0]dummy; + + assign uselessdata = 256'b0; + assign q = subwire | dummy; + assign j = |byteena_a; + assign dummy = value_out & 256'b0; + +dual_port_ram + #( .ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -2280,17 +2282,18 @@ module ram1 ( output [`RAMWIDTH-1:0] q; wire [`RAMWIDTH-1:0] value_out; wire [`RAMWIDTH-1:0] subwire; - assign q = subwire | dummy; wire [`RAMWIDTH-1:0] uselessdata; - assign uselessdata = 256'b0; -wire j; -assign j = |byteena_a; - wire [`RAMWIDTH-1:0]dummy; - assign dummy = value_out & 256'b0; - -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( + wire j; + wire [`RAMWIDTH-1:0]dummy; + + assign q = subwire | dummy; + assign uselessdata = 256'b0; + assign j = |byteena_a; + assign dummy = value_out & 256'b0; + +dual_port_ram + #( .ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -2323,17 +2326,18 @@ module ram2 ( output [`RAMWIDTH-1:0] q; wire [`RAMWIDTH-1:0] value_out; wire [`RAMWIDTH-1:0] subwire; - assign q = subwire | dummy; wire [`RAMWIDTH-1:0] uselessdata; - assign uselessdata = 256'b0; -wire j; -assign j = |byteena_a; - wire [`RAMWIDTH-1:0]dummy; - assign dummy = value_out & 256'b0; - -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( + wire j; + wire [`RAMWIDTH-1:0] dummy; + + assign q = subwire | dummy; + assign uselessdata = 256'b0; + assign j = |byteena_a; + assign dummy = value_out & 256'b0; + +dual_port_ram + #( .ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -2366,17 +2370,18 @@ module ram3 ( output [`RAMWIDTH-1:0] q; wire [`RAMWIDTH-1:0] value_out; wire [`RAMWIDTH-1:0] subwire; - assign q = subwire | dummy; wire [`RAMWIDTH-1:0] uselessdata; - assign uselessdata = 256'b0; -wire j; -assign j = |byteena_a; - wire [`RAMWIDTH-1:0]dummy; - assign dummy = value_out & 256'b0; - -defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH; -defparam inst1.DATA_WIDTH = `RAMWIDTH; -dual_port_ram inst1( + wire j; + wire [`RAMWIDTH-1:0]dummy; + + assign q = subwire | dummy; + assign uselessdata = 256'b0; + assign j = |byteena_a; + assign dummy = value_out & 256'b0; + +dual_port_ram + #( .ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH)) +inst1( .clk (clk), .we1(wren), .we2(1'b0), @@ -2412,13 +2417,13 @@ module top_ram ( wire [32-1:0] sub_wire0; wire [32-1:0] q; wire [32-1:0] junk_output; - assign q = sub_wire0 | dummy; wire[32-1:0] dummy; + assign q = sub_wire0 | dummy; assign dummy = junk_output & 32'b0; - defparam inst2.ADDR_WIDTH = 8; - defparam inst2.DATA_WIDTH = 32; - dual_port_ram inst2( + dual_port_ram + #( .ADDR_WIDTH(8), .DATA_WIDTH(32)) +inst2( .clk (clk), .we1(wren), .we2(1'b0), @@ -2898,9 +2903,9 @@ begin // : STATUS_COUNTER status_cnt <= status_cnt + 1'b1; end - defparam ram_addr.ADDR_WIDTH = `rFIFORSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `rFIFOINPUTWIDTH; - dual_port_ram ram_addr( + dual_port_ram + #( .ADDR_WIDTH(`rFIFORSIZEWIDTH), .DATA_WIDTH(`rFIFOINPUTWIDTH)) +ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input @@ -2986,9 +2991,9 @@ begin // : STATUS_COUNTER end assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0]; - defparam ram_addr.ADDR_WIDTH = `wFIFOSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `wFIFOINPUTWIDTH; - dual_port_ram ram_addr( + dual_port_ram + #( .ADDR_WIDTH(`wFIFORSIZEWIDTH), .DATA_WIDTH(`wFIFOINPUTWIDTH)) +ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input @@ -3063,9 +3068,9 @@ begin // : STATUS_COUNTER status_cnt <= status_cnt + 1; end - defparam ram_addr.ADDR_WIDTH = `aFIFOSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `aFIFOWIDTH; - dual_port_ram ram_addr( + dual_port_ram + #( .ADDR_WIDTH(`aFIFOSIZEWIDTH), .DATA_WIDTH(`aFIFOWIDTH)) +ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input @@ -3135,9 +3140,10 @@ begin // : STATUS_COUNTER else if ((wrreq) && (!rdreq) && (status_cnt != 16 )) status_cnt <= status_cnt + 1'b1; end - defparam ram_addr.ADDR_WIDTH = `mFIFOSIZEWIDTH; - defparam ram_addr.DATA_WIDTH = `mFIFOWIDTH; - dual_port_ram ram_addr( + + dual_port_ram + #( .ADDR_WIDTH(`mFIFOSIZEWIDTH), .DATA_WIDTH(`mFIFOWIDTH)) + ram_addr( .we1 (wrreq) , // write enable .we2 (rdreq) , // Read enable .addr1 (wr_pointer) , // address_0 input diff --git a/vtr_flow/benchmarks/verilog/and_latch.v b/vtr_flow/benchmarks/verilog/and_latch.v index 2c9ef7207fa..17f9c1e8865 100644 --- a/vtr_flow/benchmarks/verilog/and_latch.v +++ b/vtr_flow/benchmarks/verilog/and_latch.v @@ -10,7 +10,7 @@ module and_latch( input a_in; input b_in; - output out; + output reg out; // ASSIGN STATEMENTS always @(posedge clock) @@ -18,4 +18,4 @@ module and_latch( out <= a_in & b_in; end -endmodule \ No newline at end of file +endmodule diff --git a/vtr_flow/benchmarks/verilog/arm_core.v b/vtr_flow/benchmarks/verilog/arm_core.v index 907bc64202d..52dad585472 100644 --- a/vtr_flow/benchmarks/verilog/arm_core.v +++ b/vtr_flow/benchmarks/verilog/arm_core.v @@ -200,7 +200,7 @@ parameter WORD_SEL_LSB = 2; // = 2 input i_clk; input i_core_stall; -output o_stall; +output reg o_stall; // Read / Write requests from core input i_select; @@ -1197,7 +1197,7 @@ localparam [4:0] RST_WAIT1 = 5'd0, // Internal signals // ======================================================== wire [31:0] instruction; -wire [3:0] type; // regop, mem access etc. +wire [3:0] instruction_type; // regop, mem access etc. wire instruction_iabt; // abort flag, follows the instruction wire instruction_adex; // address exception flag, follows the instruction wire [31:0] instruction_address; // instruction virtual address, follows @@ -1429,7 +1429,7 @@ assign instruction = instruction_sel == 2'd0 ? fetch_instruction_r instruction_sel == 2'd3 ? hold_instruction : pre_fetch_instruction ; -assign type = instruction_sel == 2'd0 ? fetch_instruction_type_r : +assign instruction_type = instruction_sel == 2'd0 ? fetch_instruction_type_r : instruction_sel == 2'd1 ? saved_current_instruction_type : instruction_sel == 2'd3 ? hold_instruction_type : pre_fetch_instruction_type ; @@ -1467,16 +1467,16 @@ assign condition_nxt = instruction[31:28]; assign rm_sel_nxt = instruction[3:0]; assign rn_sel_nxt = branch ? 4'd15 : instruction[19:16]; // Use PC to calculate branch destination assign rs_sel_nxt = control_state == SWAP_WRITE ? instruction[3:0] : // Rm gets written out to memory - type == MTRANS ? mtrans_reg1 : + instruction_type == MTRANS ? mtrans_reg1 : branch ? 4'd15 : // Update the PC rds_use_rs ? instruction[11:8] : instruction[15:12] ; // Load from memory into registers -assign ldm_user_mode = type == MTRANS && {instruction[22:20],instruction[15]} == 4'b1010; -assign ldm_flags = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22]; -assign ldm_status_bits = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR; -assign load_rd_byte = (type == TRANS || type == SWAP) && instruction[22]; +assign ldm_user_mode = instruction_type == MTRANS && {instruction[22:20],instruction[15]} == 4'b1010; +assign ldm_flags = instruction_type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22]; +assign ldm_status_bits = instruction_type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR; +assign load_rd_byte = (instruction_type == TRANS || instruction_type == SWAP) && instruction[22]; assign load_rd_nxt = {ldm_flags, ldm_status_bits, ldm_user_mode, load_rd_byte, rs_sel_nxt}; @@ -1488,8 +1488,8 @@ assign offset24 = {{6{instruction[23]}}, instruction[23:0], 2'd0 }; assign imm8 = instruction[7:0]; assign immediate_shift_op = instruction[25]; -assign rds_use_rs = (type == REGOP && !instruction[25] && instruction[4]) || - (type == MULT && +assign rds_use_rs = (instruction_type == REGOP && !instruction[25] && instruction[4]) || + (instruction_type == MULT && (control_state == MULT_PROC1 || control_state == MULT_PROC2 || // instruction_valid && !interrupt )) ; @@ -1498,25 +1498,25 @@ assign rds_use_rs = (type == REGOP && !instruction[25] && instruction[ (instruction_valid && !interrupt_or_conflict))) ; -assign branch = type == BRANCH; +assign branch = instruction_type == BRANCH; assign opcode_compare = opcode == CMP || opcode == CMN || opcode == TEQ || opcode == TST ; -assign mem_op = type == TRANS; +assign mem_op = instruction_type == TRANS; assign load_op = mem_op && instruction[20]; assign store_op = mem_op && !instruction[20]; assign write_pc = (pc_wen_nxt && pc_sel_nxt != 3'd0) || load_pc_r || load_pc_nxt; assign current_write_pc = (pc_wen_nxt && pc_sel_nxt != 3'd0) || load_pc_nxt; -assign regop_set_flags = type == REGOP && instruction[20]; +assign regop_set_flags = instruction_type == REGOP && instruction[20]; assign mem_op_pre_indexed = instruction[24] && instruction[21]; assign mem_op_post_indexed = !instruction[24]; assign imm32_nxt = // add 0 to Rm - type == MULT ? { 32'd0 } : //MULT = 4'h1, + instruction_type == MULT ? { 32'd0 } : //MULT = 4'h1, // 4 x number of registers - type == MTRANS ? { mtrans_base_reg_change } : //MTRANS = 4'h4 - type == BRANCH ? { offset24 } : //BRANCH = 4'h5 - type == TRANS ? { offset12 } : //TRANS = 4'h3 + instruction_type == MTRANS ? { mtrans_base_reg_change } : //MTRANS = 4'h4 + instruction_type == BRANCH ? { offset24 } : //BRANCH = 4'h5 + instruction_type == TRANS ? { offset12 } : //TRANS = 4'h3 instruction[11:8] == 4'h0 ? { 24'd0, imm8[7:0] } : instruction[11:8] == 4'h1 ? { imm8[1:0], 24'd0, imm8[7:2] } : instruction[11:8] == 4'h2 ? { imm8[3:0], 24'd0, imm8[7:4] } : @@ -1551,11 +1551,11 @@ assign alu_function_nxt = { alu_swap_sel_nxt, // ======================================================== // Register Conflict Detection // ======================================================== -assign rn_valid = type == REGOP || type == MULT || type == SWAP || type == TRANS || type == MTRANS || type == CODTRANS; -assign rm_valid = type == REGOP || type == MULT || type == SWAP || (type == TRANS && immediate_shift_op); +assign rn_valid = instruction_type == REGOP || instruction_type == MULT || instruction_type == SWAP || instruction_type == TRANS || instruction_type == MTRANS || instruction_type == CODTRANS; +assign rm_valid = instruction_type == REGOP || instruction_type == MULT || instruction_type == SWAP || (instruction_type == TRANS && immediate_shift_op); assign rs_valid = rds_use_rs; -assign rd_valid = (type == TRANS && store_op) || (type == REGOP || type == SWAP); -assign stm_valid = type == MTRANS && !instruction[20]; // stm instruction +assign rd_valid = (instruction_type == TRANS && store_op) || (instruction_type == REGOP || instruction_type == SWAP); +assign stm_valid = instruction_type == MTRANS && !instruction[20]; // stm instruction assign rn_conflict1 = instruction_execute && rn_valid && ( load_rd_d1_nxt[4] && rn_sel_nxt == load_rd_d1_nxt[3:0] ); @@ -1771,15 +1771,15 @@ assign mtrans_base_reg_change = {25'd0, mtrans_num_registers, 2'd0}; assign firq_request = firq && !i_execute_status_bits[26]; assign irq_request = irq && !i_execute_status_bits[27]; -assign swi_request = type == SWI; +assign swi_request = instruction_type == SWI; assign dabt_request = dabt_reg; // copro15 and copro13 only supports reg trans opcodes // all other opcodes involving co-processors cause an // undefined instrution interrupt -assign und_request = type == CODTRANS || - type == COREGOP || - ( type == CORTRANS && instruction[11:8] != 4'd15 ); +assign und_request = instruction_type == CODTRANS || + instruction_type == COREGOP || + ( instruction_type == CORTRANS && instruction[11:8] != 4'd15 ); // in order of priority !! @@ -1832,7 +1832,7 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if ( type == SWI || und_request ) + if ( instruction_type == SWI || und_request ) status_bits_mode_nxt = interrupt_mode; else status_bits_mode_nxt = i_execute_status_bits[1:0]; @@ -1854,7 +1854,7 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if ( type == SWI || und_request ) + if ( instruction_type == SWI || und_request ) status_bits_irq_mask_nxt = 1'd1; else status_bits_irq_mask_nxt = o_status_bits_irq_mask; @@ -1881,7 +1881,7 @@ always @* always @* begin - if ( instruction_valid && !interrupt && !conflict &&(type == SWAP)) + if ( instruction_valid && !interrupt && !conflict &&(instruction_type == SWAP)) decode_exclusive_nxt = 1'd1; else decode_exclusive_nxt = 1'd0; @@ -1894,9 +1894,9 @@ always @* begin if ( mem_op ) decode_daccess_nxt = 1'd1; - else if ( type == MTRANS ) + else if ( instruction_type == MTRANS ) decode_daccess_nxt = 1'd1; - else if ( type == SWAP ) + else if ( instruction_type == SWAP ) decode_daccess_nxt = 1'd1; else decode_daccess_nxt = 1'd0; @@ -1915,7 +1915,7 @@ always @* always @* begin - if ( instruction_valid && !interrupt && !conflict && type == SWAP) + if ( instruction_valid && !interrupt && !conflict && instruction_type == SWAP) decode_iaccess_nxt = 1'd0; else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute &&( mtrans_num_registers > 4'd2 )) @@ -1936,7 +1936,7 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if ( type == CORTRANS && !und_request ) + if ( instruction_type == CORTRANS && !und_request ) begin if ( instruction[20] ) copro_operation_nxt = 2'd1; @@ -1961,13 +1961,13 @@ always @* begin if ( mem_op && (load_op && instruction[15:12] == 4'd15)) saved_current_instruction_wen = 1'd1; - else if ( type == MTRANS ) + else if ( instruction_type == MTRANS ) saved_current_instruction_wen = 1'd1; - else if ( type == MULT ) + else if ( instruction_type == MULT ) saved_current_instruction_wen = 1'd1; - else if ( type == SWAP ) + else if ( instruction_type == SWAP ) saved_current_instruction_wen = 1'd1; - else if ( type == CORTRANS && !und_request ) + else if ( instruction_type == CORTRANS && !und_request ) saved_current_instruction_wen = 1'd1; else saved_current_instruction_wen = 1'd0; @@ -2004,7 +2004,7 @@ always @* always @* begin - if ( instruction_valid && !interrupt && !conflict && type == MTRANS) + if ( instruction_valid && !interrupt && !conflict && instruction_type == MTRANS) // restore_base_address_nxt <= instruction[20] && // (instruction[15:0] & (1'd1 << instruction[19:16])); restore_base_address_nxt = instruction[20] && @@ -2033,7 +2033,7 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if ( type == REGOP ) + if ( instruction_type == REGOP ) begin if ( !immediate_shift_op && instruction[4] ) barrel_shift_amount_sel_nxt = 2'd1; @@ -2042,7 +2042,7 @@ always @* else barrel_shift_amount_sel_nxt = 2'd0; end - else if ( mem_op && ( type == TRANS && instruction[25] && shift_imm != 5'd0 ) ) + else if ( mem_op && ( instruction_type == TRANS && instruction[25] && shift_imm != 5'd0 ) ) barrel_shift_amount_sel_nxt = 2'd2; else barrel_shift_amount_sel_nxt = 2'd0; @@ -2055,12 +2055,12 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if(type == REGOP && !immediate_shift_op) + if(instruction_type == REGOP && !immediate_shift_op) barrel_shift_data_sel_nxt = 2'd2; - else if (mem_op && instruction[25] && type == TRANS) + else if (mem_op && instruction[25] && instruction_type == TRANS) barrel_shift_data_sel_nxt = 2'd2; - else if ( type == SWAP ) + else if ( instruction_type == SWAP ) barrel_shift_data_sel_nxt = 2'd2; else barrel_shift_data_sel_nxt = 2'd0; @@ -2075,9 +2075,9 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if ( type == REGOP && !immediate_shift_op) + if ( instruction_type == REGOP && !immediate_shift_op) barrel_shift_function_nxt = instruction[6:5]; - else if ( mem_op && type == TRANS && instruction[25] && shift_imm != 5'd0 ) + else if ( mem_op && instruction_type == TRANS && instruction[25] && shift_imm != 5'd0 ) barrel_shift_function_nxt = instruction[6:5]; else barrel_shift_function_nxt = 2'd0; @@ -2088,7 +2088,7 @@ always @* always @* begin - if ( instruction_valid && !interrupt && !conflict && type == MULT) + if ( instruction_valid && !interrupt && !conflict && instruction_type == MULT) begin multiply_function_nxt[0] = 1'd1; if( instruction[21] ) @@ -2114,15 +2114,15 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if( type == REGOP && !opcode_compare && instruction[15:12] == 4'd15) + if( instruction_type == REGOP && !opcode_compare && instruction[15:12] == 4'd15) iaddress_sel_nxt = 4'd1; - else if ( type == BRANCH ) + else if ( instruction_type == BRANCH ) iaddress_sel_nxt = 4'd1; - else if ( type == MTRANS && mtrans_num_registers > 4'd1) + else if ( instruction_type == MTRANS && mtrans_num_registers > 4'd1) iaddress_sel_nxt = 4'd3; - else if ( type == CORTRANS && !und_request ) + else if ( instruction_type == CORTRANS && !und_request ) iaddress_sel_nxt = 4'd3; - else if ( type == SWI || und_request ) + else if ( instruction_type == SWI || und_request ) iaddress_sel_nxt = 4'd2; else iaddress_sel_nxt = 4'd0; @@ -2134,8 +2134,8 @@ always @* else if ( control_state == MEM_WAIT1 && !conflict &&instruction_execute) iaddress_sel_nxt = 4'd3; - else if ( control_state == MEM_WAIT2 && !dabt && (( type == TRANS && instruction[15:12] == 4'd15 ) || - ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) + else if ( control_state == MEM_WAIT2 && !dabt && (( instruction_type == TRANS && instruction[15:12] == 4'd15 ) || + ( instruction_type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) iaddress_sel_nxt = 4'd3; @@ -2169,7 +2169,7 @@ always @* else daddress_sel_nxt = 4'd1; // alu out end - else if ( type == MTRANS ) + else if ( instruction_type == MTRANS ) if ( instruction[23] ) begin if ( instruction[24] ) // increment before @@ -2184,7 +2184,7 @@ always @* else daddress_sel_nxt = 4'd1; // alu out end - else if ( type == SWAP ) + else if ( instruction_type == SWAP ) daddress_sel_nxt = 4'd4; else daddress_sel_nxt = 4'd0; @@ -2204,21 +2204,21 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if ( type == REGOP && !opcode_compare && instruction[15:12] == 4'd15 ) + if ( instruction_type == REGOP && !opcode_compare && instruction[15:12] == 4'd15 ) pc_sel_nxt = 3'd1; else if ( mem_op && (mem_op_pre_indexed || mem_op_post_indexed) && rn_sel_nxt == 4'd15 ) pc_sel_nxt = 3'd1; - else if ( type == BRANCH ) + else if ( instruction_type == BRANCH ) pc_sel_nxt = 3'd1; - else if ( type == SWI || und_request ) + else if ( instruction_type == SWI || und_request ) pc_sel_nxt = 3'd2; else pc_sel_nxt = 3'd0; end else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) pc_sel_nxt = 3'd2; - else if ( control_state == MEM_WAIT2 && !dabt && (( type == TRANS && instruction[15:12] == 4'd15 ) || - ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) + else if ( control_state == MEM_WAIT2 && !dabt && (( instruction_type == TRANS && instruction[15:12] == 4'd15 ) || + ( instruction_type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) pc_sel_nxt = 3'd3; else if ( control_state == SWAP_WAIT1 && !dabt && instruction[15:12] == 4'd15 ) @@ -2235,15 +2235,15 @@ always @* begin if ( mem_op && ( load_op && instruction[15:12] == 4'd15 )) load_pc_nxt = 1'd1; - else if ( type == MTRANS && ( instruction[20] && mtrans_reg1 == 4'd15 )) + else if ( instruction_type == MTRANS && ( instruction[20] && mtrans_reg1 == 4'd15 )) load_pc_nxt = 1'd1; else load_pc_nxt = 1'd0; end else if ( control_state == MEM_WAIT1 && !conflict && instruction_execute) load_pc_nxt = load_pc_r; - else if ( control_state == MEM_WAIT2 && !dabt && (( type == TRANS && instruction[15:12] == 4'd15 ) || - ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) + else if ( control_state == MEM_WAIT2 && !dabt && (( instruction_type == TRANS && instruction[15:12] == 4'd15 ) || + ( instruction_type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) load_pc_nxt = load_pc_r; else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute && ( instruction[20] && mtrans_reg1 == 4'd15 )) @@ -2262,7 +2262,7 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if ( mem_op && store_op && type == TRANS && instruction[22] ) + if ( mem_op && store_op && instruction_type == TRANS && instruction[22] ) byte_enable_sel_nxt = 2'd1; else byte_enable_sel_nxt = 2'd0; @@ -2290,9 +2290,9 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if ( type == BRANCH && instruction[24] ) + if ( instruction_type == BRANCH && instruction[24] ) reg_write_sel_nxt = 3'd1; - else if ( type == SWI || und_request ) + else if ( instruction_type == SWI || und_request ) reg_write_sel_nxt = 3'd1; else reg_write_sel_nxt = 3'd0; @@ -2318,7 +2318,7 @@ always @* always @* begin - if ( instruction_valid && !interrupt && !conflict && type == MTRANS && instruction[22:20] == 3'b100 ) + if ( instruction_valid && !interrupt && !conflict && instruction_type == MTRANS && instruction[22:20] == 3'b100 ) o_user_mode_regs_store_nxt = 1'd1; else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute && instruction[22:20] == 3'b100 ) o_user_mode_regs_store_nxt = 1'd1; @@ -2331,7 +2331,7 @@ always @* always @* begin - if ( instruction_valid && !interrupt && !conflict && type == REGOP ) + if ( instruction_valid && !interrupt && !conflict && instruction_type == REGOP ) begin if ( opcode == RSB ) alu_swap_sel_nxt = 1'd1; @@ -2348,7 +2348,7 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if( type == REGOP ) + if( instruction_type == REGOP ) begin if ( opcode == SUB || opcode == CMP ) alu_not_sel_nxt = 1'd1; @@ -2367,7 +2367,7 @@ always @* end else if ( mem_op && !instruction[23]) alu_not_sel_nxt = 1'd1; - else if ( type == MTRANS && !instruction[23]) + else if ( instruction_type == MTRANS && !instruction[23]) alu_not_sel_nxt = 1'd1; else alu_not_sel_nxt = 1'd0; @@ -2381,7 +2381,7 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if( type == REGOP ) + if( instruction_type == REGOP ) begin if ( opcode == ADC ) alu_cin_sel_nxt = 2'd2; @@ -2398,7 +2398,7 @@ always @* end else if ( mem_op && !instruction[23]) alu_cin_sel_nxt = 2'd1; - else if ( type == MTRANS && !instruction[23]) + else if ( instruction_type == MTRANS && !instruction[23]) alu_cin_sel_nxt = 2'd1; else alu_cin_sel_nxt = 2'd0; @@ -2409,7 +2409,7 @@ always @* always @* begin - if ( instruction_valid && !interrupt && !conflict && type == REGOP ) + if ( instruction_valid && !interrupt && !conflict && instruction_type == REGOP ) begin if ( opcode == AND || opcode == TST ) alu_cout_sel_nxt = 1'd1; @@ -2435,7 +2435,7 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if( type == REGOP ) + if( instruction_type == REGOP ) begin if ( opcode == ADD || opcode == CMN ) alu_out_sel_nxt = 4'd1; @@ -2462,9 +2462,9 @@ always @* end else if ( mem_op ) alu_out_sel_nxt = 4'd1; - else if ( type == BRANCH ) + else if ( instruction_type == BRANCH ) alu_out_sel_nxt = 4'd1; - else if ( type == MTRANS ) + else if ( instruction_type == MTRANS ) alu_out_sel_nxt = 4'd1; else alu_out_sel_nxt = 4'd0; @@ -2479,7 +2479,7 @@ always @* begin if ( mem_op && store_op ) write_data_wen_nxt = 1'd1; - else if ( type == MTRANS && !instruction[20] ) + else if ( instruction_type == MTRANS && !instruction[20] ) write_data_wen_nxt = 1'd1; else write_data_wen_nxt = 1'd0; @@ -2496,7 +2496,7 @@ always @* always @* begin - if(instruction_valid && !interrupt && !conflict && (type == CORTRANS && !und_request) && ! instruction[20]) + if(instruction_valid && !interrupt && !conflict && (instruction_type == CORTRANS && !und_request) && ! instruction[20]) copro_write_data_wen_nxt = 1'd1; else copro_write_data_wen_nxt = 1'd0; @@ -2504,7 +2504,7 @@ always @* always @* begin - if(instruction_valid && !interrupt && !conflict && type == MTRANS) + if(instruction_valid && !interrupt && !conflict && instruction_type == MTRANS) base_address_wen_nxt = 1'd1; else base_address_wen_nxt = 1'd0; @@ -2516,7 +2516,7 @@ always @* begin if ( mem_op &&(load_op && instruction[15:12] == 4'd15) ) pc_wen_nxt = 1'd0; - else if ( type == MTRANS ) + else if ( instruction_type == MTRANS ) begin if ( mtrans_num_registers > 4'd1 ) pc_wen_nxt = 1'd0; @@ -2525,11 +2525,11 @@ always @* else pc_wen_nxt = 1'd1; end - else if ( type == MULT ) + else if ( instruction_type == MULT ) pc_wen_nxt = 1'd0; - else if ( type == SWAP ) + else if ( instruction_type == SWAP ) pc_wen_nxt = 1'd0; - else if ( type == CORTRANS && !und_request ) + else if ( instruction_type == CORTRANS && !und_request ) pc_wen_nxt = 1'd0; else pc_wen_nxt = 1'd1; @@ -2574,7 +2574,7 @@ always @* begin if ( instruction_valid && !interrupt && !conflict ) begin - if ( type == REGOP && !opcode_compare && instruction[15:12] != 4'd15) + if ( instruction_type == REGOP && !opcode_compare && instruction[15:12] != 4'd15) //reg_bank_wen_nxt = decode (instruction[15:12]); reg_bank_wen_nxt = instruction[15:12] == 4'h0 ? 15'h0001: instruction[15:12] == 4'h1 ? 15'h0002: @@ -2610,10 +2610,10 @@ always @* rn_sel_nxt == 4'hd ? 15'h2000: rn_sel_nxt == 4'he ? 15'h4000: 15'h0000; - else if ( type == BRANCH && instruction[24]) + else if ( instruction_type == BRANCH && instruction[24]) //reg_bank_wen_nxt = decode (4'd14); reg_bank_wen_nxt = 15'h4000; - else if ( type == MTRANS && instruction[21] ) + else if ( instruction_type == MTRANS && instruction[21] ) //reg_bank_wen_nxt = decode (rn_sel_nxt); reg_bank_wen_nxt = rn_sel_nxt == 4'h0 ? 15'h0001: rn_sel_nxt == 4'h1 ? 15'h0002: @@ -2631,7 +2631,7 @@ always @* rn_sel_nxt == 4'hd ? 15'h2000: rn_sel_nxt == 4'he ? 15'h4000: 15'h0000; - else if ( type == SWI || und_request ) + else if ( instruction_type == SWI || und_request ) //reg_bank_wen_nxt = decode (4'd14); reg_bank_wen_nxt = 15'h4000; else @@ -2660,7 +2660,7 @@ always @* 15'h0000; else if ( control_state == MULT_STORE ) begin - if ( type == MULT ) + if ( instruction_type == MULT ) //reg_bank_wen_nxt = decode ( instruction[19:16] ); reg_bank_wen_nxt = instruction[19:16] == 4'h0 ? 15'h0001: instruction[19:16] == 4'h1 ? 15'h0002: @@ -2736,7 +2736,7 @@ always @* begin if ( instruction_valid && !interrupt && !conflict) begin - if ( type == SWI || und_request ) + if ( instruction_type == SWI || und_request ) begin status_bits_mode_wen_nxt = 1'd1; status_bits_irq_mask_wen_nxt = 1'd1; @@ -2848,19 +2848,19 @@ always @* control_state_nxt = INT_WAIT1; else begin - if ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC + if ( instruction_type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC control_state_nxt = MEM_WAIT1; - else if ( type == MTRANS && !conflict && mtrans_num_registers != 5'd0 && mtrans_num_registers != 5'd1 ) + else if ( instruction_type == MTRANS && !conflict && mtrans_num_registers != 5'd0 && mtrans_num_registers != 5'd1 ) control_state_nxt = MTRANS_EXEC1; - else if ( type == MULT && !conflict ) + else if ( instruction_type == MULT && !conflict ) control_state_nxt = MULT_PROC1; - else if ( type == SWAP && !conflict ) + else if ( instruction_type == SWAP && !conflict ) control_state_nxt = SWAP_WRITE; - else if ( type == CORTRANS && !und_request && !conflict ) + else if ( instruction_type == CORTRANS && !und_request && !conflict ) control_state_nxt = COPRO_WAIT; else begin @@ -3075,10 +3075,10 @@ always @ ( posedge i_clk ) // to the pre-fetch instruction register // then when its decoded, a copy is saved to the saved_current_instruction // register - if ( type == MTRANS ) + if ( instruction_type == MTRANS ) begin saved_current_instruction <= mtrans_instruction_nxt; - saved_current_instruction_type <= type; + saved_current_instruction_type <= instruction_type; saved_current_instruction_iabt <= instruction_iabt; saved_current_instruction_adex <= instruction_adex; saved_current_instruction_address <= instruction_address; @@ -3087,7 +3087,7 @@ always @ ( posedge i_clk ) else if ( saved_current_instruction_wen ) begin saved_current_instruction <= instruction; - saved_current_instruction_type <= type; + saved_current_instruction_type <= instruction_type; saved_current_instruction_iabt <= instruction_iabt; saved_current_instruction_adex <= instruction_adex; saved_current_instruction_address <= instruction_address; @@ -3107,7 +3107,7 @@ always @ ( posedge i_clk ) // TODO possible to use saved_current_instruction instead and save some regs? hold_instruction <= instruction; - hold_instruction_type <= type; + hold_instruction_type <= instruction_type; hold_instruction_iabt <= instruction_iabt; hold_instruction_adex <= instruction_adex; hold_instruction_address <= instruction_address; @@ -3196,15 +3196,15 @@ assign xCONTROL_STATE = // "Fast_Interrupt" ; assign xTYPE = - type == REGOP ? "REGOP" : - type == MULT ? "MULT" : - type == SWAP ? "SWAP" : - type == TRANS ? "TRANS" : - type == MTRANS ? "MTRANS" : - type == BRANCH ? "BRANCH" : - type == CODTRANS ? "CODTRANS" : - type == COREGOP ? "COREGOP" : - type == CORTRANS ? "CORTRANS" : + instruction_type == REGOP ? "REGOP" : + instruction_type == MULT ? "MULT" : + instruction_type == SWAP ? "SWAP" : + instruction_type == TRANS ? "TRANS" : + instruction_type == MTRANS ? "MTRANS" : + instruction_type == BRANCH ? "BRANCH" : + instruction_type == CODTRANS ? "CODTRANS" : + instruction_type == COREGOP ? "COREGOP" : + instruction_type == CORTRANS ? "CORTRANS" : "SWI" ; @@ -3777,7 +3777,7 @@ input [1:0] i_function; output [31:0] o_out; output o_carry_out; -output o_stall; +output reg o_stall; /************************* IO Declarations *********************/ wire [31:0] quick_out; @@ -7080,7 +7080,7 @@ module a25_write_back( o_wb_read_data_valid, o_wb_load_rd, - i_daddress, + i_daddress // i_daddress_valid ); @@ -7372,10 +7372,10 @@ input i_wb_ack; // Signals // ---------------------------------------------------- -reg o_wb_adr = 32'd0; -reg o_wb_sel = 16'd0; +reg [31:0] o_wb_adr = 32'd0; +reg [15:0] o_wb_sel = 16'd0; reg o_wb_we = 1'd0; -reg o_wb_dat = 128'd0; +reg [127:0] o_wb_dat = 128'd0; reg o_wb_cyc = 1'd0; reg o_wb_stb = 1'd0; wire [WBUF-1:0] wbuf_valid; diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index 3beb662c402..99a22484554 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -1648,9 +1648,9 @@ reg temp_datavalid; -defparam new_ram.ADDR_WIDTH = 10; -defparam new_ram.DATA_WIDTH = 32; -single_port_ram new_ram( +single_port_ram + # (.ADDR_WIDTH(10), .DATA_WIDTH(32)) +new_ram( .clk (clk), .we(we), .data(datain), diff --git a/vtr_flow/benchmarks/verilog/ch_intrinsics.v b/vtr_flow/benchmarks/verilog/ch_intrinsics.v index 919263007ad..0ed49c01220 100755 --- a/vtr_flow/benchmarks/verilog/ch_intrinsics.v +++ b/vtr_flow/benchmarks/verilog/ch_intrinsics.v @@ -28,10 +28,9 @@ reg str_write_enable; reg [7:0] str_in; wire [7:0] str_out; - -defparam _str.ADDR_WIDTH = 5; -defparam _str.DATA_WIDTH = 8; -single_port_ram _str ( +single_port_ram + # (.ADDR_WIDTH(5), .DATA_WIDTH(8)) +_str ( .clk( clk ), .addr( str_address ), .we( str_write_enable ), diff --git a/vtr_flow/benchmarks/verilog/mcml.v b/vtr_flow/benchmarks/verilog/mcml.v index 3959f55bb04..10d9d82068c 100644 --- a/vtr_flow/benchmarks/verilog/mcml.v +++ b/vtr_flow/benchmarks/verilog/mcml.v @@ -1778,9 +1778,9 @@ assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; // assign dont_care_out = 32'b00000000000000000000000000000000; -defparam dpram1.ADDR_WIDTH = 13; -defparam dpram1.DATA_WIDTH = 32; -dual_port_ram dpram1( +dual_port_ram + # (.ADDR_WIDTH(13), .DATA_WIDTH(32)) +dpram1( .clk (clk), .we1(wren), .we2(const_zero), @@ -1815,9 +1815,9 @@ assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; // assign dont_care_out = 32'b00000000000000000000000000000000; -defparam dpram1.ADDR_WIDTH = 13; -defparam dpram1.DATA_WIDTH = 32; -dual_port_ram dpram1( +dual_port_ram + # (.ADDR_WIDTH(13), .DATA_WIDTH(32)) +dpram1( .clk (clk), .we1(wren), .we2(const_zero), @@ -1852,9 +1852,9 @@ assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; // assign dont_care_out = 32'b00000000000000000000000000000000; -defparam dpram1.ADDR_WIDTH = 13; -defparam dpram1.DATA_WIDTH = 32; -dual_port_ram dpram1( +dual_port_ram + # (.ADDR_WIDTH(13), .DATA_WIDTH(32)) +dpram1( .clk (clk), .we1(wren), .we2(const_zero), @@ -1889,9 +1889,9 @@ assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; // assign dont_care_out = 32'b00000000000000000000000000000000; -defparam dpram1.ADDR_WIDTH = 13; -defparam dpram1.DATA_WIDTH = 32; -dual_port_ram dpram1( +dual_port_ram + # (.ADDR_WIDTH(13), .DATA_WIDTH(32)) +dpram1( .clk (clk), .we1(wren), .we2(const_zero), @@ -1925,9 +1925,9 @@ assign const_zero = 1'b0; assign const_zero_data = 36'b000000000000000000000000000000000000; // assign dont_care_out = 36'b000000000000000000000000000000000000; -defparam dpram1.ADDR_WIDTH = 16; -defparam dpram1.DATA_WIDTH = 36; -dual_port_ram dpram1( +dual_port_ram + # (.ADDR_WIDTH(16), .DATA_WIDTH(36)) +dpram1( .clk (clk), .we1(wren), .we2(const_zero), @@ -1961,9 +1961,9 @@ assign const_zero = 1'b0; assign const_zero_data = 18'b000000000000000000; // assign dont_care_out = 18'b000000000000000000; -defparam dpram1.ADDR_WIDTH = 16; -defparam dpram1.DATA_WIDTH = 18; -dual_port_ram dpram1( +dual_port_ram + # (.ADDR_WIDTH(16), .DATA_WIDTH(18)) +dpram1( .clk (clk), .we1(wren), .we2(const_zero), @@ -1997,9 +1997,9 @@ assign const_zero = 1'b0; assign const_zero_data = 8'b00000000; // assign dont_care_out = 8'b00000000; -defparam dpram1.ADDR_WIDTH = 16; -defparam dpram1.DATA_WIDTH = 8; -dual_port_ram dpram1( +dual_port_ram + # (.ADDR_WIDTH(16), .DATA_WIDTH(8)) +dpram1( .clk (clk), .we1(wren), .we2(const_zero), @@ -10468,9 +10468,10 @@ reg [`BIT_WIDTH - 1:0] log_x; wire [31:0]blank; assign blank = 32'b000000000000000000000000000000; -defparam sram_replace0.ADDR_WIDTH = `MANTISSA_PRECISION; -defparam sram_replace0.DATA_WIDTH = 32; -single_port_ram sram_replace0 (.clk (clock), .addr (c_shifted_x), .data (blank), .we (1'b0), .out (mantissa)); + +single_port_ram + # (.ADDR_WIDTH(`MANTISSA_PRECISION), .DATA_WIDTH(32)) +sram_replace0 (.clk (clock), .addr (c_shifted_x), .data (blank), .we (1'b0), .out (mantissa)); // priority encoder //integer i; @@ -18323,13 +18324,14 @@ output [31:0] cosp; //Instantiate a single port ram for odin wire [31:0]blank; assign blank = 32'b000000000000000000000000000000; -defparam sinp_replace.ADDR_WIDTH = 10; -defparam sinp_replace.DATA_WIDTH = 32; -single_port_ram sinp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (sinp)); -defparam cosp_replace.ADDR_WIDTH = 10; -defparam cosp_replace.DATA_WIDTH = 32; -single_port_ram cosp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (cosp)); +single_port_ram +# (.ADDR_WIDTH(10), .DATA_WIDTH(32)) +sinp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (sinp)); + +single_port_ram +# (.ADDR_WIDTH(10), .DATA_WIDTH(32)) +cosp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (cosp)); endmodule diff --git a/vtr_flow/benchmarks/verilog/mkDelayWorker32B.v b/vtr_flow/benchmarks/verilog/mkDelayWorker32B.v index b5dc810431e..7fd0a06d4db 100644 --- a/vtr_flow/benchmarks/verilog/mkDelayWorker32B.v +++ b/vtr_flow/benchmarks/verilog/mkDelayWorker32B.v @@ -310,16 +310,6 @@ module mkDelayWorker32B(wciS0_Clk, wire dummy7; wire dummy8; wire dummy9; - assign dummy1 = &mesgRF_memory__DOB; - assign dummy2 = &mesgWF_memory__DOB; - assign dummy3 = &metaRF__D_OUT; - assign dummy4 = &metaWF__D_OUT ; - assign dummy5 = &wci_reqF__D_OUT; - assign dummy6 = &wide16Fa__D_OUT; - assign dummy7 = &wide16Fb__D_OUT; - assign dummy8 = &wmemi_respF__D_OUT; - assign dummy9 = &wsiS_reqFifo__D_OUT; - wire prevent_hang_wire; assign prevent_hang_wire = dummy1 & dummy2 & dummy3 & dummy4 &dummy5 & dummy6 & dummy7 & dummy8 & dummy9; assign prevent_hanging_nodes = prevent_hang_wire; @@ -1331,6 +1321,16 @@ module mkDelayWorker32B(wciS0_Clk, metaWF_RDY_deq__58_AND_NOT_wrtSerPos_11_EQ_3_1_ETC___d365, wci_cState_9_EQ_2_0_AND_dlyCtrl_4_BITS_3_TO_0__ETC___d397; + assign dummy1 = &mesgRF_memory__DOB; + assign dummy2 = &mesgWF_memory__DOB; + assign dummy3 = &metaRF__D_OUT; + assign dummy4 = &metaWF__D_OUT ; + assign dummy5 = &wci_reqF__D_OUT; + assign dummy6 = &wide16Fa__D_OUT; + assign dummy7 = &wide16Fb__D_OUT; + assign dummy8 = &wmemi_respF__D_OUT; + assign dummy9 = &wsiS_reqFifo__D_OUT; + // action method wciS0_mCmd assign CAN_FIRE_wciS0_mCmd = 1'b1 ; assign WILL_FIRE_wciS0_mCmd = 1'b1 ; @@ -1503,9 +1503,9 @@ module mkDelayWorker32B(wciS0_Clk, wire [255:0] dp_out_not_used1; wire [255:0] dp_out_not_used2; - defparam dpram1.ADDR_WIDTH = 10; - defparam dpram1.DATA_WIDTH = 256; - dual_port_ram dpram1 ( + dual_port_ram + # (.ADDR_WIDTH(10), .DATA_WIDTH(256)) + dpram1 ( .clk(wciS0_Clk), .addr1(mesgRF_memory__ADDRA), .addr2(mesgRF_memory__ADDRB), @@ -1523,9 +1523,9 @@ wire [255:0] dp_out_not_used2; // .DATA_WIDTH(32'b1056), // .MEMSIZE(11'b1024)) mesgWF_memory( - defparam dpram2.ADDR_WIDTH = 10; - defparam dpram2.DATA_WIDTH = 256; - dual_port_ram dpram2 ( + dual_port_ram + # (.ADDR_WIDTH(10), .DATA_WIDTH(256)) + dpram2 ( .clk(wciS0_Clk), .addr1(mesgWF_memory__ADDRA), .addr2(mesgWF_memory__ADDRB), @@ -4137,9 +4137,9 @@ reg full_n_r, empty_n_r; // manually assign assign junk_in = 32'b00000000000000000000000000000000; -defparam ram1.ADDR_WIDTH = `awa; -defparam ram1.DATA_WIDTH = `dwa; -dual_port_ram ram1( +dual_port_ram + # (.ADDR_WIDTH(`awa), .DATA_WIDTH(`dwa)) +ram1( .clk( clk ), .addr1( rp ), .addr2( wp ), @@ -4537,9 +4537,9 @@ reg full_n_r, empty_n_r; // manually assign assign junk_in = 32'b00000000000000000000000000000000; -defparam ram1.ADDR_WIDTH = `awa; -defparam ram1.DATA_WIDTH = `dwa; -dual_port_ram ram1( +dual_port_ram + # (.ADDR_WIDTH(`awa), .DATA_WIDTH(`dwa)) +ram1( .clk( clk ), .addr1( rp ), .addr2( wp ), @@ -4941,9 +4941,9 @@ reg full_n_r, empty_n_r; // manually assign assign junk_in = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam ram1.ADDR_WIDTH = `awa; -defparam ram1.DATA_WIDTH = `dwc; -dual_port_ram ram1( +dual_port_ram + # (.ADDR_WIDTH(`awa), .DATA_WIDTH(`dwc)) +ram1( .clk( clk ), .addr1( rp ), .addr2( wp ), @@ -5345,9 +5345,9 @@ reg full_n_r, empty_n_r; // manually assign assign junk_in = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam ram1.ADDR_WIDTH = `awa; -defparam ram1.DATA_WIDTH = `dwd; -dual_port_ram ram1( +dual_port_ram + # (.ADDR_WIDTH(`awa), .DATA_WIDTH(`dwd)) +ram1( .clk( clk ), .addr1( rp ), .addr2( wp ), @@ -5693,9 +5693,6 @@ parameter n=32; parameter max_size = 1< Date: Tue, 22 Jul 2025 11:03:32 -0300 Subject: [PATCH 02/31] Yosys-slang set up properly now in synthesis scripts --- libs/EXTERNAL/CMakeLists.txt | 6 +- vtr_flow/misc/yosys/slang_filelist.tcl | 76 ++++++++++++++++--- vtr_flow/misc/yosys/synthesis.tcl | 16 ++-- .../scripts/python_libs/vtr/parmys/parmys.py | 1 + vtr_flow/scripts/python_libs/vtr/paths.py | 1 + 5 files changed, 80 insertions(+), 20 deletions(-) diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index 4704e011d77..5378c7123f9 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -104,9 +104,9 @@ if (${WITH_PARMYS}) BINARY_DIR ${SLANG_BUILD_DIR} #Disabling UndrivenPass in slang_frontend.cc - PATCH_COMMAND - ${CMAKE_COMMAND} -E echo "Patching slang_frontend.cc to disable UndrivenPass" && - ${CMAKE_COMMAND} -DIN=${SLANG_FE} -P ${CMAKE_CURRENT_SOURCE_DIR}/patch_slang.cmake + # PATCH_COMMAND + # ${CMAKE_COMMAND} -E echo "Patching slang_frontend.cc to disable UndrivenPass" && + # ${CMAKE_COMMAND} -DIN=${SLANG_FE} -P ${CMAKE_CURRENT_SOURCE_DIR}/patch_slang.cmake CONFIGURE_COMMAND "" diff --git a/vtr_flow/misc/yosys/slang_filelist.tcl b/vtr_flow/misc/yosys/slang_filelist.tcl index 2f5364ef21b..79e59b142b3 100644 --- a/vtr_flow/misc/yosys/slang_filelist.tcl +++ b/vtr_flow/misc/yosys/slang_filelist.tcl @@ -8,17 +8,71 @@ # # Validates file extensions of input files and writes the names # of input files to the file list to be read by yosys-slang. - -proc build_filelist { circuit_list file_list } { - set fh [open $file_list "w"] - foreach f $circuit_list { - set ext [string tolower [file extension $f]] - if {$ext == ".sv" || $ext == ".svh" || $ext == ".v" || $ext == ".vh"} { - puts $fh $f - } else { - close $fh - error "Unsupported file type. Yosys-Slang accepts .sv .svh .v .vh. File {$f}" + +namespace eval ::slang { + + array set top_map { + and_latch.v {and_latch} + multiclock_output_and_latch.v {multiclock_output_and_latch} + arm_core.v arm_core + bgm.v bgm + blob_merge.v RLE_BlobMerging + boundtop.v paj_boundtop_hierarchy_no_mem + ch_intrinsics.v memset + diffeq1.v diffeq_paj_convert + diffeq2.v diffeq_f_systemC + LU8PEEng.v LU8PEEng + LU32PEEng.v LU32PEEng + LU64PEEng.v LU64PEEng + mcml.v mcml + mkDelayWorker32B.v mkDelayWorker32B + mkPktMerge.v mkPktMerge + mkSMAdapter4B.v mkSMAdapter4B + or1200.v or1200_flat + raygentop.v paj_raygentop_hierarchy_no_mem + sha.v sha1 + stereovision0.v sv_chip0_hierarchy_no_mem + stereovision1.v sv_chip1_hierarchy_no_mem + stereovision2.v sv_chip2_hierarchy_no_mem + stereovision3.v sv_chip3_hierarchy_no_mem + button_controller.sv top + display_control.sv top + debounce.sv top + timer.sv top + deepfreeze.style1.sv top + pulse_led.v top + clock.sv top + single_ff.v top + single_wire.v top + } + + + variable top_args {} + + + proc build_filelist { circuit_list file_list } { + variable top_args + variable top_map + set top_args {} + set fh [open $file_list "w"] + foreach f $circuit_list { + set ext [string tolower [file extension $f]] + if {$ext == ".sv" || $ext == ".svh" || $ext == ".v" || $ext == ".vh"} { + if {$f != "vtr_primitives.v" && $f != "vtr_blackboxes.v"} { + puts $fh $f + if {![info exists top_map($f)]} { + error "No top module set for $f" + } + set top_name $top_map($f) + lappend top_args --top $top_name + } + #puts $fh $f + } else { + close $fh + error "Unsupported file type. Yosys-Slang accepts .sv .svh .v .vh. File {$f}" + } } + close $fh + return $top_args } - close $fh } diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index 114c640b0ec..9b722c22138 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -1,10 +1,10 @@ yosys -import plugin -i parmys -read_verilog -nomem2reg +/parmys/vtr_primitives.v -setattr -mod -set keep_hierarchy 1 single_port_ram -setattr -mod -set keep_hierarchy 1 dual_port_ram -setattr -mod -set keep 1 dual_port_ram +#read_verilog -lib -nomem2reg +/parmys/vtr_primitives.v +#setattr -mod -set blackbox 1 single_port_ram +#setattr -mod -set blackbox 1 dual_port_ram +#setattr -mod -set keep 1 dual_port_ram # yosys-slang plugin error handling if {$env(PARSER) == "slang" } { @@ -39,11 +39,15 @@ if {$env(PARSER) == "slang" } { source [file join [pwd] "slang_filelist.tcl"] set readfile [file join [pwd] "filelist.txt"] #Writing names of circuit files to file list - build_filelist {XXX} $readfile + set slang_tops [::slang::build_filelist {XXX} $readfile] puts "Using Yosys read_slang command" - read_slang -C $readfile + #Read vtr_primitives library and user design verilog in same command + read_slang -v $env(PRIMITIVES) {*}$slang_tops -C $readfile } elseif {$env(PARSER) == "default" } { puts "Using Yosys read_verilog command" + read_verilog -nomem2reg +/parmys/vtr_primitives.v + setattr -mod -set keep_hierarchy 1 single_port_ram + setattr -mod -set keep_hierarchy 1 dual_port_ram read_verilog -sv -nolatches XXX } else { error "Invalid PARSER" diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index 72415d6b83a..75843010f57 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -251,6 +251,7 @@ def run( # set the parser if parmys_args["parser"] in YOSYS_PARSERS: os.environ["PARSER"] = parmys_args["parser"] + os.environ["PRIMITIVES"] = str(vtr.paths.vtr_primitives_path) del parmys_args["parser"] else: raise vtr.VtrError( diff --git a/vtr_flow/scripts/python_libs/vtr/paths.py b/vtr_flow/scripts/python_libs/vtr/paths.py index ce65148ffef..d6b1066f862 100644 --- a/vtr_flow/scripts/python_libs/vtr/paths.py +++ b/vtr_flow/scripts/python_libs/vtr/paths.py @@ -7,6 +7,7 @@ # VTR Paths vtr_flow_path = root_path / "vtr_flow" +vtr_primitives_path = root_path / "build" / "share" / "yosys" / "parmys" / "vtr_primitives.v" # ODIN paths odin_path = root_path / "odin_ii" From 725adbb5334bcb9a6fa5359495c9561efe8156f8 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Thu, 17 Jul 2025 10:26:08 -0300 Subject: [PATCH 03/31] Updating yosys-slang to latest version --- libs/EXTERNAL/yosys-slang | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/EXTERNAL/yosys-slang b/libs/EXTERNAL/yosys-slang index 76b83eb5b73..f106ae3a681 160000 --- a/libs/EXTERNAL/yosys-slang +++ b/libs/EXTERNAL/yosys-slang @@ -1 +1 @@ -Subproject commit 76b83eb5b73ba871797e6db7bc5fed10af380be4 +Subproject commit f106ae3a68155ee470d51b168c72282a1453171b From 5c1f4309dbd80686b94feb145cfe0ddb0a96d951 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 25 Jul 2025 15:24:40 -0400 Subject: [PATCH 04/31] Convert latches to flops --- vtr_flow/benchmarks/verilog/ch_intrinsics.v | 40 ++++++++++----------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/ch_intrinsics.v b/vtr_flow/benchmarks/verilog/ch_intrinsics.v index 0ed49c01220..3235899b759 100755 --- a/vtr_flow/benchmarks/verilog/ch_intrinsics.v +++ b/vtr_flow/benchmarks/verilog/ch_intrinsics.v @@ -42,28 +42,25 @@ _str ( wire tag; //must use all wires inside module..... -assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in; +assign tag = |memory_controller_address & | memory_controller_in; reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag; always @(posedge clk) prevTag <= tag; -always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in) + +always @(posedge clk) begin - -case(tag) - - 1'b0: + if (~tag) begin - str_address = memory_controller_address[5-1+0:0]; - str_write_enable = memory_controller_write_enable; - str_in[8-1:0] = memory_controller_in[8-1:0]; + str_address <= memory_controller_address[4:0]; + str_write_enable <= memory_controller_write_enable; + str_in[7:0] <= memory_controller_in[7:0]; end -endcase - -case(prevTag) +end - 1'b0: - memory_controller_out = str_out; -endcase +always @(posedge clk) +begin + if (~prevTag) + memory_controller_out <= str_out; end endmodule @@ -275,17 +272,16 @@ case(cur_state) end endcase -always @(cur_state) +always @(posedge clk) begin - case(cur_state) - 4'b1101: + if (cur_state == 4'b1101) begin - memory_controller_address = s_07; - memory_controller_write_enable = 1'b1; - memory_controller_in = c; + memory_controller_address <= s_07; + memory_controller_write_enable <= 1'b1; + memory_controller_in <= c; end - endcase + end endmodule From d8b8a3b87fc6330cf78a90ab1c938de62bedfc70 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 25 Jul 2025 20:24:23 -0400 Subject: [PATCH 05/31] Eliminate latches from slang post-processing by using stricter, more contemporary case statements --- vtr_flow/benchmarks/verilog/bgm.v | 38 +++++++++++++++++-------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/bgm.v b/vtr_flow/benchmarks/verilog/bgm.v index dbb32256a62..edc1c3f3898 100755 --- a/vtr_flow/benchmarks/verilog/bgm.v +++ b/vtr_flow/benchmarks/verilog/bgm.v @@ -716,7 +716,7 @@ always @(posedge clk) opa_r1 <= opa_r[30:0]; //always @(fpu_op_r3 or prod) -always @(prod) +always @(*) fract_denorm = prod; always @(posedge clk) @@ -1141,7 +1141,7 @@ always @(posedge clk) // // sign: 0=Posetive Number; 1=Negative Number -always @(signa or signb) +always @(*) case({signa, signb}) // synopsys full_case parallel_case 2'b00: sign_d = 0; 2'b01: sign_d = 1; @@ -1526,7 +1526,7 @@ module post_norm( fpu_op, opas, sign, rmode, fract_in, exp_in, exp_ovf, // Choose rounding mode - always @(rmode or exp_out_rnd0 or exp_out_rnd1 or exp_out_rnd2) + always @(*) case(rmode) // synopsys full_case parallel_case 2'b00: exp_out_rnd = exp_out_rnd0; 2'b01: exp_out_rnd = exp_out_rnd1; @@ -1534,7 +1534,7 @@ module post_norm( fpu_op, opas, sign, rmode, fract_in, exp_in, exp_ovf, 2'b11: exp_out_rnd = exp_out_rnd2; endcase - always @(rmode or fract_out_rnd0 or fract_out_rnd1 or fract_out_rnd2) + always @(*) case (rmode) // synopsys full_case parallel_case 2'b00: fract_out_rnd = fract_out_rnd0; 2'b01: fract_out_rnd = fract_out_rnd1; @@ -1684,7 +1684,7 @@ reg [5:0] fi_ldz_r0; assign fi_ldz = fi_ldz_r0; -always @(fract_in) +always @(*) begin if (fract_in[47:47] == 1'b1) fi_ldz_r0 = 6'd1; @@ -1784,6 +1784,7 @@ begin fi_ldz_r0 = 6'd48; else if (fract_in[47:0] == 48'b000000000000000000000000000000000000000000000000) fi_ldz_r0 = 6'd48; + else fi_ldz_r0 = 6'd0; end endmodule @@ -1800,7 +1801,7 @@ input [5:0] shift_value; output [47:0] shift_out; reg [47:0] shift_out; -always @(shift_value) +always @(*) begin case (shift_value) 6'b000000: shift_out = shift_in; @@ -1852,8 +1853,8 @@ begin 6'b101110: shift_out = shift_in >> 46; 6'b101111: shift_out = shift_in >> 47; 6'b110000: shift_out = shift_in >> 48; - - endcase + default: shift_out = shift_in; + endcase end //assign shift_out = shift_in >> shift_value; @@ -1871,7 +1872,7 @@ input [5:0] shift_value; output [47:0] shift_out; reg [47:0] shift_out; -always @(shift_value) +always @(*) begin case (shift_value) 6'b000000: shift_out = shift_in; @@ -1923,7 +1924,7 @@ begin 6'b101110: shift_out = shift_in << 46; 6'b101111: shift_out = shift_in << 47; 6'b110000: shift_out = shift_in << 48; - + default: shift_out = shift_in; endcase end @@ -1941,7 +1942,7 @@ input [5:0] shift_value; output [55:0] shift_out; reg [55:0] shift_out; -always @(shift_value) +always @(*) begin case (shift_value) 6'b000000: shift_out = shift_in; @@ -2000,7 +2001,8 @@ begin 6'b110101: shift_out = shift_in << 53; 6'b110110: shift_out = shift_in << 54; 6'b110111: shift_out = shift_in << 55; - 6'b111000: shift_out = shift_in << 56; + 6'b111000: shift_out = shift_in << 56; + default: shift_out = shift_in; endcase end @@ -2459,7 +2461,7 @@ assign adj_op_out[26:0] = {adj_op_out_sft[26:1], temp2 }; // --------------------------------------------------------------------- // Get truncated portion (sticky bit) -always @(exp_diff_sft or adj_op_tmp) +always @(*) case(exp_diff_sft) // synopsys full_case parallel_case 5'd00: sticky = 1'h0; 5'd01: sticky = adj_op_tmp[0]; @@ -2489,6 +2491,7 @@ always @(exp_diff_sft or adj_op_tmp) 5'd25: sticky = |adj_op_tmp[24:0]; 5'd26: sticky = |adj_op_tmp[25:0]; 5'd27: sticky = |adj_op_tmp[26:0]; + default: sticky = 1'h0; endcase // --------------------------------------------------------------------- @@ -2514,7 +2517,7 @@ always @(posedge clk) // Determine sign for the output // sign: 0=Positive Number; 1=Negative Number -always @(signa or signb or add or fractb_lt_fracta) +always @(*) case({signa, signb, add}) // synopsys full_case parallel_case // Add @@ -2567,7 +2570,7 @@ always @(posedge clk) // // add: 1=Add; 0=Subtract -always @(signa or signb or add) +always @(*) case({signa, signb, add}) // synopsys full_case parallel_case // Add @@ -2599,7 +2602,7 @@ input [4:0] shift_value; output [26:0] shift_out; reg [26:0] shift_out; -always @(shift_value) +always @(*) begin case (shift_value) 5'b00000: shift_out = shift_in; @@ -2630,7 +2633,8 @@ begin 5'b11001: shift_out = shift_in >> 25; 5'b11010: shift_out = shift_in >> 26; 5'b11011: shift_out = shift_in >> 27; - endcase + default: shift_out = shift_in; + endcase end From 0721dc80683351ef9cb30478cbd157912d042397 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Sun, 3 Aug 2025 11:43:57 -0400 Subject: [PATCH 06/31] Remove trailing comma in port list to resolve slang error --- vtr_flow/benchmarks/verilog/multiclock_reader_writer.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/benchmarks/verilog/multiclock_reader_writer.v b/vtr_flow/benchmarks/verilog/multiclock_reader_writer.v index 15e752ddf0c..37e7d49a3fb 100644 --- a/vtr_flow/benchmarks/verilog/multiclock_reader_writer.v +++ b/vtr_flow/benchmarks/verilog/multiclock_reader_writer.v @@ -2,7 +2,7 @@ module multiclock_reader_writer( clock_reader_head, clock_writer_head, in, - out, + out ); //INPUT From 07c9796aa4a0e1930ffeba29b68f45236db5f0e0 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 08:10:06 -0400 Subject: [PATCH 07/31] Convert combinational always blocks to always @*, add defaults to case statements to prevent latch inference --- vtr_flow/benchmarks/verilog/or1200.v | 83 ++++++++++++++-------------- 1 file changed, 40 insertions(+), 43 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/or1200.v b/vtr_flow/benchmarks/verilog/or1200.v index 5321b81b3dd..7999dc67d19 100644 --- a/vtr_flow/benchmarks/verilog/or1200.v +++ b/vtr_flow/benchmarks/verilog/or1200.v @@ -1690,8 +1690,7 @@ always @(posedge clk ) // // Async calculation of new PC value. This value is used for addressing the IC. // -always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type - or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin +always @(*) begin case ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case {2'b00, `OR1200_BRANCHOP_NOP}: begin pc = {pcreg + 30'b000000000000000000000000000001, 2'b0}; @@ -2212,7 +2211,7 @@ assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRA // // Generation of sel_a // -always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw) +always @(*) if ((id_insn[20:16] == rf_addrw) && rfwb_op[0]) sel_a = `OR1200_SEL_EX_FORW; else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid) @@ -2223,7 +2222,7 @@ always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw) // // Generation of sel_b // -always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw) +always @(*) if (sel_imm) sel_b = `OR1200_SEL_IMM; else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0]) @@ -2268,7 +2267,7 @@ end // // Decode of multicycle // -always @(id_insn) begin +always @(*) begin case (id_insn[31:26]) // synopsys parallel_case // l.lwz @@ -2319,7 +2318,7 @@ end // // Decode of imm_signextend // -always @(id_insn) begin +always @(*) begin case (id_insn[31:26]) // synopsys parallel_case // l.addi @@ -2362,7 +2361,7 @@ end // // LSU addr offset // -always @(lsu_op or ex_insn) begin +always @(*) begin lsu_addrofs[10:0] = ex_insn[10:0]; case(lsu_op) // synopsys parallel_case `OR1200_LSUOP_SB : @@ -3257,7 +3256,7 @@ end // // Forwarding logic for operand A register // -always @(ex_forw or wb_forw or rf_dataa or sel_a) begin +always @(*) begin case (sel_a) `OR1200_SEL_EX_FORW: @@ -3272,7 +3271,7 @@ end // // Forwarding logic for operand B register // -always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin +always @(*) begin case (sel_b) // synopsys parallel_case @@ -3369,7 +3368,7 @@ assign result_and = a & b; // Central part of the ALU // -always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) +always @(*) begin case (alu_op) // synopsys parallel_case @@ -3432,7 +3431,7 @@ end // // Examples for move byte, set bit and clear bit // -always @(cust5_op or cust5_limm or a or b) begin +always @(*) begin case (cust5_op) // synopsys parallel_case 5'h1 : begin case (cust5_limm[1:0]) @@ -3458,7 +3457,7 @@ end // // Generate flag and flag write enable // -always @(alu_op or result_sum or result_and or flagcomp) begin +always @(*) begin case (alu_op) // synopsys parallel_case `OR1200_ALUOP_ADD : begin @@ -3490,10 +3489,7 @@ end // // Generate SR[CY] write enable // -always @(alu_op or cy_sum - - - ) begin +always @(*) begin case (alu_op) // synopsys parallel_case `OR1200_ALUOP_ADD : begin @@ -3516,7 +3512,7 @@ end // // Shifts and rotation // -always @(shrot_op or a or b) begin +always @(*) begin case (shrot_op) // synopsys parallel_case 2'b00 : shifted_rotated = (a << 2); @@ -3534,7 +3530,7 @@ end // // First type of compare implementation // -always @(comp_op or a_eq_b or a_lt_b) begin +always @(*) begin case(comp_op[2:0]) // synopsys parallel_case `OR1200_COP_SFEQ: flagcomp = a_eq_b; @@ -3654,7 +3650,7 @@ assign div_tmp = mul_prod_r[63:32] - y; // Select result of current ALU operation to be forwarded // to next instruction and to WB stage // -always @(alu_op or mul_prod_r or mac_r or a or b) +always @(*) case(alu_op) `OR1200_ALUOP_DIV: @@ -3939,7 +3935,7 @@ assign spr_cs = unqualified_cs & {{read_spr | write_spr},{read_spr | write_spr}, // // Decoding of groups // -always @(spr_addr) +always @(*) case (spr_addr[15:11]) 5'b00000: unqualified_cs = 32'b00000000000000000000000000000001; 5'b00001: unqualified_cs = 32'b00000000000000000000000000000010; @@ -4063,8 +4059,7 @@ always @(posedge clk) // // MTSPR/MFSPR interface // -always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or - spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin +always @(*) begin case (sprs_op) // synopsys parallel_case `OR1200_ALUOP_MTSR : begin write_spr = 1'b1; @@ -4598,7 +4593,7 @@ reg [31:0] spr_dat_o; // SPR Read Data // // Implementation of VR, UPR and configuration registers // -always @(spr_addr) +always @(*) if (~|spr_addr[31:4]) case(spr_addr[3:0]) // synopsys parallel_case @@ -4686,9 +4681,8 @@ always @(spr_addr) end default: spr_dat_o = 32'h00000000; endcase - - - + else spr_dat_o = 32'h00000000; + // endmodule @@ -4752,7 +4746,7 @@ end // // Write-back multiplexer // -always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin +always @(*) begin case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) 2'b00: muxout = muxin_a; 2'b01: begin @@ -4843,7 +4837,7 @@ assign dcpu_adr_o = addrbase + addrofs; assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |lsu_op; assign dcpu_we_o = lsu_op[3]; assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE; -always @(lsu_op or dcpu_adr_o) +always @(*) case({lsu_op, dcpu_adr_o[1:0]}) {`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000; {`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100; @@ -4919,7 +4913,7 @@ assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll}; // // Mux to memdata[31:24] // -always @(lsu_op or addr or regdata) begin +always @(*) begin case({lsu_op, addr[1:0]}) // synopsys parallel_case {`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0]; {`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8]; @@ -4930,7 +4924,7 @@ end // // Mux to memdata[23:16] // -always @(lsu_op or addr or regdata) begin +always @(*) begin case({lsu_op, addr[1:0]}) // synopsys parallel_case {`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16]; default : memdata_hl = regdata[7:0]; @@ -4940,7 +4934,7 @@ end // // Mux to memdata[15:8] // -always @(lsu_op or addr or regdata) begin +always @(*) begin case({lsu_op, addr[1:0]}) // synopsys parallel_case {`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0]; default : memdata_lh = regdata[15:8]; @@ -4950,7 +4944,7 @@ end // // Mux to memdata[7:0] // -always @(regdata) +always @(*) memdata_ll = regdata[7:0]; endmodule @@ -4986,7 +4980,7 @@ assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll}; // // Byte select 0 // -always @(addr or lsu_op) begin +always @(*) begin case({lsu_op[2:0], addr}) // synopsys parallel_case {3'b011, 2'b00}: // lbz/lbs 0 sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3 @@ -5004,7 +4998,7 @@ end // // Byte select 1 // -always @(addr or lsu_op) begin +always @(*) begin case({lsu_op[2:0], addr}) // synopsys parallel_case {3'b010, 2'b00}: // lbz sel_byte1 = `OR1200_M2R_ZERO; // zero extend @@ -5026,7 +5020,7 @@ end // // Byte select 2 // -always @(addr or lsu_op) begin +always @(*) begin case({lsu_op[2:0], addr}) // synopsys parallel_case {3'b010, 2'b00}: sel_byte2 = `OR1200_M2R_ZERO; // lbz @@ -5052,7 +5046,7 @@ end // // Byte select 3 // -always @(addr or lsu_op) begin +always @(*) begin case({lsu_op[2:0], addr}) // synopsys parallel_case {3'b010, 2'b00}: sel_byte3 = `OR1200_M2R_ZERO; // zero extend // lbz @@ -5078,7 +5072,7 @@ end // // Byte 0 // -always @(sel_byte0 or memdata) +always @(*) begin case(sel_byte0) `OR1200_M2R_BYTE0: begin @@ -5101,7 +5095,7 @@ end // // Byte 1 // -always @(sel_byte1 or memdata) begin +always @(*) begin case(sel_byte1) @@ -5133,7 +5127,7 @@ end // // Byte 2 // -always @(sel_byte2 or memdata) begin +always @(*) begin case(sel_byte2) @@ -5162,7 +5156,7 @@ end // // Byte 3 // -always @(sel_byte3 or memdata) begin +always @(*) begin case(sel_byte3) `OR1200_M2R_ZERO: begin @@ -5182,7 +5176,10 @@ always @(sel_byte3 or memdata) begin end `OR1200_M2R_EXTB3: begin regdata_hh = {{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]}}; - end + end + default: begin + regdata_hh = {{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]}}; + end endcase end @@ -5195,7 +5192,7 @@ end // // Alignment // -always @(addr or memdata) begin +always @(*) begin case(addr) 2'b00: aligned = memdata; @@ -5212,7 +5209,7 @@ end // Bytes // /* -always @(lsu_op or aligned) begin +always @(*) begin case(lsu_op) `OR1200_LSUOP_LBZ: begin regdata[7:0] = aligned[31:24]; From 0a947105eebc2b41a33fe528f5107e381edc6748 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 08:10:33 -0400 Subject: [PATCH 08/31] Convert combinational always blocks to always @*, add defaults to case statements to prevent latch inference --- vtr_flow/benchmarks/verilog/boundtop.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index 99a22484554..c6732a81b2c 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -406,7 +406,7 @@ reg[31:0] temp_rgResultData; end end - always @(state or pending01 or pending10) + always @(*) begin case (state) 0 : @@ -1398,7 +1398,7 @@ endmodule end end - always @(state or trigger or count) + always @(*) begin case (state) 0 : @@ -1442,6 +1442,10 @@ endmodule end end + //Before adding default this could infer latches, so + //defaulting to holding previous state preserves deisgn intent + default: next_state = state; + endcase end endmodule From 726729c4b5c71d93be0b1c3bd51e35dcb1b0abec Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 08:13:11 -0400 Subject: [PATCH 09/31] Convert always blocks to always @(*) --- vtr_flow/benchmarks/verilog/raygentop.v | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index e6dfe7a2036..d3ee5074376 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -455,7 +455,7 @@ module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, ori end end - always @(state or CfgData_Ready) + always @(*) begin case (state) 0 : @@ -710,11 +710,7 @@ waddress <= temp_waddress; end end - always @(state or addr_ready or data_ready or waddress or datain or wantDir or - want_read or wantwriteback or writebackdata or writebackaddr or - fcount or fbpage or faddress or fbnextscanline or triID or wantshadedata or - wanttexel or texeladdr) - + always @(*) begin case (state) @@ -1098,7 +1094,7 @@ rgAddr <= temp_rgAddr; end end - always @(state or ack or as or rgDone) + always @(*) begin case (state) @@ -1378,7 +1374,7 @@ rgAddr <= temp_rgAddr; assign nas0 = temp_nas0; assign nas1 = temp_nas1; - always @(state or go or ack or busy or dirReady or addr or count or loaded) + always @(*) begin case (state) 0 : @@ -1781,7 +1777,7 @@ hit10c <= temp_hit10c; end - always @(state or rgResultReady or rgResultSource) + always @(*) begin case (state) 0 : @@ -2119,9 +2115,7 @@ shadedatac <= temp_shadedatac; end assign addrout = (process01 == 1'b1) ? addrout01 : addrout10 ; - always @(state or process01 or pending10 or ack or shadedataready or id01a or - id01b or id01c or id10a or id10b or id10c or selectuv or hita or - hitb or hitc or shadedata or pending01 or texmap or texelready) + always @(*) begin case (state) 0 : @@ -2664,7 +2658,7 @@ shadedatac <= temp_shadedatac; reg[15:0] col16; - always @(dataline or texelselect) + always @(*) begin case (texelselect) 2'b00 : @@ -2815,8 +2809,7 @@ shadedatac <= temp_shadedatac; reg[6:0] bvl; reg[6:0] bwl; - always @(selectuv or u01a or u01b or u01c or v01a or v01b or v01c or u10a or - u10b or u10c or v10a or v10b or v10c) + always @(*) begin case (selectuv) 3'b000 : From 4a6fda3b443988a3978fddac25a56888210a47e2 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 08:51:00 -0400 Subject: [PATCH 10/31] Convert all combinational always blocks to always @(*) --- vtr_flow/benchmarks/verilog/LU32PEEng.v | 30 +- vtr_flow/benchmarks/verilog/LU64PEEng.v | 30 +- vtr_flow/benchmarks/verilog/LU8PEEng.v | 30 +- vtr_flow/benchmarks/verilog/blob_merge.v | 2 +- vtr_flow/benchmarks/verilog/boundtop.v | 16 +- vtr_flow/benchmarks/verilog/mcml.v | 464 +++--------------- .../benchmarks/verilog/mkDelayWorker32B.v | 108 +--- vtr_flow/benchmarks/verilog/mkPktMerge.v | 8 +- vtr_flow/benchmarks/verilog/mkSMAdapter4B.v | 114 +---- vtr_flow/benchmarks/verilog/raygentop.v | 2 +- vtr_flow/benchmarks/verilog/spree.v | 8 +- vtr_flow/benchmarks/verilog/stereovision1.v | 6 +- vtr_flow/benchmarks/verilog/stereovision3.v | 2 +- 13 files changed, 179 insertions(+), 641 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/LU32PEEng.v b/vtr_flow/benchmarks/verilog/LU32PEEng.v index b1d59f4a13d..b0e604dcd2d 100644 --- a/vtr_flow/benchmarks/verilog/LU32PEEng.v +++ b/vtr_flow/benchmarks/verilog/LU32PEEng.v @@ -508,7 +508,7 @@ begin end end -always @ (cur_state) +always @ (*) begin case (cur_state) `MODE1: @@ -1064,7 +1064,7 @@ begin end // connections to top block memory ports -always @ (topSourceSel or topWriteSel or curReadDataLU or addResult31 or addResult30 or addResult29 or addResult28 or addResult27 or addResult26 or addResult25 or addResult24 or addResult23 or addResult22 or addResult21 or addResult20 or addResult19 or addResult18 or addResult17 or addResult16 or addResult15 or addResult14 or addResult13 or addResult12 or addResult11 or addResult10 or addResult9 or addResult8 or addResult7 or addResult6 or addResult5 or addResult4 or addResult3 or addResult2 or addResult1 or addResult0) +always @ (*) begin if (topSourceSel == 1'b0) case (topWriteSel) @@ -1765,7 +1765,7 @@ else if (waitCycles >7'b0000000) end // determining next state of main FSM -always @ (currentState or start or mode or m or n or counter or mdivk or topIdxCounter or doneFetchRow or divCounter or j or stop2 or waitCycles or stop or i1) +always @ (*) begin case (currentState) `cSETUP: @@ -1957,7 +1957,7 @@ begin endcase end -always @ (currentRowState or currentState or nextState or i1 or topIdxCounter or mdivk or msIdxCounter or readRowCounter or j or n or mode) +always @ (*) begin if (currentRowState == `cDONE_FETCH_ROW) doneFetchRow = 1; @@ -1975,7 +1975,7 @@ begin end // second FSM that controls the control signals to temp_top block -always @ (currentRowState or nextTopIdxCounter or n or startFetchRow or loadRow or topIdx or mdivk or nextState) +always @ (*) begin case (currentRowState) `cFETCH_ROW: @@ -3678,7 +3678,7 @@ module fpu_add (clock, a1, b1, sum); reg smaller; //smaller is 1 if a < b, 0 otherwise //Shift mantissa's to have the same exponent - always @ (a or b) begin + always @ (*) begin //a_exp = a[30:23]; //b_exp = b[30:23]; //a_man = {1'b1, a[22:0]}; @@ -3863,7 +3863,7 @@ module fpu_add (clock, a1, b1, sum); end //Perform the addition operation - always @ (a_man or b_man or a or b) begin + always @ (*) begin if (a_man < b_man) begin smaller = 1'b1; end else begin @@ -3908,7 +3908,7 @@ module fpu_add (clock, a1, b1, sum); //Store the number // we already have the sign. - always @ (sum_man or a_exp) begin + always @ (*) begin if (sum_man[24])begin //shif sum >> by 1, add 1 to the exponent. sum[22:0] = sum_man[23:1]; sum[30:23] = a_exp + 8'b00000001; @@ -4046,7 +4046,7 @@ module fpu_div(clock, n, d, div); end //Find the exponent, store in div_exp. - always @ (n_exp or d_exp) begin + always @ (*) begin if (n_exp >= d_exp) begin div_exp = 8'b01111111 + (n_exp - d_exp); end else begin @@ -4059,12 +4059,12 @@ module fpu_div(clock, n, d, div); //Store the result. Shift exponents appropriately. Store sign. //Sign - always @ (n_sign or d_sign) begin + always @ (*) begin div[31] = n_sign ^ d_sign; end //Mantissa and Exponent - always @ (div_man or div_exp) begin + always @ (*) begin if (div_man[23]) begin //do nothing div[22:0] = div_man[22:0]; div[30:23] = div_exp; @@ -4211,7 +4211,7 @@ module div_24b(numer, denom, res); // end //res[23] - always @ (denom_pad or numer23) begin + always @ (*) begin if (denom_pad[23:0] <= numer23[46:23]) begin res[23] = 1'b1; @@ -4856,7 +4856,7 @@ assign shiftb = b[23 - 1] ? 1 : // If number is denorm, shift the significand the appropriate amount // assign shifteda = a[`WSIG-1:0] << shifta; //Must have constant shifts for ODIN - always @ (shifta or a) begin + always @ (*) begin case (shifta) 5'b00001: begin shifteda = a[`WSIG-1:0] << 5'b00001; @@ -4959,7 +4959,7 @@ assign shiftb = b[23 - 1] ? 1 : assign norma = aisdenorm ? shifteda : {1'b1, a[`WSIG-1:0]}; // assign shiftedb = b[`WSIG-1:0] << shiftb; - always @ (shiftb or b) begin + always @ (*) begin case (shiftb) 5'b00001: begin shiftedb = b[`WSIG-1:0] << 5'b00001; @@ -5172,7 +5172,7 @@ module shift(normalized, selectedexp, shiftprod, shiftexp, shiftloss); // shift significand //assign postshift = preshift >> actualshiftamt; //We can only have constant shifts for ODIN: - always @ (actualshiftamt or preshift) begin + always @ (*) begin case (actualshiftamt) 5'b00001: begin postshift = preshift >> 5'b00001; diff --git a/vtr_flow/benchmarks/verilog/LU64PEEng.v b/vtr_flow/benchmarks/verilog/LU64PEEng.v index 901b7718f10..860e433da58 100644 --- a/vtr_flow/benchmarks/verilog/LU64PEEng.v +++ b/vtr_flow/benchmarks/verilog/LU64PEEng.v @@ -508,7 +508,7 @@ begin end end -always @ (cur_state) +always @ (*) begin case (cur_state) `MODE1: @@ -1224,7 +1224,7 @@ begin end // connections to top block memory ports -always @ (topSourceSel or topWriteSel or curReadDataLU or addResult63 or addResult62 or addResult61 or addResult60 or addResult59 or addResult58 or addResult57 or addResult56 or addResult55 or addResult54 or addResult53 or addResult52 or addResult51 or addResult50 or addResult49 or addResult48 or addResult47 or addResult46 or addResult45 or addResult44 or addResult43 or addResult42 or addResult41 or addResult40 or addResult39 or addResult38 or addResult37 or addResult36 or addResult35 or addResult34 or addResult33 or addResult32 or addResult31 or addResult30 or addResult29 or addResult28 or addResult27 or addResult26 or addResult25 or addResult24 or addResult23 or addResult22 or addResult21 or addResult20 or addResult19 or addResult18 or addResult17 or addResult16 or addResult15 or addResult14 or addResult13 or addResult12 or addResult11 or addResult10 or addResult9 or addResult8 or addResult7 or addResult6 or addResult5 or addResult4 or addResult3 or addResult2 or addResult1 or addResult0) +always @ (*) begin if (topSourceSel == 1'b0) case (topWriteSel) @@ -2149,7 +2149,7 @@ else if (waitCycles >8'b00000000) end // determining next state of main FSM -always @ (currentState or start or mode or m or n or counter or mdivk or topIdxCounter or doneFetchRow or divCounter or j or stop2 or waitCycles or stop or i1) +always @ (*) begin case (currentState) `cSETUP: @@ -2341,7 +2341,7 @@ begin endcase end -always @ (currentRowState or currentState or nextState or i1 or topIdxCounter or mdivk or msIdxCounter or readRowCounter or j or n or mode) +always @ (*) begin if (currentRowState == `cDONE_FETCH_ROW) doneFetchRow = 1; @@ -2359,7 +2359,7 @@ begin end // second FSM that controls the control signals to temp_top block -always @ (currentRowState or nextTopIdxCounter or n or startFetchRow or loadRow or topIdx or mdivk or nextState) +always @ (*) begin case (currentRowState) `cFETCH_ROW: @@ -4224,7 +4224,7 @@ module fpu_add (clock, a1, b1, sum); reg smaller; //smaller is 1 if a < b, 0 otherwise //Shift mantissa's to have the same exponent - always @ (a or b) begin + always @ (*) begin //a_exp = a[30:23]; //b_exp = b[30:23]; //a_man = {1'b1, a[22:0]}; @@ -4409,7 +4409,7 @@ module fpu_add (clock, a1, b1, sum); end //Perform the addition operation - always @ (a_man or b_man or a or b) begin + always @ (*) begin if (a_man < b_man) begin smaller = 1'b1; end else begin @@ -4454,7 +4454,7 @@ module fpu_add (clock, a1, b1, sum); //Store the number // we already have the sign. - always @ (sum_man or a_exp) begin + always @ (*) begin if (sum_man[24])begin //shif sum >> by 1, add 1 to the exponent. sum[22:0] = sum_man[23:1]; sum[30:23] = a_exp + 8'b00000001; @@ -4592,7 +4592,7 @@ module fpu_div(clock, n, d, div); end //Find the exponent, store in div_exp. - always @ (n_exp or d_exp) begin + always @ (*) begin if (n_exp >= d_exp) begin div_exp = 8'b01111111 + (n_exp - d_exp); end else begin @@ -4605,12 +4605,12 @@ module fpu_div(clock, n, d, div); //Store the result. Shift exponents appropriately. Store sign. //Sign - always @ (n_sign or d_sign) begin + always @ (*) begin div[31] = n_sign ^ d_sign; end //Mantissa and Exponent - always @ (div_man or div_exp) begin + always @ (*) begin if (div_man[23]) begin //do nothing div[22:0] = div_man[22:0]; div[30:23] = div_exp; @@ -4757,7 +4757,7 @@ module div_24b(numer, denom, res); // end //res[23] - always @ (denom_pad or numer23) begin + always @ (*) begin if (denom_pad[23:0] <= numer23[46:23]) begin res[23] = 1'b1; @@ -5402,7 +5402,7 @@ assign shiftb = b[23 - 1] ? 1 : // If number is denorm, shift the significand the appropriate amount // assign shifteda = a[`WSIG-1:0] << shifta; //Must have constant shifts for ODIN - always @ (shifta or a) begin + always @ (*) begin case (shifta) 5'b00001: begin shifteda = a[`WSIG-1:0] << 5'b00001; @@ -5505,7 +5505,7 @@ assign shiftb = b[23 - 1] ? 1 : assign norma = aisdenorm ? shifteda : {1'b1, a[`WSIG-1:0]}; // assign shiftedb = b[`WSIG-1:0] << shiftb; - always @ (shiftb or b) begin + always @ (*) begin case (shiftb) 5'b00001: begin shiftedb = b[`WSIG-1:0] << 5'b00001; @@ -5718,7 +5718,7 @@ module shift(normalized, selectedexp, shiftprod, shiftexp, shiftloss); // shift significand //assign postshift = preshift >> actualshiftamt; //We can only have constant shifts for ODIN: - always @ (actualshiftamt or preshift) begin + always @ (*) begin case (actualshiftamt) 5'b00001: begin postshift = preshift >> 5'b00001; diff --git a/vtr_flow/benchmarks/verilog/LU8PEEng.v b/vtr_flow/benchmarks/verilog/LU8PEEng.v index 030f6a30278..6283e42517a 100755 --- a/vtr_flow/benchmarks/verilog/LU8PEEng.v +++ b/vtr_flow/benchmarks/verilog/LU8PEEng.v @@ -508,7 +508,7 @@ begin end end -always @ (cur_state) +always @ (*) begin case (cur_state) `MODE1: @@ -944,7 +944,7 @@ begin end // connections to top block memory ports -always @ (topSourceSel or topWriteSel or curReadDataLU or addResult7 or addResult6 or addResult5 or addResult4 or addResult3 or addResult2 or addResult1 or addResult0) +always @ (*) begin if (topSourceSel == 1'b0) case (topWriteSel) @@ -1477,7 +1477,7 @@ else if (waitCycles >5'b00000) end // determining next state of main FSM -always @ (currentState or start or mode or m or n or counter or mdivk or topIdxCounter or doneFetchRow or divCounter or j or stop2 or waitCycles or stop or i1) +always @ (*) begin case (currentState) `cSETUP: @@ -1669,7 +1669,7 @@ begin endcase end -always @ (currentRowState or currentState or nextState or i1 or topIdxCounter or mdivk or msIdxCounter or readRowCounter or j or n or mode) +always @ (*) begin if (currentRowState == `cDONE_FETCH_ROW) doneFetchRow = 1; @@ -1687,7 +1687,7 @@ begin end // second FSM that controls the control signals to temp_top block -always @ (currentRowState or nextTopIdxCounter or n or startFetchRow or loadRow or topIdx or mdivk or nextState) +always @ (*) begin case (currentRowState) `cFETCH_ROW: @@ -3214,7 +3214,7 @@ module fpu_add (clock, a1, b1, sum); reg smaller; //smaller is 1 if a < b, 0 otherwise //Shift mantissa's to have the same exponent - always @ (a or b) begin + always @ (*) begin //a_exp = a[30:23]; //b_exp = b[30:23]; //a_man = {1'b1, a[22:0]}; @@ -3399,7 +3399,7 @@ module fpu_add (clock, a1, b1, sum); end //Perform the addition operation - always @ (a_man or b_man or a or b) begin + always @ (*) begin if (a_man < b_man) begin smaller = 1'b1; end else begin @@ -3444,7 +3444,7 @@ module fpu_add (clock, a1, b1, sum); //Store the number // we already have the sign. - always @ (sum_man or a_exp) begin + always @ (*) begin if (sum_man[24])begin //shif sum >> by 1, add 1 to the exponent. sum[22:0] = sum_man[23:1]; sum[30:23] = a_exp + 8'b00000001; @@ -3582,7 +3582,7 @@ module fpu_div(clock, n, d, div); end //Find the exponent, store in div_exp. - always @ (n_exp or d_exp) begin + always @ (*) begin if (n_exp >= d_exp) begin div_exp = 8'b01111111 + (n_exp - d_exp); end else begin @@ -3595,12 +3595,12 @@ module fpu_div(clock, n, d, div); //Store the result. Shift exponents appropriately. Store sign. //Sign - always @ (n_sign or d_sign) begin + always @ (*) begin div[31] = n_sign ^ d_sign; end //Mantissa and Exponent - always @ (div_man or div_exp) begin + always @ (*) begin if (div_man[23]) begin //do nothing div[22:0] = div_man[22:0]; div[30:23] = div_exp; @@ -3747,7 +3747,7 @@ module div_24b(numer, denom, res); // end //res[23] - always @ (denom_pad or numer23) begin + always @ (*) begin if (denom_pad[23:0] <= numer23[46:23]) begin res[23] = 1'b1; @@ -4392,7 +4392,7 @@ assign shiftb = b[23 - 1] ? 1 : // If number is denorm, shift the significand the appropriate amount // assign shifteda = a[`WSIG-1:0] << shifta; //Must have constant shifts for ODIN - always @ (shifta or a) begin + always @ (*) begin case (shifta) 5'b00001: begin shifteda = a[`WSIG-1:0] << 5'b00001; @@ -4495,7 +4495,7 @@ assign shiftb = b[23 - 1] ? 1 : assign norma = aisdenorm ? shifteda : {1'b1, a[`WSIG-1:0]}; // assign shiftedb = b[`WSIG-1:0] << shiftb; - always @ (shiftb or b) begin + always @ (*) begin case (shiftb) 5'b00001: begin shiftedb = b[`WSIG-1:0] << 5'b00001; @@ -4708,7 +4708,7 @@ module shift(normalized, selectedexp, shiftprod, shiftexp, shiftloss); // shift significand //assign postshift = preshift >> actualshiftamt; //We can only have constant shifts for ODIN: - always @ (actualshiftamt or preshift) begin + always @ (*) begin case (actualshiftamt) 5'b00001: begin postshift = preshift >> 5'b00001; diff --git a/vtr_flow/benchmarks/verilog/blob_merge.v b/vtr_flow/benchmarks/verilog/blob_merge.v index e7b8365331b..57edc27cf4b 100755 --- a/vtr_flow/benchmarks/verilog/blob_merge.v +++ b/vtr_flow/benchmarks/verilog/blob_merge.v @@ -1447,7 +1447,7 @@ module divider(//clk, reg [10:0] divider_copy8; wire [10:0] remainder8; -always @ (opa or opb) +always @ (*) begin //stage initial quotient0 = 11'b00000000000; diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index c6732a81b2c..8ba03ee12de 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -234,7 +234,7 @@ assign raygroupout = raygroupout01 | raygroupout10 ; assign cntreset = cntreset01 | cntreset10 ; // reset <= reset01 or reset10; - always @(BoundNodeID01 or BoundNodeID10 or resultid) + always @(*) begin if (resultid == 2'b01) begin @@ -1513,7 +1513,7 @@ reg temp_datavalid; end end - always @(state or addr_ready or data_ready or addrvalid or datavalid) + always @(*) begin case (state) @@ -1738,8 +1738,7 @@ new_ram( end end - always @(state or addr_ready or data_ready or waddress or datain or addrvalid or - datavalid or addr) + always @(*) begin case (state) 0 : @@ -2013,7 +2012,7 @@ module resultinterface (t1b, t2b, t3b, u1b, u2b, u3b, v1b, v2b, v3b, id1b, id2b, end end - always @(state or resultready) + always @(*) begin case (state) 0 : @@ -2221,7 +2220,7 @@ module sortedstack (keyin, datain, write, reset, peekdata, globalreset, clk); assign peekdata[(7 + 1) * (13) - 1:7 * (13)] = ((full7) == 1'b1) ? data7 : 0; // Select the proper insertion point - always @(keyin or key0 or key1 or key2 or key3 or key4 or key5 or key6 or key7 or full0 or full1 or full2 or full3 or full4 or full5 or full6 or full7) + always @(*) begin /* PAJ -- changed for loops */ @@ -2502,7 +2501,7 @@ module listhandler (dataarrayin, commit, hitmask, ack, boundnodeID, level, empty assign empty = (lvempty == 3'b111 & busy == 1'b0) ? 1'b1 : 1'b0 ; assign dataready = ((((dataout[10]) == 1'b1 & (hitmask[0]) == 1'b1) | ((dataout[11]) == 1'b1 & (hitmask[1]) == 1'b1) | ((dataout[12]) == 1'b1 & (hitmask[2]) == 1'b1)) & (empty == 1'b0) & (busy == 1'b0)) ? 1'b1 : 1'b0 ; - always @(offset0 or offset1 or offset2 or address) + always @(*) begin address[4:3] = readlevel ; @@ -2554,8 +2553,7 @@ module listhandler (dataarrayin, commit, hitmask, ack, boundnodeID, level, empty end end - always @(state or commit or ack or address or dataarrayin or reset or dataready or - empty) + always @(*) begin case (state) diff --git a/vtr_flow/benchmarks/verilog/mcml.v b/vtr_flow/benchmarks/verilog/mcml.v index 10d9d82068c..d61cf38e294 100644 --- a/vtr_flow/benchmarks/verilog/mcml.v +++ b/vtr_flow/benchmarks/verilog/mcml.v @@ -489,7 +489,7 @@ PhotonCalculator u_calc ( ); // Mux to read the absorbtion array -always @(r_state or done or r_absorb_read_counter or r_absorb_write_counter or absorb_wraddress or absorb_data or absorb_rdaddress or absorb_data or absorb_wren ) +always @(*) begin if(r_state == RESET_MEM_ST) begin @@ -518,112 +518,7 @@ end // 1. Read constants // 2. Wait for completion // 3. Write data back -always @(r_state or r_absorb_read_counter or r_absorb_write_counter or result or r_toggle or r_counter or read_constants or constants or done - or inc_result or mem_cost or mem_sint or absorb_q - or r_const__103 - or r_const__102 - or r_const__101 - or r_const__100 - or r_const__99 - or r_const__98 - or r_const__97 - or r_const__96 - or r_const__95 - or r_const__94 - or r_const__93 - or r_const__92 - or r_const__91 - or r_const__90 - or r_const__89 - or r_const__88 - or r_const__87 - or r_const__86 - or r_const__85 - or r_const__84 - or r_const__83 - or r_const__82 - or r_const__81 - or r_const__80 - or r_const__79 - or r_const__78 - or r_const__77 - or r_const__76 - or r_const__75 - or r_const__74 - or r_const__73 - or r_const__72 - or r_const__71 - or r_const__70 - or r_const__69 - or r_const__68 - or r_const__67 - or r_const__66 - or r_const__65 - or r_const__64 - or r_const__63 - or r_const__62 - or r_const__61 - or r_const__60 - or r_const__59 - or r_const__58 - or r_const__57 - or r_const__56 - or r_const__55 - or r_const__54 - or r_const__53 - or r_const__52 - or r_const__51 - or r_const__50 - or r_const__49 - or r_const__48 - or r_const__47 - or r_const__46 - or r_const__45 - or r_const__44 - or r_const__43 - or r_const__42 - or r_const__41 - or r_const__40 - or r_const__39 - or r_const__38 - or r_const__37 - or r_const__36 - or r_const__35 - or r_const__34 - or r_const__33 - or r_const__32 - or r_const__31 - or r_const__30 - or r_const__29 - or r_const__28 - or r_const__27 - or r_const__26 - or r_const__25 - or r_const__24 - or r_const__23 - or r_const__22 - or r_const__21 - or r_const__20 - or r_const__19 - or r_const__18 - or r_const__17 - or r_const__16 - or r_const__15 - or r_const__14 - or r_const__13 - or r_const__12 - or r_const__11 - or r_const__10 - or r_const__9 - or r_const__8 - or r_const__7 - or r_const__6 - or r_const__5 - or r_const__4 - or r_const__3 - or r_const__2 - or r_const__1 - or r_const__0) begin +always @(*) begin // Initialize data //for(i = 0; i < 104; i = i + 1) begin // c_const[i] = r_const[i]; @@ -2429,7 +2324,7 @@ DropSpinWrapper dropSpin ( ); // Determine how many photons left -always @(r_num_photons_left or dead_Roulette or r_done or r_counter) +always @(*) begin //c_num_photons_left = r_num_photons_left; //c_counter = 0; @@ -2455,7 +2350,7 @@ begin end // Only state info is done -always @(r_done or r_counter) +always @(*) begin //c_done = r_done; if(r_counter > `PIPELINE_DEPTH_UPPER_LIMIT) @@ -2467,9 +2362,7 @@ begin end // Create mux to mover -always @(dead_Roulette or initialWeight or r_num_photons_left or x_Roulette or y_Roulette or z_Roulette or - ux_Roulette or uy_Roulette or uz_Roulette or sz_Roulette or sr_Roulette or sleftz_Roulette or - sleftr_Roulette or layer_Roulette or weight_Roulette or dead_Roulette) +always @(*) begin if(dead_Roulette) begin @@ -2674,12 +2567,7 @@ wire reset_new; assign reset_new = reset & bigOr; // multiplex constants -always @(layer_moverMux or OneOver_MutMaxrad_0 or OneOver_MutMaxdep_0 or OneOver_Mut_0 or - OneOver_MutMaxrad_1 or OneOver_MutMaxdep_1 or OneOver_Mut_1 or - OneOver_MutMaxrad_2 or OneOver_MutMaxdep_2 or OneOver_Mut_2 or - OneOver_MutMaxrad_3 or OneOver_MutMaxdep_3 or OneOver_Mut_3 or - OneOver_MutMaxrad_4 or OneOver_MutMaxdep_4 or OneOver_Mut_4 or - OneOver_MutMaxrad_5 or OneOver_MutMaxdep_5 or OneOver_Mut_5) +always @(*) begin case(layer_moverMux) 3'b000: @@ -2728,8 +2616,7 @@ endcase end // Determine move value -always @(sleftz_moverMux or log_rand_num or OneOver_MutMaxrad or OneOver_MutMaxdep or sleftr_moverMux or - OneOver_Mut) +always @(*) begin // Resource sharing for multipliers if(sleftz_moverMux == 32'b0) @@ -2749,7 +2636,7 @@ begin end // Determine move value -always @(sleftz_moverMux or c_r_op0 or c_r_op1 or c_z_op0 or c_z_op1 or sleftr_moverMux) +always @(*) begin c_sr_big = c_r_op0 * c_r_op1; c_sz_big = c_z_op0 * c_z_op1; @@ -5538,12 +5425,7 @@ mult_signed_32_bc mult_u3( .result(sr_big)); // multiplexor to find z1 and z0 -always @(c_layer__0 or z1_0 or z0_0 or mut_0 or - z1_1 or z0_1 or mut_1 or - z1_2 or z0_2 or mut_2 or - z1_3 or z0_3 or mut_3 or - z1_4 or z0_4 or mut_4 or - z1_5 or z0_5 or mut_5) +always @(*) begin case(c_layer__0) 3'b000: @@ -5593,7 +5475,7 @@ end // May have to change block staments on this one for odin // set numerator -always @(c_uz__0 or c_z1__0 or c_z__0 or c_z0__0) +always @(*) begin //c_numer__0 = 63'b0; if(c_uz__0[31] == 1'b0) @@ -5613,10 +5495,7 @@ begin end // initialize uninitialized data in pipeline -always @(x_mover or y_mover or z_mover or - ux_mover or uy_mover or uz_mover or - sz_mover or sr_mover or sleftz_mover or sleftr_mover or - weight_mover or layer_mover or dead_mover) +always @(*) begin c_x__0 = x_mover; c_y__0 = y_mover; @@ -5637,187 +5516,7 @@ begin end // Determine new (x,y,z) coordinates -always @(r_x__0 or r_y__0 or r_z__0 or r_ux__0 or r_uy__0 or r_uz__0 or r_sz__0 or r_sr__0 or r_sleftz__0 or r_sleftr__0 or - r_weight__0 or r_layer__0 or r_dead__0 or r_hit__0 or r_diff__0 or r_dl_b__0 or r_numer__0 or r_z1__0 or r_z0__0 or r_mut__0 or - - r_x__1 or r_y__1 or r_z__1 or r_ux__1 or r_uy__1 or r_uz__1 or r_sz__1 or r_sr__1 or r_sleftz__1 or r_sleftr__1 or - r_weight__1 or r_layer__1 or r_dead__1 or r_hit__1 or r_diff__1 or r_dl_b__1 or r_numer__1 or r_z1__1 or r_z0__1 or r_mut__1 or - - r_x__2 or r_y__2 or r_z__2 or r_ux__2 or r_uy__2 or r_uz__2 or r_sz__2 or r_sr__2 or r_sleftz__2 or r_sleftr__2 or - r_weight__2 or r_layer__2 or r_dead__2 or r_hit__2 or r_diff__2 or r_dl_b__2 or r_numer__2 or r_z1__2 or r_z0__2 or r_mut__2 or - - r_x__3 or r_y__3 or r_z__3 or r_ux__3 or r_uy__3 or r_uz__3 or r_sz__3 or r_sr__3 or r_sleftz__3 or r_sleftr__3 or - r_weight__3 or r_layer__3 or r_dead__3 or r_hit__3 or r_diff__3 or r_dl_b__3 or r_numer__3 or r_z1__3 or r_z0__3 or r_mut__3 or - - r_x__4 or r_y__4 or r_z__4 or r_ux__4 or r_uy__4 or r_uz__4 or r_sz__4 or r_sr__4 or r_sleftz__4 or r_sleftr__4 or - r_weight__4 or r_layer__4 or r_dead__4 or r_hit__4 or r_diff__4 or r_dl_b__4 or r_numer__4 or r_z1__4 or r_z0__4 or r_mut__4 or - - r_x__5 or r_y__5 or r_z__5 or r_ux__5 or r_uy__5 or r_uz__5 or r_sz__5 or r_sr__5 or r_sleftz__5 or r_sleftr__5 or - r_weight__5 or r_layer__5 or r_dead__5 or r_hit__5 or r_diff__5 or r_dl_b__5 or r_numer__5 or r_z1__5 or r_z0__5 or r_mut__5 or - - r_x__6 or r_y__6 or r_z__6 or r_ux__6 or r_uy__6 or r_uz__6 or r_sz__6 or r_sr__6 or r_sleftz__6 or r_sleftr__6 or - r_weight__6 or r_layer__6 or r_dead__6 or r_hit__6 or r_diff__6 or r_dl_b__6 or r_numer__6 or r_z1__6 or r_z0__6 or r_mut__6 or - - r_x__7 or r_y__7 or r_z__7 or r_ux__7 or r_uy__7 or r_uz__7 or r_sz__7 or r_sr__7 or r_sleftz__7 or r_sleftr__7 or - r_weight__7 or r_layer__7 or r_dead__7 or r_hit__7 or r_diff__7 or r_dl_b__7 or r_numer__7 or r_z1__7 or r_z0__7 or r_mut__7 or - - r_x__8 or r_y__8 or r_z__8 or r_ux__8 or r_uy__8 or r_uz__8 or r_sz__8 or r_sr__8 or r_sleftz__8 or r_sleftr__8 or - r_weight__8 or r_layer__8 or r_dead__8 or r_hit__8 or r_diff__8 or r_dl_b__8 or r_numer__8 or r_z1__8 or r_z0__8 or r_mut__8 or - - r_x__9 or r_y__9 or r_z__9 or r_ux__9 or r_uy__9 or r_uz__9 or r_sz__9 or r_sr__9 or r_sleftz__9 or r_sleftr__9 or - r_weight__9 or r_layer__9 or r_dead__9 or r_hit__9 or r_diff__9 or r_dl_b__9 or r_numer__9 or r_z1__9 or r_z0__9 or r_mut__9 or - - r_x__10 or r_y__10 or r_z__10 or r_ux__10 or r_uy__10 or r_uz__10 or r_sz__10 or r_sr__10 or r_sleftz__10 or r_sleftr__10 or - r_weight__10 or r_layer__10 or r_dead__10 or r_hit__10 or r_diff__10 or r_dl_b__10 or r_numer__10 or r_z1__10 or r_z0__10 or r_mut__10 or - - r_x__11 or r_y__11 or r_z__11 or r_ux__11 or r_uy__11 or r_uz__11 or r_sz__11 or r_sr__11 or r_sleftz__11 or r_sleftr__11 or - r_weight__11 or r_layer__11 or r_dead__11 or r_hit__11 or r_diff__11 or r_dl_b__11 or r_numer__11 or r_z1__11 or r_z0__11 or r_mut__11 or - - r_x__12 or r_y__12 or r_z__12 or r_ux__12 or r_uy__12 or r_uz__12 or r_sz__12 or r_sr__12 or r_sleftz__12 or r_sleftr__12 or - r_weight__12 or r_layer__12 or r_dead__12 or r_hit__12 or r_diff__12 or r_dl_b__12 or r_numer__12 or r_z1__12 or r_z0__12 or r_mut__12 or - - r_x__13 or r_y__13 or r_z__13 or r_ux__13 or r_uy__13 or r_uz__13 or r_sz__13 or r_sr__13 or r_sleftz__13 or r_sleftr__13 or - r_weight__13 or r_layer__13 or r_dead__13 or r_hit__13 or r_diff__13 or r_dl_b__13 or r_numer__13 or r_z1__13 or r_z0__13 or r_mut__13 or - - r_x__14 or r_y__14 or r_z__14 or r_ux__14 or r_uy__14 or r_uz__14 or r_sz__14 or r_sr__14 or r_sleftz__14 or r_sleftr__14 or - r_weight__14 or r_layer__14 or r_dead__14 or r_hit__14 or r_diff__14 or r_dl_b__14 or r_numer__14 or r_z1__14 or r_z0__14 or r_mut__14 or - - r_x__15 or r_y__15 or r_z__15 or r_ux__15 or r_uy__15 or r_uz__15 or r_sz__15 or r_sr__15 or r_sleftz__15 or r_sleftr__15 or - r_weight__15 or r_layer__15 or r_dead__15 or r_hit__15 or r_diff__15 or r_dl_b__15 or r_numer__15 or r_z1__15 or r_z0__15 or r_mut__15 or - - r_x__16 or r_y__16 or r_z__16 or r_ux__16 or r_uy__16 or r_uz__16 or r_sz__16 or r_sr__16 or r_sleftz__16 or r_sleftr__16 or - r_weight__16 or r_layer__16 or r_dead__16 or r_hit__16 or r_diff__16 or r_dl_b__16 or r_numer__16 or r_z1__16 or r_z0__16 or r_mut__16 or - - r_x__17 or r_y__17 or r_z__17 or r_ux__17 or r_uy__17 or r_uz__17 or r_sz__17 or r_sr__17 or r_sleftz__17 or r_sleftr__17 or - r_weight__17 or r_layer__17 or r_dead__17 or r_hit__17 or r_diff__17 or r_dl_b__17 or r_numer__17 or r_z1__17 or r_z0__17 or r_mut__17 or - - r_x__18 or r_y__18 or r_z__18 or r_ux__18 or r_uy__18 or r_uz__18 or r_sz__18 or r_sr__18 or r_sleftz__18 or r_sleftr__18 or - r_weight__18 or r_layer__18 or r_dead__18 or r_hit__18 or r_diff__18 or r_dl_b__18 or r_numer__18 or r_z1__18 or r_z0__18 or r_mut__18 or - - r_x__19 or r_y__19 or r_z__19 or r_ux__19 or r_uy__19 or r_uz__19 or r_sz__19 or r_sr__19 or r_sleftz__19 or r_sleftr__19 or - r_weight__19 or r_layer__19 or r_dead__19 or r_hit__19 or r_diff__19 or r_dl_b__19 or r_numer__19 or r_z1__19 or r_z0__19 or r_mut__19 or - - r_x__20 or r_y__20 or r_z__20 or r_ux__20 or r_uy__20 or r_uz__20 or r_sz__20 or r_sr__20 or r_sleftz__20 or r_sleftr__20 or - r_weight__20 or r_layer__20 or r_dead__20 or r_hit__20 or r_diff__20 or r_dl_b__20 or r_numer__20 or r_z1__20 or r_z0__20 or r_mut__20 or - - r_x__21 or r_y__21 or r_z__21 or r_ux__21 or r_uy__21 or r_uz__21 or r_sz__21 or r_sr__21 or r_sleftz__21 or r_sleftr__21 or - r_weight__21 or r_layer__21 or r_dead__21 or r_hit__21 or r_diff__21 or r_dl_b__21 or r_numer__21 or r_z1__21 or r_z0__21 or r_mut__21 or - - r_x__22 or r_y__22 or r_z__22 or r_ux__22 or r_uy__22 or r_uz__22 or r_sz__22 or r_sr__22 or r_sleftz__22 or r_sleftr__22 or - r_weight__22 or r_layer__22 or r_dead__22 or r_hit__22 or r_diff__22 or r_dl_b__22 or r_numer__22 or r_z1__22 or r_z0__22 or r_mut__22 or - - r_x__23 or r_y__23 or r_z__23 or r_ux__23 or r_uy__23 or r_uz__23 or r_sz__23 or r_sr__23 or r_sleftz__23 or r_sleftr__23 or - r_weight__23 or r_layer__23 or r_dead__23 or r_hit__23 or r_diff__23 or r_dl_b__23 or r_numer__23 or r_z1__23 or r_z0__23 or r_mut__23 or - - r_x__24 or r_y__24 or r_z__24 or r_ux__24 or r_uy__24 or r_uz__24 or r_sz__24 or r_sr__24 or r_sleftz__24 or r_sleftr__24 or - r_weight__24 or r_layer__24 or r_dead__24 or r_hit__24 or r_diff__24 or r_dl_b__24 or r_numer__24 or r_z1__24 or r_z0__24 or r_mut__24 or - - r_x__25 or r_y__25 or r_z__25 or r_ux__25 or r_uy__25 or r_uz__25 or r_sz__25 or r_sr__25 or r_sleftz__25 or r_sleftr__25 or - r_weight__25 or r_layer__25 or r_dead__25 or r_hit__25 or r_diff__25 or r_dl_b__25 or r_numer__25 or r_z1__25 or r_z0__25 or r_mut__25 or - - r_x__26 or r_y__26 or r_z__26 or r_ux__26 or r_uy__26 or r_uz__26 or r_sz__26 or r_sr__26 or r_sleftz__26 or r_sleftr__26 or - r_weight__26 or r_layer__26 or r_dead__26 or r_hit__26 or r_diff__26 or r_dl_b__26 or r_numer__26 or r_z1__26 or r_z0__26 or r_mut__26 or - - r_x__27 or r_y__27 or r_z__27 or r_ux__27 or r_uy__27 or r_uz__27 or r_sz__27 or r_sr__27 or r_sleftz__27 or r_sleftr__27 or - r_weight__27 or r_layer__27 or r_dead__27 or r_hit__27 or r_diff__27 or r_dl_b__27 or r_numer__27 or r_z1__27 or r_z0__27 or r_mut__27 or - - r_x__28 or r_y__28 or r_z__28 or r_ux__28 or r_uy__28 or r_uz__28 or r_sz__28 or r_sr__28 or r_sleftz__28 or r_sleftr__28 or - r_weight__28 or r_layer__28 or r_dead__28 or r_hit__28 or r_diff__28 or r_dl_b__28 or r_numer__28 or r_z1__28 or r_z0__28 or r_mut__28 or - - r_x__29 or r_y__29 or r_z__29 or r_ux__29 or r_uy__29 or r_uz__29 or r_sz__29 or r_sr__29 or r_sleftz__29 or r_sleftr__29 or - r_weight__29 or r_layer__29 or r_dead__29 or r_hit__29 or r_diff__29 or r_dl_b__29 or r_numer__29 or r_z1__29 or r_z0__29 or r_mut__29 or - - r_x__30 or r_y__30 or r_z__30 or r_ux__30 or r_uy__30 or r_uz__30 or r_sz__30 or r_sr__30 or r_sleftz__30 or r_sleftr__30 or - r_weight__30 or r_layer__30 or r_dead__30 or r_hit__30 or r_diff__30 or r_dl_b__30 or r_numer__30 or r_z1__30 or r_z0__30 or r_mut__30 or - - r_x__31 or r_y__31 or r_z__31 or r_ux__31 or r_uy__31 or r_uz__31 or r_sz__31 or r_sr__31 or r_sleftz__31 or r_sleftr__31 or - r_weight__31 or r_layer__31 or r_dead__31 or r_hit__31 or r_diff__31 or r_dl_b__31 or r_numer__31 or r_z1__31 or r_z0__31 or r_mut__31 or - - r_x__32 or r_y__32 or r_z__32 or r_ux__32 or r_uy__32 or r_uz__32 or r_sz__32 or r_sr__32 or r_sleftz__32 or r_sleftr__32 or - r_weight__32 or r_layer__32 or r_dead__32 or r_hit__32 or r_diff__32 or r_dl_b__32 or r_numer__32 or r_z1__32 or r_z0__32 or r_mut__32 or - - r_x__33 or r_y__33 or r_z__33 or r_ux__33 or r_uy__33 or r_uz__33 or r_sz__33 or r_sr__33 or r_sleftz__33 or r_sleftr__33 or - r_weight__33 or r_layer__33 or r_dead__33 or r_hit__33 or r_diff__33 or r_dl_b__33 or r_numer__33 or r_z1__33 or r_z0__33 or r_mut__33 or - - r_x__34 or r_y__34 or r_z__34 or r_ux__34 or r_uy__34 or r_uz__34 or r_sz__34 or r_sr__34 or r_sleftz__34 or r_sleftr__34 or - r_weight__34 or r_layer__34 or r_dead__34 or r_hit__34 or r_diff__34 or r_dl_b__34 or r_numer__34 or r_z1__34 or r_z0__34 or r_mut__34 or - - r_x__35 or r_y__35 or r_z__35 or r_ux__35 or r_uy__35 or r_uz__35 or r_sz__35 or r_sr__35 or r_sleftz__35 or r_sleftr__35 or - r_weight__35 or r_layer__35 or r_dead__35 or r_hit__35 or r_diff__35 or r_dl_b__35 or r_numer__35 or r_z1__35 or r_z0__35 or r_mut__35 or - - r_x__36 or r_y__36 or r_z__36 or r_ux__36 or r_uy__36 or r_uz__36 or r_sz__36 or r_sr__36 or r_sleftz__36 or r_sleftr__36 or - r_weight__36 or r_layer__36 or r_dead__36 or r_hit__36 or r_diff__36 or r_dl_b__36 or r_numer__36 or r_z1__36 or r_z0__36 or r_mut__36 or - - r_x__37 or r_y__37 or r_z__37 or r_ux__37 or r_uy__37 or r_uz__37 or r_sz__37 or r_sr__37 or r_sleftz__37 or r_sleftr__37 or - r_weight__37 or r_layer__37 or r_dead__37 or r_hit__37 or r_diff__37 or r_dl_b__37 or r_numer__37 or r_z1__37 or r_z0__37 or r_mut__37 or - - r_x__38 or r_y__38 or r_z__38 or r_ux__38 or r_uy__38 or r_uz__38 or r_sz__38 or r_sr__38 or r_sleftz__38 or r_sleftr__38 or - r_weight__38 or r_layer__38 or r_dead__38 or r_hit__38 or r_diff__38 or r_dl_b__38 or r_numer__38 or r_z1__38 or r_z0__38 or r_mut__38 or - - r_x__39 or r_y__39 or r_z__39 or r_ux__39 or r_uy__39 or r_uz__39 or r_sz__39 or r_sr__39 or r_sleftz__39 or r_sleftr__39 or - r_weight__39 or r_layer__39 or r_dead__39 or r_hit__39 or r_diff__39 or r_dl_b__39 or r_numer__39 or r_z1__39 or r_z0__39 or r_mut__39 or - - r_x__40 or r_y__40 or r_z__40 or r_ux__40 or r_uy__40 or r_uz__40 or r_sz__40 or r_sr__40 or r_sleftz__40 or r_sleftr__40 or - r_weight__40 or r_layer__40 or r_dead__40 or r_hit__40 or r_diff__40 or r_dl_b__40 or r_numer__40 or r_z1__40 or r_z0__40 or r_mut__40 or - - r_x__41 or r_y__41 or r_z__41 or r_ux__41 or r_uy__41 or r_uz__41 or r_sz__41 or r_sr__41 or r_sleftz__41 or r_sleftr__41 or - r_weight__41 or r_layer__41 or r_dead__41 or r_hit__41 or r_diff__41 or r_dl_b__41 or r_numer__41 or r_z1__41 or r_z0__41 or r_mut__41 or - - r_x__42 or r_y__42 or r_z__42 or r_ux__42 or r_uy__42 or r_uz__42 or r_sz__42 or r_sr__42 or r_sleftz__42 or r_sleftr__42 or - r_weight__42 or r_layer__42 or r_dead__42 or r_hit__42 or r_diff__42 or r_dl_b__42 or r_numer__42 or r_z1__42 or r_z0__42 or r_mut__42 or - - r_x__43 or r_y__43 or r_z__43 or r_ux__43 or r_uy__43 or r_uz__43 or r_sz__43 or r_sr__43 or r_sleftz__43 or r_sleftr__43 or - r_weight__43 or r_layer__43 or r_dead__43 or r_hit__43 or r_diff__43 or r_dl_b__43 or r_numer__43 or r_z1__43 or r_z0__43 or r_mut__43 or - - r_x__44 or r_y__44 or r_z__44 or r_ux__44 or r_uy__44 or r_uz__44 or r_sz__44 or r_sr__44 or r_sleftz__44 or r_sleftr__44 or - r_weight__44 or r_layer__44 or r_dead__44 or r_hit__44 or r_diff__44 or r_dl_b__44 or r_numer__44 or r_z1__44 or r_z0__44 or r_mut__44 or - - r_x__45 or r_y__45 or r_z__45 or r_ux__45 or r_uy__45 or r_uz__45 or r_sz__45 or r_sr__45 or r_sleftz__45 or r_sleftr__45 or - r_weight__45 or r_layer__45 or r_dead__45 or r_hit__45 or r_diff__45 or r_dl_b__45 or r_numer__45 or r_z1__45 or r_z0__45 or r_mut__45 or - - r_x__46 or r_y__46 or r_z__46 or r_ux__46 or r_uy__46 or r_uz__46 or r_sz__46 or r_sr__46 or r_sleftz__46 or r_sleftr__46 or - r_weight__46 or r_layer__46 or r_dead__46 or r_hit__46 or r_diff__46 or r_dl_b__46 or r_numer__46 or r_z1__46 or r_z0__46 or r_mut__46 or - - r_x__47 or r_y__47 or r_z__47 or r_ux__47 or r_uy__47 or r_uz__47 or r_sz__47 or r_sr__47 or r_sleftz__47 or r_sleftr__47 or - r_weight__47 or r_layer__47 or r_dead__47 or r_hit__47 or r_diff__47 or r_dl_b__47 or r_numer__47 or r_z1__47 or r_z0__47 or r_mut__47 or - - r_x__48 or r_y__48 or r_z__48 or r_ux__48 or r_uy__48 or r_uz__48 or r_sz__48 or r_sr__48 or r_sleftz__48 or r_sleftr__48 or - r_weight__48 or r_layer__48 or r_dead__48 or r_hit__48 or r_diff__48 or r_dl_b__48 or r_numer__48 or r_z1__48 or r_z0__48 or r_mut__48 or - - r_x__49 or r_y__49 or r_z__49 or r_ux__49 or r_uy__49 or r_uz__49 or r_sz__49 or r_sr__49 or r_sleftz__49 or r_sleftr__49 or - r_weight__49 or r_layer__49 or r_dead__49 or r_hit__49 or r_diff__49 or r_dl_b__49 or r_numer__49 or r_z1__49 or r_z0__49 or r_mut__49 or - - r_x__50 or r_y__50 or r_z__50 or r_ux__50 or r_uy__50 or r_uz__50 or r_sz__50 or r_sr__50 or r_sleftz__50 or r_sleftr__50 or - r_weight__50 or r_layer__50 or r_dead__50 or r_hit__50 or r_diff__50 or r_dl_b__50 or r_numer__50 or r_z1__50 or r_z0__50 or r_mut__50 or - - r_x__51 or r_y__51 or r_z__51 or r_ux__51 or r_uy__51 or r_uz__51 or r_sz__51 or r_sr__51 or r_sleftz__51 or r_sleftr__51 or - r_weight__51 or r_layer__51 or r_dead__51 or r_hit__51 or r_diff__51 or r_dl_b__51 or r_numer__51 or r_z1__51 or r_z0__51 or r_mut__51 or - - r_x__52 or r_y__52 or r_z__52 or r_ux__52 or r_uy__52 or r_uz__52 or r_sz__52 or r_sr__52 or r_sleftz__52 or r_sleftr__52 or - r_weight__52 or r_layer__52 or r_dead__52 or r_hit__52 or r_diff__52 or r_dl_b__52 or r_numer__52 or r_z1__52 or r_z0__52 or r_mut__52 or - - r_x__53 or r_y__53 or r_z__53 or r_ux__53 or r_uy__53 or r_uz__53 or r_sz__53 or r_sr__53 or r_sleftz__53 or r_sleftr__53 or - r_weight__53 or r_layer__53 or r_dead__53 or r_hit__53 or r_diff__53 or r_dl_b__53 or r_numer__53 or r_z1__53 or r_z0__53 or r_mut__53 or - - r_x__54 or r_y__54 or r_z__54 or r_ux__54 or r_uy__54 or r_uz__54 or r_sz__54 or r_sr__54 or r_sleftz__54 or r_sleftr__54 or - r_weight__54 or r_layer__54 or r_dead__54 or r_hit__54 or r_diff__54 or r_dl_b__54 or r_numer__54 or r_z1__54 or r_z0__54 or r_mut__54 or - - r_x__55 or r_y__55 or r_z__55 or r_ux__55 or r_uy__55 or r_uz__55 or r_sz__55 or r_sr__55 or r_sleftz__55 or r_sleftr__55 or - r_weight__55 or r_layer__55 or r_dead__55 or r_hit__55 or r_diff__55 or r_dl_b__55 or r_numer__55 or r_z1__55 or r_z0__55 or r_mut__55 or - - r_x__56 or r_y__56 or r_z__56 or r_ux__56 or r_uy__56 or r_uz__56 or r_sz__56 or r_sr__56 or r_sleftz__56 or r_sleftr__56 or - r_weight__56 or r_layer__56 or r_dead__56 or r_hit__56 or r_diff__56 or r_dl_b__56 or r_numer__56 or r_z1__56 or r_z0__56 or r_mut__56 or - - r_x__57 or r_y__57 or r_z__57 or r_ux__57 or r_uy__57 or r_uz__57 or r_sz__57 or r_sr__57 or r_sleftz__57 or r_sleftr__57 or - r_weight__57 or r_layer__57 or r_dead__57 or r_hit__57 or r_diff__57 or r_dl_b__57 or r_numer__57 or r_z1__57 or r_z0__57 or r_mut__57 or - - r_x__58 or r_y__58 or r_z__58 or r_ux__58 or r_uy__58 or r_uz__58 or r_sz__58 or r_sr__58 or r_sleftz__58 or r_sleftr__58 or - r_weight__58 or r_layer__58 or r_dead__58 or r_hit__58 or r_diff__58 or r_dl_b__58 or r_numer__58 or r_z1__58 or r_z0__58 or r_mut__58 or - - r_x__59 or r_y__59 or r_z__59 or r_ux__59 or r_uy__59 or r_uz__59 or r_sz__59 or r_sr__59 or r_sleftz__59 or r_sleftr__59 or - r_weight__59 or r_layer__59 or r_dead__59 or r_hit__59 or r_diff__59 or r_dl_b__59 or r_numer__59 or r_z1__59 or r_z0__59 or r_mut__59 or - - sr_big or sleftz_big or sleftr_big or quotient_div1) +always @(*) // default // setup standard pipeline @@ -10019,12 +9718,7 @@ mult_signed_32 u2(sr_boundaryChecker, uy_boundaryChecker, c_ymult_big); mult_signed_32 u3(sz_boundaryChecker, uz_boundaryChecker, c_zmult_big); // Determine new (x,y,z) coordinates -always @(c_dead or - c_x_big or c_y_big or c_z_big or - c_x or c_y or c_z or - x_boundaryChecker or y_boundaryChecker or z_boundaryChecker or - c_xmult_big or c_ymult_big or c_zmult_big - or hit_boundaryChecker or dead_boundaryChecker) +always @(*) begin c_x_big = x_boundaryChecker + c_xmult_big[2*`BIT_WIDTH-2:31]; @@ -10169,7 +9863,7 @@ module mult_signed_32(a, b, c); reg [63:0]c_tmp; -always@(a or b or is_neg_a or is_neg_b or a_tmp or b_tmp or c) +always@(*) begin if(a[31] == 1) begin @@ -10198,7 +9892,7 @@ begin end end -always@(c_tmp) +always@(*) begin c = c_tmp; end @@ -10285,7 +9979,7 @@ reg [`LAYER_WIDTH-1:0]layer_Roulette; reg [`BIT_WIDTH-1:0] weight_Roulette; reg dead_Roulette; -always @ (reset or enable or weight_absorber or randBits or randnumber or dead_RouletteMux) begin +always @ (*) begin //Default case moved inside else statements for odin //randBits = randnumber; //Reading from external random num generator //weight_roulette=weight_absorber; //Avoid inferring a latch @@ -10393,7 +10087,7 @@ reg [31:0] r_s1, r_s2, r_s3; assign number_o = r_s1 ^ r_s2 ^ r_s3; -always @(loadseed_i or seed_i or r_s1 or r_s2 or r_s3) +always @(*) begin if(loadseed_i) begin @@ -10486,7 +10180,7 @@ sram_replace0 (.clk (clock), .addr (c_shifted_x), .data (blank), .we (1'b0), .ou //end // Priority encoder, loop expanded -always @(in_x) +always @(*) begin if (in_x[31]) begin c_indexFirstOne = 6'b011111; @@ -10595,7 +10289,7 @@ end wire [5:0]shifted; assign shifted = c_indexFirstOne - `MANTISSA_PRECISION + 1; -always@(c_indexFirstOne or in_x or shifted) +always@(*) begin // c_temp_shift_x = in_x >> (c_indexFirstOne - `MANTISSA_PRECISION + 1); if(c_indexFirstOne >= `MANTISSA_PRECISION) @@ -10679,7 +10373,7 @@ begin end // calculate log -always@(r_indexFirstOne or mantissa) +always@(*) begin if(r_indexFirstOne >= `MANTISSA_PRECISION) begin @@ -13106,8 +12800,7 @@ ScattererReflectorWrapper scattererReflector( //// or the reflector should be used in any clock cycle //// ////////////////////////////////////////////////////////////////////// -always @ (hit__37 or ux_scatterer or uy_scatterer or uz_scatterer or layer__37 or dead__37 or - ux_reflector or uy_reflector or uz_reflector or layer_reflector or dead_reflector) begin +always @ (*) begin case (hit__37) 0: begin o_ux = ux_scatterer; @@ -14840,7 +14533,7 @@ PhotonBlock1 photon1q( ////////////////////////////////////////////////////////////////////////////// ///////////////STAGE 2 - square of x and y///////////////////////// -always @(reset or x_pipe or y_pipe) begin +always @(*) begin if (reset) begin x2_temp=0; y2_temp=0; @@ -14852,7 +14545,7 @@ always @(reset or x_pipe or y_pipe) begin end ///////////////STAGE 3 - square of r///////////////////////// -always @(reset or x2_P or y2_P) begin +always @(*) begin if (reset) r2_temp=0; else @@ -14861,7 +14554,7 @@ end ///////////////STAGE 4 - Find r and dwa///////////////////////// //Create MUX -always@(layer_pipe or muaFraction1 or muaFraction2 or muaFraction3 or muaFraction4 or muaFraction5) +always@(*) case(layer_pipe) 1: fractionScaled=muaFraction1; 2: fractionScaled=muaFraction2; @@ -14872,7 +14565,7 @@ always@(layer_pipe or muaFraction1 or muaFraction2 or muaFraction3 or muaFractio endcase -always @(reset or weight__4 or r_P_wire or weight_P4 or fractionScaled or product64bit or dead__4 or hit__4) begin +always @(*) begin if (reset) begin weight_P4=0; r_P=0; @@ -14903,7 +14596,7 @@ Sqrt_64b squareRoot ( ); ///////////////STAGE 14 - Find ir and iz///////////////////////// -always @(reset or r_P or z_pipe or dead__14 or hit__14 or iz_temp or ir_temp) begin +always @(*) begin if (reset) begin ir_temp=0; iz_temp=0; @@ -14951,7 +14644,7 @@ always @(reset or r_P or z_pipe or dead__14 or hit__14 or iz_temp or ir_temp) be end ///////////////STAGE 15 - Compute MEM address///////////////////////// -always @(reset or ir__15 or iz__15 or ir_P or iz_P or ir_scaled) begin +always @(*) begin if (reset) begin ir_P=0; iz_P=0; @@ -14967,7 +14660,7 @@ always @(reset or ir__15 or iz__15 or ir_P or iz_P or ir_scaled) begin end ///////////////STAGE 16 - MEM read///////////////////////// -always @(reset or ir__16 or ir__17 or iz__16 or iz__17 or ir__18 or iz__18 or newAbs_P or q or newAbs_temp) begin +always @(*) begin if (reset) begin oldAbs_MEM=0; end else begin @@ -14985,7 +14678,7 @@ end ///////////////STAGE 17 - Update Weight///////////////////////// //TO BE TESTED!!! -always @(reset or dwa__17 or weight__17 or weight_P or dwa_P or oldAbs_P) begin +always @(*) begin if(reset) begin dwa_P=0; //How to specify Base 10??? weight_P=0; @@ -15629,7 +15322,7 @@ assign reset_new = reset & bigOr; //MUX for sending in indices for memory. -always @ (i_layer31_pipeWrapper) begin +always @ (*) begin case (i_layer31_pipeWrapper) 3'b001: layerMinusOne = 0; 3'b010: layerMinusOne = 1; @@ -17924,11 +17617,7 @@ end //are placed on the appropriate wires for placement in the pipeline. //-------------MUXES for SYNCHRONOUS LOGIC-------- -always @ (i_layer36 or downCritAngle_0 or upCritAngle_0 or - downCritAngle_1 or upCritAngle_1 or - downCritAngle_2 or upCritAngle_2 or - downCritAngle_3 or upCritAngle_3 or - downCritAngle_4 or upCritAngle_4) begin +always @ (*) begin case (i_layer36) 1:begin downCritAngle = downCritAngle_0; @@ -17958,7 +17647,7 @@ always @ (i_layer36 or downCritAngle_0 or upCritAngle_0 or endcase end -always @ (i_uz35 or i_layer35) begin +always @ (*) begin negUz = -i_uz35; case (i_uz35[31]) 0: begin @@ -18009,11 +17698,7 @@ assign op1_2_2 = i_uz1; //SUBTRACTION, see math results //CC 4 -always @ (i_uz3 or i_layer3 or down_niOverNt_2_1 or up_niOverNt_2_1 or - down_niOverNt_2_2 or up_niOverNt_2_2 or - down_niOverNt_2_3 or up_niOverNt_2_3 or - down_niOverNt_2_4 or up_niOverNt_2_4 or - down_niOverNt_2_5 or up_niOverNt_2_5) begin +always @ (*) begin case (i_uz3[31]) //uz >= 0 0:begin @@ -18051,11 +17736,7 @@ assign sqrtOperand1_6 = uz2_2__5; //CC `SQRT+`DIV+6 -- Line up with Scatterer. assign op1_36_1 = i_ux35; -always @ (i_uz35 or i_layer35 or down_niOverNt_1 or up_niOverNt_1 or - down_niOverNt_2 or up_niOverNt_2 or - down_niOverNt_3 or up_niOverNt_3 or - down_niOverNt_4 or up_niOverNt_4 or - down_niOverNt_5 or up_niOverNt_5) begin +always @ (*) begin case (i_uz35[31]) 0: begin//uz >= 0 case (i_layer35) @@ -18199,8 +17880,7 @@ assign overflow2_36 = ~prod2_36[63] & toAnd2_36_1; //and U9(negOverflow2_36, prod2_36[63], toAnd2_36_2); assign negOverflow2_36 = prod2_36[63] & toAnd2_36_2; -always @ (overflow1_36 or negOverflow1_36 or prod1_36 or - overflow2_36 or negOverflow2_36 or prod2_36) begin +always @ (*) begin case ({overflow1_36, negOverflow1_36}) 0: new_ux_transmitted = {prod1_36[63:63], prod1_36[59:29]}; 1: new_ux_transmitted = `INTMIN; @@ -18235,9 +17915,7 @@ end // // // -always @ (i_uz36 or downCritAngle or upCritAngle or down_rFresnel or i_ux36 or - i_uy36 or i_layer36 or i_dead36 or rnd or up_rFresnel or ux_transmitted__37 or - uy_transmitted__37 or uz2__37) begin +always @ (*) begin //REFLECTED -- Due to total internal reflection while moving down if (~i_uz36[31] && i_uz36 <= downCritAngle) begin new_ux = i_ux36; @@ -22932,7 +22610,7 @@ add_32b uyNumer_add( assign new_sqrtOneMinusUz2_inv = (div_overflow) ? `INTMAX : {quot1_16[63:63], quot1_16[46:16]}; //CC `SQRT+`DIV+6 -always @ (overflow1_36 or negOverflow1_36 or prod1_36 or overflow2_36 or negOverflow2_36 or prod2_36) begin +always @ (*) begin case ({overflow1_36, negOverflow1_36}) 0: new_uxQuotient = {prod1_36[63:63], prod1_36[45:15]}; 1: new_uxQuotient = `INTMIN; @@ -22985,7 +22663,7 @@ assign new_uzCost = prod6_36; //Determine whether or not the photon calculation was done on a photon that //was normal (orthogonal) to the plane of interest. This is to avoid divide //by zero errors -always @ (i_uz36) begin +always @ (*) begin //If uz >= `INTMAX-3 || uz <= -`INTMAX+3, normal incident if(i_uz36 == 32'h7FFFFFFF || i_uz36 == 32'h7FFFFFFE || i_uz36 == 32'h7FFFFFFD || i_uz36 == 32'h7FFFFFFC || i_uz36 == 32'h80000000 || i_uz36 == 32'h80000001 || i_uz36 == 32'h80000002 || i_uz36 == 32'h80000003 || i_uz36 == 32'h80000004) begin normalIncident = 1'b1; @@ -23106,7 +22784,7 @@ module Mult_32b (dataa, datab, result); //now signed version! reg [63:0]mult_tmp; reg [63:0]c_tmp; -always@(a or b or is_neg_a or is_neg_b or a_tmp or b_tmp or c) +always@(*) begin if(a[31] == 1) begin a_tmp = -a; @@ -23136,7 +22814,7 @@ begin end end -always@(c_tmp) +always@(*) begin c = c_tmp; end @@ -23158,7 +22836,7 @@ module Div_64b (clock, denom, numer, quotient, remain); wire [31:0]remain_temp; Div_64b_unsigned div_temp(.clock(clock), .denom_(denom), .numer_(numer), .quotient(quotient_temp), .remain(remain_temp)); - always @ (numer or denom or quotient_temp or remain_temp) begin + always @ (*) begin if ( numer[63]^denom[31] ) begin // only one is negative quotient = -quotient_temp; remain = -remain_temp; @@ -23326,7 +23004,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); reg [31:0]denom19; - always @(numer or denom0) begin + always @(*) begin numer_temp_63 = {31'b0, numer}; //quo0[63] @@ -23363,7 +23041,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom1 <= denom0; end - always @(numer_temp_60_q or denom1 or quo0_q) begin + always @(*) begin quo1_d[63:61] = quo0_q[63:61]; //quo1_d[60] @@ -23399,7 +23077,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom2 <= denom1; end - always @ (numer_temp_57_q or denom2 or quo1_q) begin + always @ (*) begin quo2_d[63:58] = quo1_q[63:58]; //quo2_d[57] @@ -23436,7 +23114,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom3 <= denom2; end - always @ (numer_temp_54_q or denom3 or quo2_q) begin + always @ (*) begin quo3_d[63:55] = quo2_q[63:55]; //quo3_d[54] @@ -23472,7 +23150,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom4 <= denom3; end - always @ (numer_temp_51_q or denom4 or quo3_q) begin + always @ (*) begin quo4_d[63:52] = quo3_q[63:52]; //quo4[51] @@ -23508,7 +23186,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom5 <= denom4; end - always @ (numer_temp_48_q or denom5 or quo4_q) begin + always @ (*) begin quo5_d[63:49] = quo4_q[63:49]; //quo5_d[48] @@ -23544,7 +23222,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom6 <= denom5; end - always @ (numer_temp_45_q or denom6 or quo5_q) begin + always @ (*) begin quo6_d[63:46] = quo5_q[63:46]; //quo6_d[45] @@ -23580,7 +23258,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom7 <= denom6; end - always @ (numer_temp_42_q or denom7 or quo6_q) begin + always @ (*) begin quo7_d[63:43] = quo6_q[63:43]; //quo7_d[42] @@ -23616,7 +23294,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom8 <= denom7; end - always @ (numer_temp_39_q or denom8 or quo7_q) begin + always @ (*) begin quo8_d[63:40] = quo7_q[63:40]; //quo8[39] @@ -23652,7 +23330,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom9 <= denom8; end - always @ (numer_temp_36_q or denom9 or quo8_q) begin + always @ (*) begin quo9_d[63:37] = quo8_q[63:37]; //quo9[36] @@ -23688,7 +23366,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom10 <= denom9; end - always @ (numer_temp_33_q or denom10 or quo9_q) begin + always @ (*) begin quo10_d[63:34] = quo9_q[63:34]; //quo10_d[33] @@ -23724,7 +23402,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom11 <= denom10; end - always @ (numer_temp_30_q or denom11 or quo10_q) begin + always @ (*) begin quo11_d[63:31] = quo10_q[63:31]; //quo11[30] @@ -23760,7 +23438,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom12 <= denom11; end - always @ (numer_temp_27_q or denom12 or quo11_q) begin + always @ (*) begin quo12_d[63:28] = quo11_q[63:28]; //quo12[27] @@ -23804,7 +23482,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom13 <= denom12; end - always @ (numer_temp_23_q or denom13 or quo12_q) begin + always @ (*) begin quo13_d[63:24] = quo12_q[63:24]; //quo13_d[23] @@ -23848,7 +23526,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom14 <= denom13; end - always @ (numer_temp_19_q or denom14 or quo13_q) begin + always @ (*) begin quo14_d[63:20] = quo13_q[63:20]; //quo14_d[19] @@ -23892,7 +23570,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom15 <= denom14; end - always @ (numer_temp_15_q or denom15 or quo14_q) begin + always @ (*) begin quo15_d[63:16] = quo14_q[63:16]; //quo15_d[15] @@ -23936,7 +23614,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom16 <= denom15; end - always @ (numer_temp_11_q or denom16 or quo15_q) begin + always @ (*) begin quo16_d[63:12] = quo15_q[63:12]; //quo16_d[11] @@ -23980,7 +23658,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom17 <= denom16; end - always @ (numer_temp_7_q or denom17 or quo16_q) begin + always @ (*) begin quo17_d[63:8] = quo16_q[63:8]; //quo17_d[7] @@ -24024,7 +23702,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom18 <= denom17; end - always @ (numer_temp_3_q or denom18 or quo17_q) begin + always @ (*) begin quo18_d[63:4] = quo17_q[63:4]; //quo18_d[3] @@ -24052,7 +23730,7 @@ module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); denom19 <= denom18; end - always @ (numer_temp_1_q or denom19 or quo18_q) begin + always @ (*) begin quo19_d[63:2] = quo18_q[63:2]; //quo19_d[1] if (numer_temp_1_q[94:1] >= denom19 ) begin @@ -24213,7 +23891,7 @@ module Sqrt_64b (clk, num_, res); reg [63:0]one; //This is the one that is selected in first expanded loop reg [31:0]one_tmp; - always @ (num) begin + always @ (*) begin //The first for-loop: //all of these will be zero no matter how 'one' is selected. @@ -24354,7 +24032,7 @@ module Sqrt_64b (clk, num_, res); assign res__0 = 64'b0; assign one__0 = one; - always @ (res__0 or op__0 or one__0) begin + always @ (*) begin //i = 0 if (op__0 >= res__0 + one__0) begin @@ -24393,7 +24071,7 @@ module Sqrt_64b (clk, num_, res); one__3_q <= one__3_d; end - always @ (op__3_q or res__3_q or one__3_q) begin + always @ (*) begin //i = 3 if (op__3_q >= res__3_q + one__3_q) begin op__4 = op__3_q - res__3_q - one__3_q; @@ -24441,7 +24119,7 @@ module Sqrt_64b (clk, num_, res); res__7_q <= res__7_d; end - always @ (op__7_q or res__7_q or one__7_q) begin + always @ (*) begin //i = 7 if (op__7_q >= res__7_q + one__7_q) begin op__8 = op__7_q - res__7_q - one__7_q; @@ -24489,7 +24167,7 @@ module Sqrt_64b (clk, num_, res); res__11_q <= res__11_d; end - always @ (op__11_q or res__11_q or one__11_q) begin + always @ (*) begin //i = 11 if (op__11_q >= res__11_q + one__11_q) begin op__12 = op__11_q - res__11_q - one__11_q; @@ -24537,7 +24215,7 @@ module Sqrt_64b (clk, num_, res); res__15_q <= res__15_d; end - always @ (op__15_q or res__15_q or one__15_q) begin + always @ (*) begin //i = 15 if (op__15_q >= res__15_q + one__15_q) begin op__16 = op__15_q - res__15_q - one__15_q; @@ -24575,7 +24253,7 @@ module Sqrt_64b (clk, num_, res); res__18_q <= res__18_d; end - always @ (op__18_q or res__18_q or one__18_q) begin + always @ (*) begin //i = 18 if (op__18_q >= res__18_q + one__18_q) begin op__19 = op__18_q - res__18_q - one__18_q; @@ -24613,7 +24291,7 @@ module Sqrt_64b (clk, num_, res); res__21_q <= res__21_d; end - always @ (op__21_q or res__21_q or one__21_q) begin + always @ (*) begin //i = 21 if (op__21_q >= res__21_q + one__21_q) begin op__22 = op__21_q - res__21_q - one__21_q; @@ -24651,7 +24329,7 @@ module Sqrt_64b (clk, num_, res); res__24_q <= res__24_d; end - always @ (op__24_q or res__24_q or one__24_q) begin + always @ (*) begin //i = 24 if (op__24_q >= res__24_q + one__24_q) begin op__25 = op__24_q - res__24_q - one__24_q; @@ -24689,7 +24367,7 @@ module Sqrt_64b (clk, num_, res); res__27_q <= res__27_d; end - always @ (op__27_q or res__27_q or one__27_q) begin + always @ (*) begin //i = 27 if (op__27_q >= res__27_q + one__27_q) begin op__28 = op__27_q - res__27_q - one__27_q; diff --git a/vtr_flow/benchmarks/verilog/mkDelayWorker32B.v b/vtr_flow/benchmarks/verilog/mkDelayWorker32B.v index 7fd0a06d4db..b20a866394f 100644 --- a/vtr_flow/benchmarks/verilog/mkDelayWorker32B.v +++ b/vtr_flow/benchmarks/verilog/mkDelayWorker32B.v @@ -2190,10 +2190,7 @@ wire [255:0] dp_out_not_used2; assign MUX_wmemi_reqF_x_wire__wset_1__VAL_1 = { 4'b0101, addr__h20994, 12'b01 } ; assign MUX_wmemi_reqF_x_wire__wset_1__VAL_2 = { 4'b0011, addr__h21166, 12'b01 } ; assign MUX_wci_respF_x_wire__wset_1__VAL_1 = { 2'b01, x_data__h21804 } ; - always@(WILL_FIRE_RL_wci_cfrd or - MUX_wci_respF_x_wire__wset_1__VAL_1 or - WILL_FIRE_RL_wci_ctl_op_complete or - MUX_wci_respF_x_wire__wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wci_cfrd: @@ -2266,9 +2263,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'b00 ; assign MUX_wmemi_reqF_q_1__write_1__SEL_2 = WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'b01 ; - always@(wrtSerPos or - IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_mesgWF_w_ETC___d354 or - x1__h19969 or x1__h19978) + always@(*) begin case (wrtSerPos) 2'b00: MUX_wide16Fa__enq_1__VAL_2 = x1__h19969; @@ -2277,9 +2272,7 @@ wire [255:0] dp_out_not_used2; IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_mesgWF_w_ETC___d354; endcase end - always@(wrtSerPos or - IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_metaWF_f_ETC___d377 or - x1__h20492 or x1__h20501) + always@(*) begin case (wrtSerPos) 2'b00: MUX_wide16Fa__enq_1__VAL_1 = x1__h20492; @@ -2557,9 +2550,7 @@ wire [255:0] dp_out_not_used2; // wsiS_reqFifo__D_OUT[39:8] != 32'b00000000000000000000000000000000) ; // register impreciseBurst - always@(WILL_FIRE_RL_wmwt_doAbort or - MUX_impreciseBurst__write_1__SEL_2 or - WILL_FIRE_RL_wmwt_messageFinalize) + always@(*) case (1'b1) WILL_FIRE_RL_wmwt_doAbort: impreciseBurst__D_IN = 1'b0; MUX_impreciseBurst__write_1__SEL_2: impreciseBurst__D_IN = 1'b1; @@ -2572,11 +2563,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wmwt_doAbort ; // register mesgLength - always@(WILL_FIRE_RL_wmwt_doAbort or - MUX_mesgLength__write_1__SEL_2 or - MUX_mesgLength__write_1__VAL_2 or - MUX_endOfMessage__write_1__SEL_1 or - MUX_mesgLength__write_1__VAL_3 or WILL_FIRE_RL_wmwt_messageFinalize) + always@(*) case (1'b1) WILL_FIRE_RL_wmwt_doAbort: mesgLength__D_IN = 15'b010101010101010; MUX_mesgLength__write_1__SEL_2: @@ -2650,9 +2637,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wci_ctrl_IsO ; // register opcode - always@(WILL_FIRE_RL_wmwt_doAbort or - WILL_FIRE_RL_wmwt_mesgBegin or - MUX_opcode__write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + always@(*) case (1'b1) WILL_FIRE_RL_wmwt_doAbort: opcode__D_IN = 9'b010101010; WILL_FIRE_RL_wmwt_mesgBegin: opcode__D_IN = MUX_opcode__write_1__VAL_2; @@ -2664,8 +2649,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wmwt_mesgBegin ; // register preciseBurst - always@(WILL_FIRE_RL_wmwt_doAbort or - MUX_mesgLength__write_1__SEL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + always@(*) case (1'b1) WILL_FIRE_RL_wmwt_doAbort: preciseBurst__D_IN = 1'b0; MUX_mesgLength__write_1__SEL_2: preciseBurst__D_IN = 1'b1; @@ -2733,10 +2717,7 @@ wire [255:0] dp_out_not_used2; assign rdSerUnroll__EN = MUX_rdSerEmpty__write_1__PSEL_1 ; // register rdSyncWord - always@(WILL_FIRE_RL_rdSer_body or - MUX_rdSyncWord__write_1__VAL_1 or - WILL_FIRE_RL_rdSer_begin or - MUX_rdSyncWord__write_1__VAL_2 or WILL_FIRE_RL_rdSer_sync) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_rdSer_body: @@ -2756,9 +2737,7 @@ wire [255:0] dp_out_not_used2; assign readMeta__EN = CAN_FIRE_RL_wmrd_mesgBegin ; // register readyToPush - always@(WILL_FIRE_RL_wmwt_doAbort or - MUX_impreciseBurst__write_1__SEL_2 or - MUX_endOfMessage__write_1__SEL_1) + always@(*) case (1'b1) WILL_FIRE_RL_wmwt_doAbort: readyToPush__D_IN = 1'b0; MUX_impreciseBurst__write_1__SEL_2: readyToPush__D_IN = 1'b1; @@ -2821,7 +2800,7 @@ wire [255:0] dp_out_not_used2; MUX_wci_illegalEdge__write_1__SEL_2 ; // register wci_nState - always@(wci_reqF__D_OUT) + always@(*) begin case (wci_reqF__D_OUT[36:34]) 3'b000: wci_nState__D_IN = 3'b001; @@ -2860,11 +2839,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wci_respF_both || WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b00 || WILL_FIRE_RL_wci_respF_decCtr ; - always@(WILL_FIRE_RL_wci_respF_both or - MUX_wci_respF_q_0__write_1__VAL_1 or - MUX_wci_respF_q_0__write_1__SEL_2 or - MUX_wci_respF_q_0__write_1__VAL_2 or - WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wci_respF_both: @@ -2881,10 +2856,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wci_respF_both || WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b01 || WILL_FIRE_RL_wci_respF_decCtr ; - always@(WILL_FIRE_RL_wci_respF_both or - MUX_wci_respF_q_1__write_1__VAL_1 or - MUX_wci_respF_q_1__write_1__SEL_2 or - MUX_wci_respF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wci_respF_both: @@ -2929,11 +2901,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wmemi_dhF_decCtr || WILL_FIRE_RL_wmemi_dhF_incCtr ; // register wmemi_dhF_q_0 - always@(WILL_FIRE_RL_wmemi_dhF_both or - MUX_wmemi_dhF_q_0__write_1__VAL_1 or - MUX_wmemi_dhF_q_0__write_1__SEL_2 or - MUX_wmemi_dhF_q_0__write_1__VAL_2 or - WILL_FIRE_RL_wmemi_dhF_decCtr or wmemi_dhF_q_1) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmemi_dhF_both: @@ -2951,10 +2919,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wmemi_dhF_decCtr ; // register wmemi_dhF_q_1 - always@(WILL_FIRE_RL_wmemi_dhF_both or - MUX_wmemi_dhF_q_1__write_1__VAL_1 or - MUX_wmemi_dhF_q_1__write_1__SEL_2 or - MUX_wmemi_dhF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmemi_dhF_both: @@ -2994,11 +2959,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wmemi_reqF_incCtr ; // register wmemi_reqF_q_0 - always@(WILL_FIRE_RL_wmemi_reqF_both or - MUX_wmemi_reqF_q_0__write_1__VAL_1 or - MUX_wmemi_reqF_q_0__write_1__SEL_2 or - MUX_wmemi_reqF_q_0__write_1__VAL_2 or - WILL_FIRE_RL_wmemi_reqF_decCtr or wmemi_reqF_q_1) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmemi_reqF_both: @@ -3016,10 +2977,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wmemi_reqF_decCtr ; // register wmemi_reqF_q_1 - always@(WILL_FIRE_RL_wmemi_reqF_both or - MUX_wmemi_reqF_q_1__write_1__VAL_1 or - MUX_wmemi_reqF_q_1__write_1__SEL_2 or - MUX_wmemi_reqF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wmemi_reqF_decCtr) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmemi_reqF_both: @@ -3166,11 +3124,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b00 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; - always@(WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_0__write_1__VAL_1 or - MUX_wsiM_reqFifo_q_0__write_1__SEL_2 or - MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or - WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wsiM_reqFifo_both: @@ -3189,11 +3143,7 @@ wire [255:0] dp_out_not_used2; WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b01 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; - always@(WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_1__write_1__VAL_1 or - MUX_wsiM_reqFifo_q_1__write_1__SEL_2 or - MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or - WILL_FIRE_RL_wsiM_reqFifo_decCtr) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wsiM_reqFifo_both: @@ -3341,8 +3291,7 @@ wire [255:0] dp_out_not_used2; CAN_FIRE_RL_wrtSer_body ? x__h15126[9:0] : mesgWF_rRdPtr[9:0] ; // submodule metaRF - always@(rdSerPos or - rdSerStage_3 or wide16Fb__D_OUT or rdSerStage_1 or rdSerStage_2) + always@(*) begin case (rdSerPos) 2'b00: metaRF__D_IN = wide16Fb__D_OUT[31:0]; @@ -3470,20 +3419,7 @@ wire [255:0] dp_out_not_used2; assign x_burstLength__h22437 = (readMeta[23:0] == 24'b000000000000000000000000) ? 12'b01 : readMeta[16:5] ; assign x_byteEn__h22438 = (readMeta[23:0] == 24'b000000000000000000000000) ? 32'b00000000000000000000000000000000 : 32'hFFFFFFFF ; - always@(wci_reqF__D_OUT or - dlyCtrl or - dlyHoldoffBytes or - dlyHoldoffCycles or - mesgWtCount or - mesgRdCount or - bytesWritten or - rdat__h21847 or - wsiS_extStatusW__wget or - wsiM_extStatusW__wget or - wmemiWrReq or - wmemiRdReq or - wmemiRdResp or - rdat__h22030 or rdat__h22038 or rdat__h22046 or rdat__h22054) + always@(*) begin case (wci_reqF__D_OUT[51:32]) 20'h0: x_data__h21804 = dlyCtrl; @@ -3510,7 +3446,7 @@ wire [255:0] dp_out_not_used2; default: x_data__h21804 = 32'b00000000000000000000000000000000; endcase end - always@(wrtSerPos or wide16Fa__FULL_N) + always@(*) begin case (wrtSerPos) // 2'b00, 2'b01, 2'b10 @@ -3528,7 +3464,7 @@ wire [255:0] dp_out_not_used2; wrtSerPos != 2'b11 || wide16Fa__FULL_N; endcase end - always@(wrtSerPos) + always@(*) begin case (wrtSerPos) // 2'b00, 2'b01, 2'b10, 2'b11: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; diff --git a/vtr_flow/benchmarks/verilog/mkPktMerge.v b/vtr_flow/benchmarks/verilog/mkPktMerge.v index 6bf067203c1..2ba4e347ff5 100755 --- a/vtr_flow/benchmarks/verilog/mkPktMerge.v +++ b/vtr_flow/benchmarks/verilog/mkPktMerge.v @@ -200,8 +200,7 @@ module mkPktMerge(CLK, WILL_FIRE_RL_fi0_advance ; // register fi0HasPrio - always@(WILL_FIRE_RL_arbitrate or - fi0HasPrio or WILL_FIRE_RL_fi0_advance or WILL_FIRE_RL_fi1_advance) + always@(*) begin // case (1'b1) // synopsys parallel_case // WILL_FIRE_RL_arbitrate: fi0HasPrio__D_IN = !fi0HasPrio; @@ -246,10 +245,7 @@ module mkPktMerge(CLK, assign fi1__CLR = 1'b0 ; // submodule fo - always@(WILL_FIRE_RL_arbitrate or - MUX_fo__enq_1__VAL_1 or - WILL_FIRE_RL_fi0_advance or - fi0__D_OUT or WILL_FIRE_RL_fi1_advance or fi1__D_OUT) + always@(*) begin // case (1'b1) // synopsys parallel_case //WILL_FIRE_RL_arbitrate: fo__D_IN = MUX_fo__enq_1__VAL_1; diff --git a/vtr_flow/benchmarks/verilog/mkSMAdapter4B.v b/vtr_flow/benchmarks/verilog/mkSMAdapter4B.v index 1065be1fb2c..a610692aecc 100644 --- a/vtr_flow/benchmarks/verilog/mkSMAdapter4B.v +++ b/vtr_flow/benchmarks/verilog/mkSMAdapter4B.v @@ -1819,10 +1819,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; assign MUX_wsiM_reqFifo_c_r__write_1__VAL_1 = wsiM_reqFifo_c_r - 2'b01 ; assign MUX_wsiM_reqFifo_c_r__write_1__VAL_2 = wsiM_reqFifo_c_r + 2'b01 ; assign MUX_wci_respF_x_wire__wset_1__VAL_2 = { 2'b01, x_data__h15447 } ; - always@(WILL_FIRE_RL_wci_ctl_op_complete or - MUX_wci_respF_x_wire__wset_1__VAL_1 or - WILL_FIRE_RL_wci_cfrd or - MUX_wci_respF_x_wire__wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wci_ctl_op_complete: @@ -1923,12 +1920,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; { 4'b0101, x__h18884, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; assign MUX_wmi_reqF_x_wire__wset_1__VAL_3 = { 4'b0011, x__h16715, 1'b0, addr__h16647, 12'b000000000001 } ; - always@(WILL_FIRE_RL_wmwt_requestPrecise or - MUX_wmi_reqF_x_wire__wset_1__VAL_1 or - WILL_FIRE_RL_wmrd_mesgBodyRequest or - MUX_wmi_reqF_x_wire__wset_1__VAL_2 or - WILL_FIRE_RL_wmwt_messagePushImprecise or - MUX_wmi_reqF_x_wire__wset_1__VAL_3) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmwt_requestPrecise: @@ -2177,9 +2169,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; assign firstMsgReq__D_IN = 1'b0 ; // register impreciseBurst - always@(WILL_FIRE_RL_wmwt_doAbort or - MUX_impreciseBurst__write_1__SEL_2 or - WILL_FIRE_RL_wmwt_messageFinalize) + always@(*) case (1'b1) WILL_FIRE_RL_wmwt_doAbort: impreciseBurst__D_IN = 1'b0; MUX_impreciseBurst__write_1__SEL_2: impreciseBurst__D_IN = 1'b1; @@ -2204,9 +2194,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wci_ctrl_IsO ; // register mesgCount - always@(MUX_mesgCount__write_1__SEL_1 or - MUX_mesgCount__write_1__VAL_1 or - WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) + always@(*) begin case (1'b1) // synopsys parallel_case MUX_mesgCount__write_1__SEL_1: @@ -2223,11 +2211,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wci_ctrl_IsO ; // register mesgLength - always@(WILL_FIRE_RL_wmwt_doAbort or - MUX_mesgLength__write_1__SEL_2 or - MUX_mesgLength__write_1__VAL_2 or - WILL_FIRE_RL_wmwt_messageFinalize or - MUX_endOfMessage__write_1__SEL_1 or MUX_mesgLength__write_1__VAL_4) + always@(*) case (1'b1) WILL_FIRE_RL_wmwt_doAbort: mesgLength__D_IN = 15'b010101010101010; MUX_mesgLength__write_1__SEL_2: @@ -2279,9 +2263,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wmwt_requestPrecise ; // register opcode - always@(WILL_FIRE_RL_wmwt_doAbort or - WILL_FIRE_RL_wmwt_mesgBegin or - MUX_opcode__write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + always@(*) case (1'b1) WILL_FIRE_RL_wmwt_doAbort: opcode__D_IN = 9'b010101010; WILL_FIRE_RL_wmwt_mesgBegin: opcode__D_IN = MUX_opcode__write_1__VAL_2; @@ -2294,8 +2276,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wmwt_doAbort ; // register preciseBurst - always@(WILL_FIRE_RL_wmwt_doAbort or - MUX_mesgLength__write_1__SEL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + always@(*) case (1'b1) WILL_FIRE_RL_wmwt_doAbort: preciseBurst__D_IN = 1'b0; MUX_mesgLength__write_1__SEL_2: preciseBurst__D_IN = 1'b1; @@ -2308,9 +2289,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wmwt_doAbort ; // register readyToPush - always@(WILL_FIRE_RL_wmwt_doAbort or - MUX_impreciseBurst__write_1__SEL_2 or - MUX_endOfMessage__write_1__SEL_1) + always@(*) case (1'b1) WILL_FIRE_RL_wmwt_doAbort: readyToPush__D_IN = 1'b0; MUX_impreciseBurst__write_1__SEL_2: readyToPush__D_IN = 1'b1; @@ -2333,11 +2312,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; assign smaCtrl__EN = WILL_FIRE_RL_wci_cfwr && wci_reqF__D_OUT[39:32] == 8'h0 ; // register thisMesg - always@(MUX_endOfMessage__write_1__SEL_1 or - MUX_thisMesg__write_1__VAL_1 or - WILL_FIRE_RL_wmrd_mesgBegin or - MUX_thisMesg__write_1__VAL_2 or - WILL_FIRE_RL_wmwt_requestPrecise or WILL_FIRE_RL_wci_ctrl_IsO) + always@(*) begin case (1'b1) // synopsys parallel_case MUX_endOfMessage__write_1__SEL_1: @@ -2399,7 +2374,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; MUX_wci_illegalEdge__write_1__SEL_2 ; // register wci_nState - always@(wci_reqF__D_OUT) + always@(*) begin case (wci_reqF__D_OUT[36:34]) 3'b000: wci_nState__D_IN = 3'b001; @@ -2438,11 +2413,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b00 || WILL_FIRE_RL_wci_respF_both || WILL_FIRE_RL_wci_respF_decCtr ; - always@(MUX_wci_respF_q_0__write_1__SEL_1 or - MUX_wci_respF_q_0__write_1__VAL_1 or - WILL_FIRE_RL_wci_respF_both or - MUX_wci_respF_q_0__write_1__VAL_2 or - WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + always@(*) begin case (1'b1) // synopsys parallel_case MUX_wci_respF_q_0__write_1__SEL_1: @@ -2459,10 +2430,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b01 || WILL_FIRE_RL_wci_respF_both || WILL_FIRE_RL_wci_respF_decCtr ; - always@(MUX_wci_respF_q_1__write_1__SEL_1 or - MUX_wci_respF_q_0__write_1__VAL_1 or - WILL_FIRE_RL_wci_respF_both or - MUX_wci_respF_q_1__write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + always@(*) begin case (1'b1) // synopsys parallel_case MUX_wci_respF_q_1__write_1__SEL_1: @@ -2495,11 +2463,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wmi_dhF_decCtr || WILL_FIRE_RL_wmi_dhF_incCtr ; // register wmi_dhF_q_0 - always@(WILL_FIRE_RL_wmi_dhF_both or - MUX_wmi_dhF_q_0__write_1__VAL_1 or - MUX_wmi_dhF_q_0__write_1__SEL_2 or - MUX_wmi_dhF_q_0__write_1__VAL_2 or - WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_dhF_both: @@ -2516,10 +2480,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 - always@(WILL_FIRE_RL_wmi_dhF_both or - MUX_wmi_dhF_q_1__write_1__VAL_1 or - MUX_wmi_dhF_q_1__write_1__SEL_2 or - MUX_wmi_dhF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_dhF_both: @@ -2545,10 +2506,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wmi_mFlagF_incCtr ; // register wmi_mFlagF_q_0 - always@(WILL_FIRE_RL_wmi_mFlagF_both or - MUX_wmi_mFlagF_q_0__write_1__VAL_1 or - MUX_wmi_mFlagF_q_0__write_1__SEL_2 or - value__h6065 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_mFlagF_both: @@ -2564,10 +2522,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_mFlagF_q_1 - always@(WILL_FIRE_RL_wmi_mFlagF_both or - MUX_wmi_mFlagF_q_1__write_1__VAL_1 or - MUX_wmi_mFlagF_q_1__write_1__SEL_2 or - value__h6065 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_mFlagF_both: @@ -2599,11 +2554,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wmi_reqF_decCtr || WILL_FIRE_RL_wmi_reqF_incCtr ; // register wmi_reqF_q_0 - always@(MUX_wmi_reqF_q_0__write_1__SEL_1 or - MUX_wmi_reqF_q_0__write_1__VAL_1 or - WILL_FIRE_RL_wmi_reqF_both or - MUX_wmi_reqF_q_0__write_1__VAL_2 or - WILL_FIRE_RL_wmi_reqF_decCtr or wmi_reqF_q_1) + always@(*) begin case (1'b1) // synopsys parallel_case MUX_wmi_reqF_q_0__write_1__SEL_1: @@ -2620,10 +2571,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wmi_reqF_decCtr ; // register wmi_reqF_q_1 - always@(MUX_wmi_reqF_q_1__write_1__SEL_1 or - MUX_wmi_reqF_q_0__write_1__VAL_1 or - WILL_FIRE_RL_wmi_reqF_both or - MUX_wmi_reqF_q_1__write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr) + always@(*) begin case (1'b1) // synopsys parallel_case MUX_wmi_reqF_q_1__write_1__SEL_1: @@ -2705,11 +2653,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b00 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; - always@(WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_0__write_1__VAL_1 or - MUX_wsiM_reqFifo_q_0__write_1__SEL_2 or - MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or - WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wsiM_reqFifo_both: @@ -2728,11 +2672,7 @@ assign dummy3 = &wsiS_reqFifo__D_OUT; WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b01 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; - always@(WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_1__write_1__VAL_1 or - MUX_wsiM_reqFifo_q_1__write_1__SEL_2 or - MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or - WILL_FIRE_RL_wsiM_reqFifo_decCtr) + always@(*) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wsiM_reqFifo_both: @@ -2911,13 +2851,7 @@ assign b__h19084 = { {fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredi assign x_length__h17087 = { 2'b00, IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753 } ; - always@(wci_reqF__D_OUT or - smaCtrl or - mesgCount or - abortCount or - thisMesg or - lastMesg or - rdat__h15540 or wsiS_extStatusW__wget or wsiM_extStatusW__wget) + always@(*) begin case (wci_reqF__D_OUT[39:32]) 8'h0: x_data__h15447 = smaCtrl; @@ -2935,11 +2869,7 @@ assign b__h19084 = { {fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredi default: x_data__h15447 = 32'b00000000000000000000000000000000; endcase end - always@(MUX_endOfMessage__write_1__SEL_1 or - MUX_wmi_mFlagF_x_wire__wset_1__VAL_1 or - MUX_wmi_mFlagF_x_wire__wset_1__SEL_2 or - WILL_FIRE_RL_wmwt_requestPrecise or - MUX_wmi_mFlagF_x_wire__wset_1__VAL_3) + always@(*) begin case (1'b1) // synopsys parallel_case MUX_endOfMessage__write_1__SEL_1: diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index d3ee5074376..f6bbfc6c908 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -247,7 +247,7 @@ module delay1x3 (datain, dataout, clk); end end - always @(state or trigger or count) + always @(*) begin case (state) 0 : diff --git a/vtr_flow/benchmarks/verilog/spree.v b/vtr_flow/benchmarks/verilog/spree.v index 3494a3c0c13..b1e108c4b5d 100644 --- a/vtr_flow/benchmarks/verilog/spree.v +++ b/vtr_flow/benchmarks/verilog/spree.v @@ -2202,7 +2202,7 @@ output [31:0] d_writedataout; reg [3:0] d_byteena; reg [31:0] d_writedataout; -always @(write_data or d_address or store_size) +always @(*) begin case (store_size) 2'b11: @@ -2276,7 +2276,7 @@ assign d_address [1:0] =d_readdatain [25:24]; //assume always full-word-access -always @(d_readdatain or d_address ) +always @(*) begin d_loadresult[31:0]=d_readdatain[31:0]; end @@ -2404,7 +2404,7 @@ output [31:0] result; reg [31:0] logic_result; -always@(opA or opB or op ) +always@(*) case(op) 2'b00: logic_result=opA&opB; @@ -2876,7 +2876,7 @@ output stalled; reg T,Tnext; // State machine for Stalling 1 cycle - always@(request or T) + always@(*) begin case(T) 1'b0: Tnext=request; diff --git a/vtr_flow/benchmarks/verilog/stereovision1.v b/vtr_flow/benchmarks/verilog/stereovision1.v index 5a9765831c4..0c8033af58a 100755 --- a/vtr_flow/benchmarks/verilog/stereovision1.v +++ b/vtr_flow/benchmarks/verilog/stereovision1.v @@ -2294,7 +2294,7 @@ module my_wrapper_divider(rst, clk, data_in_a, data_in_b, data_out); y <= Y; end - always @(y) + always @(*) begin case (y) S1 : @@ -2370,7 +2370,7 @@ module my_divider(clk, rst, start, LA, EB, data_in_a, data_in_b, Remainder, data reg [INPUT_WIDTH_A-1:0] DataA; reg ff0; - always @(start or y or zero) + always @(*) begin case(y) S1: @@ -2409,7 +2409,7 @@ module my_divider(clk, rst, start, LA, EB, data_in_a, data_in_b, Remainder, data y <= Y; end - always @(y or start or Cout or zero) + always @(*) begin case (y) S1: diff --git a/vtr_flow/benchmarks/verilog/stereovision3.v b/vtr_flow/benchmarks/verilog/stereovision3.v index 1b3e343a2bb..c45692e2a80 100755 --- a/vtr_flow/benchmarks/verilog/stereovision3.v +++ b/vtr_flow/benchmarks/verilog/stereovision3.v @@ -637,7 +637,7 @@ module sv_chip3_hierarchy_no_mem (tm3_clk_v0, tm3_clk_v2, tm3_vidin_llc, tm3_vid endcase end - always @(reg_prog_state or iic_stop) + always @(*) begin case (reg_prog_state) reg_prog1 : From f2da171fc5eff0bf2d41fc791dccce84893048d0 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 12:12:18 -0400 Subject: [PATCH 11/31] Refactor rgconfigmemory to eliminate inferred latches --- vtr_flow/benchmarks/verilog/raygentop.v | 97 ++++--------------------- 1 file changed, 16 insertions(+), 81 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index f6bbfc6c908..acb63435462 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -398,20 +398,6 @@ module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, ori reg next_state; wire we; - reg[27:0] temp_origx; - reg[27:0] temp_origy; - reg[27:0] temp_origz; - reg[15:0] temp_m11; - reg[15:0] temp_m12; - reg[15:0] temp_m13; - reg[15:0] temp_m21; - reg[15:0] temp_m22; - reg[15:0] temp_m23; - reg[15:0] temp_m31; - reg[15:0] temp_m32; - reg[15:0] temp_m33; - reg[20:0] temp_bkcolour; - // <> Can't find translated component 'spram'. Module name may not match spram21x4 spraminst(we, texinfo, CfgData[20:0], clk); assign we = ((CfgData_Ready == 1'b1) & (CfgAddr == 4'b1110)) ? 1'b1 : 1'b0 ; @@ -438,20 +424,22 @@ module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, ori end else begin - state <= next_state ; - origx <= temp_origx; - origy <= temp_origy; - origz <= temp_origz; - m11 <= temp_m11; - m12 <= temp_m12; - m13 <= temp_m13; - m21 <= temp_m21; - m22 <= temp_m22; - m23 <= temp_m23; - m31 <= temp_m31; - m32 <= temp_m32; - m33 <= temp_m33; - bkcolour <= bkcolour; + state <= next_state ; + if (CfgData_Ready) begin + if (CfgAddr == 4'b0001) origx <= CfgData; + if (CfgAddr == 4'b0010) origy <= CfgData; + if (CfgAddr == 4'b0011) origz <= CfgData; + if (CfgAddr == 4'b0100) m11 <= CfgData[15:0]; + if (CfgAddr == 4'b0101) m12 <= CfgData[15:0]; + if (CfgAddr == 4'b0110) m13 <= CfgData[15:0]; + if (CfgAddr == 4'b0111) m21 <= CfgData[15:0]; + if (CfgAddr == 4'b1000) m22 <= CfgData[15:0]; + if (CfgAddr == 4'b1001) m23 <= CfgData[15:0]; + if (CfgAddr == 4'b1010) m31 <= CfgData[15:0]; + if (CfgAddr == 4'b1011) m32 <= CfgData[15:0]; + if (CfgAddr == 4'b1100) m33 <= CfgData[15:0]; + if (CfgAddr == 4'b1101) bkcolour <= CfgData[20:0]; + end end end @@ -470,59 +458,6 @@ module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, ori begin next_state = 0 ; end - - if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0001)) - begin - temp_origx = CfgData ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0010)) - begin - temp_origy = CfgData ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0011)) - begin - temp_origz = CfgData ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0100)) - begin - temp_m11 = CfgData[15:0] ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0101)) - begin - temp_m12 = CfgData[15:0] ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0110)) - begin - temp_m13 = CfgData[15:0] ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0111)) - begin - temp_m21 = CfgData[15:0] ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1000)) - begin - temp_m22 = CfgData[15:0] ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1001)) - begin - temp_m23 = CfgData[15:0] ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1010)) - begin - temp_m31 = CfgData[15:0] ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1011)) - begin - temp_m32 = CfgData[15:0] ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1100)) - begin - temp_m33 = CfgData[15:0] ; - end - else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1101)) - begin - temp_bkcolour = CfgData[20:0] ; - end end 1 : begin From 2d018c03e6a1c2f6ef2c84bf6da2b8b7027d885a Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 12:33:51 -0400 Subject: [PATCH 12/31] Eliminate latch inference from resultwriter --- vtr_flow/benchmarks/verilog/raygentop.v | 1112 +++++++++++------------ 1 file changed, 552 insertions(+), 560 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index acb63435462..bce9152b878 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -1931,7 +1931,6 @@ hit10c <= temp_hit10c; reg temp_pending01; reg temp_pending10; - reg temp_process01; reg temp_texmap; reg[20:0] temp_texinfol; reg[20:0] temp_shadedataa; @@ -1971,599 +1970,592 @@ hit10c <= temp_hit10c; begin state <= next_state ; -process01 <= temp_process01; -pending01 <= temp_pending01; -pending10 <= temp_pending10; -texmap <= temp_texmap; -texinfol <= temp_texinfol; -shadedataa <= temp_shadedataa; -shadedatab <= temp_shadedatab; -shadedatac <= temp_shadedatac; - - dataout <= {1'b0, - shadedataa[20], - shadedataa[19], - shadedataa[18], - shadedataa[17], - shadedataa[16], - shadedataa[15], - shadedataa[14], - shadedataa[13], - shadedataa[12], - shadedataa[11], - shadedataa[10], - shadedataa[9], - shadedataa[8], - shadedataa[7], - shadedataa[6], - shadedataa[5], - shadedataa[4], - shadedataa[3], - shadedataa[2], - shadedataa[1], - shadedataa[0], - shadedatab[20], - shadedatab[19], - shadedatab[18], - shadedatab[17], - shadedatab[16], - shadedatab[15], - shadedatab[14], - shadedatab[13], - shadedatab[12], - shadedatab[11], - shadedatab[10], - shadedatab[9], - shadedatab[8], - shadedatab[7], - shadedatab[6], - shadedatab[5], - shadedatab[4], - shadedatab[3], - shadedatab[2], - shadedatab[1], - shadedatab[0], - shadedatac[20], - shadedatac[19], - shadedatac[18], - shadedatac[17], - shadedatac[16], - shadedatac[15], - shadedatac[14], - shadedatac[13], - shadedatac[12], - shadedatac[11], - shadedatac[10], - shadedatac[9], - shadedatac[8], - shadedatac[7], - shadedatac[6], - shadedatac[5], - shadedatac[4], - shadedatac[3], - shadedatac[2], - shadedatac[1], - shadedatac[0]} ; + if (state == 0) begin + process01 <= pending01; + end + + pending01 <= temp_pending01; + pending10 <= temp_pending10; + texmap <= temp_texmap; + texinfol <= temp_texinfol; + shadedataa <= temp_shadedataa; + shadedatab <= temp_shadedatab; + shadedatac <= temp_shadedatac; + + dataout <= {1'b0, shadedataa, shadedatab, shadedatac} ; end // end // PAJ used to be assign, but weird error, so added as register assign dataout = {1'b0, end assign addrout = (process01 == 1'b1) ? addrout01 : addrout10 ; - always @(*) - begin - case (state) + always @(*) + begin + case (state) 0 : - begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - if (pending01 == 1'b1 | pending10 == 1'b1) - begin - next_state = 2 ; - end - else - - begin - next_state = 0 ; - end - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - temp_process01 = pending01 ; - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + end + 1 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + end 2 : - begin - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - wantshadedata = 1'b1 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b00 ; - if (process01 == 1'b1) - begin - triID = id01a ; - - end - else - begin - triID = id10a ; - end - if (shadedataready == 1'b1) - begin - if (hita == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) - begin - next_state = 3 ; - end - else - - begin - next_state = 4 ; - end - end - else - begin - next_state = 2 ; - end - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - - if (hita == 1'b1) - begin - temp_shadedataa = shadedata[20:0] ; - temp_texmap = (~shadedata[63]) & shadedata[62] ; - end - else - begin - temp_shadedataa = bkcolour ; - end - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end + begin + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + wantshadedata = 1'b1 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + if (process01 == 1'b1) + begin + triID = id01a ; + + end + else + begin + triID = id10a ; + end + end 3 : - begin - wantshadedata = 1'b0 ; - triID = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - - selectuv[1:0] = 2'b00 ; - next_state = 8 ; - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - temp_texinfol = texinfo ; - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - - end + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + end + 4 : + begin + wantshadedata = 1'b0 ; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + if (process01 == 1'b1) + begin + triID = id01b ; + end + else + begin + triID = id10b ; + end + end + 5 : + begin + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + wantshadedata = 1'b1 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + if (process01 == 1'b1) + begin + triID = id01c ; + end + else + begin + triID = id10c ; + end + end + 6 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + end + 7 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + end 8 : - begin - wantshadedata = 1'b0 ; - triID = 0; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b00 ; - lmenable = 1'b1 ; - if (texmap == 1'b1) - begin - - next_state = 11 ; - end - else - begin - next_state = 4 ; - end - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - temp_shadedataa[6:0] = blb ; - temp_shadedataa[13:7] = blg ; - temp_shadedataa[20:14] = blr ; - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + lmenable = 1'b1 ; + end + 9 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + lmenable = 1'b1 ; + end + 10 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + lmenable = 1'b1 ; + end 11 : - begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - - wanttexel = 1'b1 ; - if (texelready == 1'b1) - begin - next_state = 4 ; - end - else - begin - next_state = 11 ; - end - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - - temp_shadedataa[6:0] = texelb ; - temp_shadedataa[13:7] = texelg ; - temp_shadedataa[20:14] = texelr ; - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b1 ; + end 12 : - begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - - wanttexel = 1'b1 ; - if (texelready == 1'b1) - begin - next_state = 5 ; - end - else - begin - next_state = 12 ; - end - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - temp_shadedatab[6:0] = texelb ; - temp_shadedatab[13:7] = texelg ; - temp_shadedatab[20:14] = texelr ; - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b1 ; + end 13 : - begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - - wanttexel = 1'b1 ; - if (texelready == 1'b1) - begin - next_state = 1 ; - end - else - begin - next_state = 13 ; - end - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - - temp_shadedatac[6:0] = texelb ; - temp_shadedatac[13:7] = texelg ; - temp_shadedatac[20:14] = texelr ; + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b1 ; + end + // Default needed to prevent latch inference; set everything to zero + // for undefined state. This represents a change in design intent + // vs. original code, albeit a subtle one + default: begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + end + endcase + end - end + always @(*) + begin + case (state) + 1 : + begin + if (ack == 1'b1 & process01 == 1'b1) + begin + temp_pending01 = 1'b0 ; + temp_pending10 = pending10; + end + + else if (ack == 1'b1 & process01 == 1'b0) + begin + temp_pending10 = 1'b0 ; + temp_pending01 = pending01; + end + //add an else to hold the register value to prevent + //latch inference while preserving design intent + else begin + temp_pending01 = pending01; + temp_pending10 = pending10; + end + end + // Create a default to avoid latch inference. This has a couple of side effects: + // 1. the two unused states in the FSM will pick up this logic (subtle change + // in design intent) + // 2. We can collapse the case statement to eliminate redundancy -- most + // states calculate these values as follows: + default : + begin + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + //add an else to hold the register value to prevent + //latch inference while preserving design intent + else begin + temp_pending01 = pending01; + end + + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + //add an else to hold the register value to prevent + //latch inference while preserving design intent + else begin + temp_pending10 = pending10; + end + end + endcase + end + + always @(*) + begin + case (state) + 1 : + begin + if (process01 == 1'b1 & ack == 1'b1) + begin + temp_shiften01 = 1'b1; + temp_shiften10 = 1'b1; + end + else begin + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + end + temp_write = 1'b1; + end + // Create a default to avoid latch inference. This has a couple of side effects: + // 1. the two unused states in the FSM will pick up this logic (subtle change + // in design intent) + // 2. We can collapse the case statement to eliminate redundancy -- most + // states calculate these values as follows: + default: begin + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + endcase + end + + always @(*) + begin + case (state) + 2 : + begin + if (hita == 1'b1) + begin + temp_shadedataa = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedataa = bkcolour ; + temp_texmap = texmap; + end + + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol; + + end + 3 : + begin + temp_texinfol = texinfo ; + + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texmap = texmap; + end + 4 : + begin + if (hitb == 1'b1) + begin + temp_shadedatab = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedatab = bkcolour ; + temp_texmap = texmap; + end + temp_shadedataa = shadedataa; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol; + end + 5 : + begin + if (hitc == 1'b1) + begin + temp_shadedatac = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedatac = bkcolour ; + temp_texmap = texmap; + end + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_texinfol = texinfol; + end 6 : - begin - wantshadedata = 1'b0 ; - triID = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b01 ; - next_state = 9 ; - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - temp_texinfol = texinfo ; - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end - 9 : - begin - wantshadedata = 1'b0 ; - triID = 0; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b01 ; - lmenable = 1'b1 ; - if (texmap == 1'b1) - begin - next_state = 12 ; - - end - else - begin - next_state = 5 ; - end - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - - temp_shadedatab[6:0] = blb ; - temp_shadedatab[13:7] = blg ; - temp_shadedatab[20:14] = blr ; - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end + begin + temp_texinfol = texinfo ; + + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texmap = texmap; + end 7 : - begin - wantshadedata = 1'b0 ; - triID = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b10 ; - next_state = 10 ; - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - temp_texinfol = texinfo ; - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end - + begin + temp_texinfol = texinfo ; + + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texmap = texmap; + end + 8 : + begin + temp_shadedataa[6:0] = blb ; + temp_shadedataa[13:7] = blg ; + temp_shadedataa[20:14] = blr ; + + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + 9 : + begin + temp_shadedatab[6:0] = blb ; + temp_shadedatab[13:7] = blg ; + temp_shadedatab[20:14] = blr ; + + temp_shadedataa = shadedataa; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end 10 : - begin - wantshadedata = 1'b0 ; - triID = 0; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b10 ; - if (texmap == 1'b1) - begin - next_state = 13 ; - end - else - begin - next_state = 1 ; - end - - lmenable = 1'b1 ; - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - temp_shadedatac[6:0] = blb ; - temp_shadedatac[13:7] = blg ; - temp_shadedatac[20:14] = blr ; - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end - 4 : - begin - wantshadedata = 1'b0 ; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b01 ; - if (process01 == 1'b1) - begin - triID = id01b ; - end - else - begin + begin + temp_shadedatac[6:0] = blb ; + temp_shadedatac[13:7] = blg ; + temp_shadedatac[20:14] = blr ; + + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + 11 : + begin + temp_shadedataa[6:0] = texelb ; + temp_shadedataa[13:7] = texelg ; + temp_shadedataa[20:14] = texelr ; + + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + 12 : + begin + temp_shadedatab[6:0] = texelb ; + temp_shadedatab[13:7] = texelg ; + temp_shadedatab[20:14] = texelr ; + + temp_shadedataa = shadedataa; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + 13 : + begin + temp_shadedatac[6:0] = texelb ; + temp_shadedatac[13:7] = texelg ; + temp_shadedatac[20:14] = texelr ; + + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + //create a default to avoid latch inference; use to hold + //previous state and thus preserve design intent + default: begin + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol; + temp_texmap = texmap; + end + endcase + end - triID = id10b ; - end - if (shadedataready == 1'b1) + always @(*) + begin + case (state) + 0 : + begin + if (pending01 == 1'b1 | pending10 == 1'b1) + begin + next_state = 2 ; + end + else + begin + next_state = 0 ; + end + end + 1 : + begin + if (ack == 1'b1) + begin + next_state = 0 ; + end + else + begin + next_state = 1 ; + end + end + 2 : + begin + if (shadedataready == 1'b1) + begin + if (hita == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) begin - if (hitb == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) - begin - next_state = 6 ; - end - else - begin - next_state = 5 ; - end - + next_state = 3 ; end - else - begin - next_state = 4 ; - end - - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - - if (hitb == 1'b1) - begin - temp_shadedatab = shadedata[20:0] ; - temp_texmap = (~shadedata[63]) & shadedata[62] ; - end - else - begin - temp_shadedatab = bkcolour ; - end + else - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end - 5 : - begin - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - wantshadedata = 1'b1 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b10 ; - if (process01 == 1'b1) - - begin - triID = id01c ; - end - else begin - triID = id10c ; + next_state = 4 ; end - if (shadedataready == 1'b1) + end + else + begin + next_state = 2 ; + end + end + 3 : + begin + next_state = 8 ; + end + 4 : + begin + if (shadedataready == 1'b1) + begin + if (hitb == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) begin - if (hitc == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) - begin - next_state = 7 ; - - end - else - begin - next_state = 1 ; - end + next_state = 6 ; end - else + else begin next_state = 5 ; end - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - - if (hitc == 1'b1) - begin - temp_shadedatac = shadedata[20:0] ; - temp_texmap = (~shadedata[63]) & shadedata[62] ; - end - else - begin - temp_shadedatac = bkcolour ; - end - - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end - 1 : - - begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - if (ack == 1'b1) + end + else + begin + next_state = 4 ; + end + end + 5 : + begin + if (shadedataready == 1'b1) + begin + if (hitc == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) begin - next_state = 0 ; + next_state = 7 ; + end - else + else begin next_state = 1 ; end - - if (ack == 1'b1 & process01 == 1'b1) - begin - temp_pending01 = 1'b0 ; - end - - else if (ack == 1'b1 & process01 == 1'b0) - begin - temp_pending10 = 1'b0 ; - end - - if (process01 == 1'b1 & ack == 1'b1) - begin - temp_shiften01 = 1'b1; - temp_shiften10 = 1'b1; - end - temp_write = 1'b1; - end - endcase - end + end + else + begin + next_state = 5 ; + end + end + 6 : + begin + next_state = 9 ; + end + 7 : + begin + next_state = 10 ; + end + 8 : + begin + if (texmap == 1'b1) + begin + next_state = 11 ; + end + else + begin + next_state = 4 ; + end + end + 9 : + begin + if (texmap == 1'b1) + begin + next_state = 12 ; + + end + else + begin + next_state = 5 ; + end + end + 10 : + begin + if (texmap == 1'b1) + begin + next_state = 13 ; + end + else + begin + next_state = 1 ; + end + end + 11 : + begin + if (texelready == 1'b1) + begin + next_state = 4 ; + end + else + begin + next_state = 11 ; + end + end + 12 : + begin + if (texelready == 1'b1) + begin + next_state = 5 ; + end + else + begin + next_state = 12 ; + end + end + 13 : + begin + if (texelready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 13 ; + end + end + // create a default to avoid latch inference; preserving intent by holding + // circuit in invalid states + default: begin + next_state = state; + end + endcase + end endmodule ////////////////////////////////////////////////////////////////////////////////////////////// // From 75f86e62ba155bdf95fe5000c28a6dcaeff71430 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 14:26:14 -0400 Subject: [PATCH 13/31] Eliminate latches from raygencont --- vtr_flow/benchmarks/verilog/raygentop.v | 915 +++++++++++++++--------- 1 file changed, 596 insertions(+), 319 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index bce9152b878..c4a9db33ab0 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -1290,8 +1290,25 @@ rgAddr <= temp_rgAddr; addr[1:0] <= temp_addr[1:0]; state <= next_state ; - dir <= temp_dir; - cycles <= temp_cycles; + // dir is only loaded if state == 1, make enable logic here rather + // than risk latch inference below + if (state == 1) begin + dir <= dirIn; + end + + // This matches original logic for all explicitly defined + // states; with a simulation testbench, we could show whether + // there are bugs introduced by allowing this to increment + // during states that are not part of the next state logic + if (state == 0) begin + if (go) begin + cycles <= 0; + end + end + else begin + cycles <= cycles + 1; + end + loaded <= temp_loaded; groupID <= temp_groupID; count <= temp_count; @@ -1309,250 +1326,575 @@ rgAddr <= temp_rgAddr; assign nas0 = temp_nas0; assign nas1 = temp_nas1; - always @(*) - begin - case (state) + always @(*) + begin + case (state) 0 : - begin - as = 1'b0 ; - wantDir = 1'b0 ; - if (go == 1'b1) + begin + temp_addr[1:0] = 2'b00 ; + temp_loaded = 2'b00 ; + temp_groupID = 2'b00 ; + temp_count = initcount ; + temp_active = 1'b0 ; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + 1 : + begin + if (dirReady == 1'b1 & addr[1:0] == 2'b10) + begin + if (active == 1'b0) begin - next_state = 1 ; + temp_loaded[0] = 1'b1 ; end - else + else begin - next_state = 0 ; + temp_loaded[1] = 1'b1 ; end - statepeek = 3'b001 ; - temp_busyout = 1'b0; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; - - - if (go == 1'b1) - begin - temp_cycles = 0; - end + end + temp_addr[1:0] = addr; + temp_groupID = groupID; + temp_count = count; + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + 2 : + begin + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + temp_active = active; + temp_addr[1:0] = addr[1:0] + 2'b01 ; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + else if ((ack == 1'b1) & addr[1:0] == 2'b10) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_active = active; + temp_addr[1:0] = addr; + temp_raygroupvalid0 = 1'b1 ; + temp_raygroupvalid1 = raygroupvalid1; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + temp_active = active; + temp_addr[1:0] = addr; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = 1'b1 ; + end + else if ((loaded[0]) == 1'b0) + begin + temp_active = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + else if ((loaded[1]) == 1'b0) + begin + temp_active = 1'b1 ; temp_addr[1:0] = 2'b00 ; - temp_loaded = 2'b00 ; - temp_groupID = 2'b00 ; - temp_count = initcount ; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + end + else begin + temp_addr[1:0] = addr; + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + temp_loaded = loaded; + temp_groupID = groupID; + temp_count = count; + end + 3 : + begin + if ((busy[0]) == 1'b1) + begin + temp_groupID = {groupID[1], ~groupID[0]} ; + temp_raygroupvalid0 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + temp_raygroupvalid1 = 1'b1 ; + temp_active = active; + + end + else if ((loaded[1]) == 1'b0) + begin + temp_raygroupvalid1 = raygroupvalid1 ; + temp_active = 1'b1 ; + end + else + begin + temp_raygroupvalid1 = raygroupvalid1 ; temp_active = 1'b0 ; + end + end + else begin + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + temp_count = count; + temp_groupID = groupID; + end + temp_loaded = {loaded[1], 1'b0} ; + temp_addr[1:0] = 2'b00 ; + end + 4 : + begin + if ((busy[1]) == 1'b1) + begin + temp_groupID = {~groupID[1], groupID[0]} ; + temp_raygroupvalid1 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_raygroupvalid0 = 1'b1 ; + temp_active = active; + end - end - 1 : - begin - as = dirReady ; - wantDir = 1'b1 ; - if (dirReady == 1'b1) + else if ((loaded[0]) == 1'b0) begin - next_state = 2 ; + temp_raygroupvalid0 = raygroupvalid0 ; + temp_active = 1'b0 ; end - else + else begin - next_state = 1 ; + temp_raygroupvalid0 = raygroupvalid0; + temp_active = 1'b1 ; end - statepeek = 3'b010 ; - temp_busyout = 1'b1; - if (addr[1:0] == 2'b00 & dirReady == 1'b1 & active == 1'b0) - begin - temp_nas0 = 1'b1; - temp_nas1 = 1'b1; - end - - temp_dir = dirIn ; - if (dirReady == 1'b1 & addr[1:0] == 2'b10) - begin - if (active == 1'b0) - begin - temp_loaded[0] = 1'b1 ; - end - else - begin - temp_loaded[1] = 1'b1 ; - end - end - temp_cycles = cycles + 1 ; + end + else begin + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + temp_count = count; + temp_groupID = groupID; + end + temp_loaded = {1'b0, loaded[0]} ; + temp_addr[1:0] = 2'b00 ; + end + // add a default to prevent latch inference. preserve original + // design intent and hold previous state + default: begin + temp_addr[1:0] = addr; + temp_loaded = loaded; + temp_groupID = groupID; + temp_count = count; + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + endcase + end + always @(*) + begin + case (state) + 0 : + begin + as = 1'b0 ; + wantDir = 1'b0 ; + statepeek = 3'b001 ; + temp_busyout = 1'b0; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + end + 1 : + begin + as = dirReady ; + wantDir = 1'b1 ; + statepeek = 3'b010 ; + temp_busyout = 1'b1; + if (addr[1:0] == 2'b00 & dirReady == 1'b1 & active == 1'b0) + begin + temp_nas0 = 1'b1; + temp_nas1 = 1'b1; + end + end + 2 : + begin + wantDir = 1'b0 ; + as = 1'b1 ; + statepeek = 3'b011 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + end + // Create a default to avoid latch inference + // use the pattern from other states to make + // choices about how to calculate each value. + // this preserves design intent for defined states + // while not guaranteeing identical behavior for + // undefined states. + // Note that states 3 and 4 were previously explicitly + // defined for these signals but match the defaults. + default: begin + //***NOTE: The original behavior of "wantDir" and "as" is almost + // certainly buggy, as the values are undefined for + // states 3-7 and so behavior during states 3-4 (which are + // actually used unlike states 5-7) would have + // held as = 1 and wantDir = 0 regardless of whether + // that was the desired effect or not. It seems unlikely + // that latched behavior was envisioned, as the clock + // for these latches is not well defined. We thus have + // to guess as to the desired value for these bits in + // states 3, 4, (and 5-7 for that matter). The next state + // logic bounces around, so there's not much insight + // to be gleaned from it. The safe choice appears to be + // to set them both inactive even though that definitely + // changes the behavior of the circuit by allowing as to + // clear on transitions from states 2-3 or 2-4. + wantDir = 1'b0; + as = 1'b0; + statepeek = state + 1 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + end + endcase + end - end + always @(*) + begin + case (state) + 0 : + begin + if (go == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + end + 1 : + begin + if (dirReady == 1'b1) + begin + next_state = 2 ; + end + else + begin + next_state = 1 ; + end + end 2 : - begin - wantDir = 1'b0 ; - as = 1'b1 ; - if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + next_state = 1 ; + end + else if (ack == 1'b1) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) begin - next_state = 1 ; + next_state = 3 ; end - else if (ack == 1'b1) + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) begin - if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) - begin - next_state = 3 ; - end - else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) - begin - next_state = 4 ; - end - else if (loaded != 2'b11) - begin - - next_state = 1 ; - end - else - begin - next_state = 2 ; - end + next_state = 4 ; end - else + else if (loaded != 2'b11) + begin + next_state = 1 ; + end + else begin next_state = 2 ; end - statepeek = 3'b011 ; - temp_busyout = 1'b1; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; + end + else + begin + next_state = 2 ; + end + end + 3 : + begin + if ((busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (count > 0) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + end + 4 : + begin + if ((busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if (count > 0) + begin - if ((ack == 1'b1) & (addr[1:0] != 2'b10)) - begin - temp_addr[1:0] = addr[1:0] + 2'b01 ; - end - else if ((ack == 1'b1) & addr[1:0] == 2'b10) - begin - if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) - begin - temp_raygroupvalid0 = 1'b1 ; - end - else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) - begin - - temp_raygroupvalid1 = 1'b1 ; - end - else if ((loaded[0]) == 1'b0) - begin - temp_active = 1'b0 ; - temp_addr[1:0] = 2'b00 ; - end - else if ((loaded[1]) == 1'b0) - begin - temp_active = 1'b1 ; - temp_addr[1:0] = 2'b00 ; - end - end + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + end + endcase + end - temp_cycles = cycles + 1 ; - end - 4 : - begin - if ((busy[1]) == 1'b0) + /* Original below -- delete when done */ + + always @(*) + begin + case (state) + 0 : + begin + as = 1'b0 ; + wantDir = 1'b0 ; + if (go == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + statepeek = 3'b001 ; + temp_busyout = 1'b0; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + + if (go == 1'b1) + begin + temp_cycles = 0; + end + temp_addr[1:0] = 2'b00 ; + temp_loaded = 2'b00 ; + temp_groupID = 2'b00 ; + temp_count = initcount ; + temp_active = 1'b0 ; + + end + 1 : + begin + as = dirReady ; + wantDir = 1'b1 ; + if (dirReady == 1'b1) + begin + next_state = 2 ; + end + else + begin + next_state = 1 ; + end + statepeek = 3'b010 ; + temp_busyout = 1'b1; + if (addr[1:0] == 2'b00 & dirReady == 1'b1 & active == 1'b0) + begin + temp_nas0 = 1'b1; + temp_nas1 = 1'b1; + end + + temp_dir = dirIn ; + if (dirReady == 1'b1 & addr[1:0] == 2'b10) + begin + if (active == 1'b0) begin - next_state = 4 ; + temp_loaded[0] = 1'b1 ; end - else if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + else + begin + temp_loaded[1] = 1'b1 ; + end + end + temp_cycles = cycles + 1 ; + + + end + 2 : + begin + wantDir = 1'b0 ; + as = 1'b1 ; + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + next_state = 1 ; + end + else if (ack == 1'b1) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) begin next_state = 3 ; end - else if (count > 0) + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (loaded != 2'b11) begin next_state = 1 ; end - else + else begin - next_state = 0 ; + next_state = 2 ; end - statepeek = 3'b101 ; - temp_busyout = 1'b1; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; + end + else + begin + next_state = 2 ; + end + statepeek = 3'b011 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; - if ((busy[1]) == 1'b1) - begin - temp_groupID[1] = ~groupID[1] ; - temp_raygroupvalid1 = 1'b0 ; - temp_count = count - 1 ; - if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) - begin - temp_raygroupvalid0 = 1'b1 ; - end - - else if ((loaded[0]) == 1'b0) - begin - temp_active = 1'b0 ; - end - else - begin - temp_active = 1'b1 ; - end - end - temp_loaded[1] = 1'b0 ; + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + temp_addr[1:0] = addr[1:0] + 2'b01 ; + end + else if ((ack == 1'b1) & addr[1:0] == 2'b10) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_raygroupvalid0 = 1'b1 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + + temp_raygroupvalid1 = 1'b1 ; + end + else if ((loaded[0]) == 1'b0) + begin + temp_active = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + end + else if ((loaded[1]) == 1'b0) + begin + temp_active = 1'b1 ; temp_addr[1:0] = 2'b00 ; + end + end - temp_cycles = cycles + 1 ; - end + temp_cycles = cycles + 1 ; + end 3 : - begin - if ((busy[0]) == 1'b0) - begin - next_state = 3 ; + begin + if ((busy[0]) == 1'b0) + begin + next_state = 3 ; - end - else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (count > 0) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + + end + statepeek = 3'b100 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + if ((busy[0]) == 1'b1) + begin + temp_groupID[0] = ~groupID[0] ; + temp_raygroupvalid0 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) begin - next_state = 4 ; + temp_raygroupvalid1 = 1'b1 ; + end - else if (count > 0) + else if ((loaded[1]) == 1'b0) begin - next_state = 1 ; + temp_active = 1'b1 ; end - else + else begin - next_state = 0 ; - + temp_active = 1'b0 ; end - statepeek = 3'b100 ; - temp_busyout = 1'b1; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; + end + temp_loaded[0] = 1'b0 ; + temp_addr[1:0] = 2'b00 ; - if ((busy[0]) == 1'b1) - begin - temp_groupID[0] = ~groupID[0] ; - temp_raygroupvalid0 = 1'b0 ; - temp_count = count - 1 ; - if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) - begin - temp_raygroupvalid1 = 1'b1 ; - - end - else if ((loaded[1]) == 1'b0) - begin - temp_active = 1'b1 ; - end - else - begin - temp_active = 1'b0 ; - end - end - temp_loaded[0] = 1'b0 ; - temp_addr[1:0] = 2'b00 ; + temp_cycles = cycles + 1 ; + end + 4 : + begin + if ((busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if (count > 0) + begin - temp_cycles = cycles + 1 ; - end - endcase + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + statepeek = 3'b101 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + if ((busy[1]) == 1'b1) + begin + temp_groupID[1] = ~groupID[1] ; + temp_raygroupvalid1 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_raygroupvalid0 = 1'b1 ; + end + + else if ((loaded[0]) == 1'b0) + begin + temp_active = 1'b0 ; + end + else + begin + temp_active = 1'b1 ; + end + end + temp_loaded[1] = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + + temp_cycles = cycles + 1 ; + end + endcase end endmodule - - - - - - - module resultrecieve (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); + module resultrecieve (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); output valid01; reg valid01; @@ -1616,34 +1958,6 @@ rgAddr <= temp_rgAddr; input globalreset; input clk; - reg temp_valid01; - reg temp_valid10; - reg[15:0] temp_id01a; - reg[15:0] temp_id01b; - reg[15:0] temp_id01c; - reg[15:0] temp_id10a; - reg[15:0] temp_id10b; - reg[15:0] temp_id10c; - reg temp_hit01a; - reg temp_hit01b; - reg temp_hit01c; - reg temp_hit10a; - reg temp_hit10b; - reg temp_hit10c; - reg[7:0] temp_u01a; - reg[7:0] temp_u01b; - reg[7:0] temp_u01c; - reg[7:0] temp_v01a; - reg[7:0] temp_v01b; - reg[7:0] temp_v01c; - reg[7:0] temp_u10a; - reg[7:0] temp_u10b; - reg[7:0] temp_u10c; - reg[7:0] temp_v10a; - reg[7:0] temp_v10b; - reg[7:0] temp_v10c; - - reg[2:0] state; reg[2:0] next_state; @@ -1685,29 +1999,63 @@ rgAddr <= temp_rgAddr; begin state <= next_state ; -valid01 <= temp_valid01; -valid10 <= temp_valid10; -id01a <= temp_id01a; -id01b <= temp_id01b; -id01c <= temp_id01c; -hit01a <= temp_hit01a; -hit01b <= temp_hit01b; -hit01c <= temp_hit01c; -u01a <= temp_u01a; -u01b <= temp_u01b; -u01c <= temp_u01c; -u10a <= temp_u10a; -u10b <= temp_u10b; -u10c <= temp_u10c; -v01a <= temp_v01a; -v01b <= temp_v01b; -v01c <= temp_v01c; -v10a <= temp_v10a; -v10b <= temp_v10b; -v10c <= temp_v10c; -hit10a <= temp_hit10a; -hit10b <= temp_hit10b; -hit10c <= temp_hit10c; + if (state == 0) begin + if (rgResultReady == 1'b1 & rgResultSource == 2'b01) + begin + id01a <= rgResultData[31:16] ; + id01b <= rgResultData[15:0] ; + end + else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) + begin + id10a <= rgResultData[31:16] ; + id10b <= rgResultData[15:0] ; + end + end + if (state == 1) begin + id01c <= rgResultData[15:0]; + hit01a <= rgResultData[18]; + hit01b <= rgResultData[17]; + hit01c <= rgResultData[16]; + end + if (state == 2) begin + u01a <= rgResultData[23:16]; + u01b <= rgResultData[15:8]; + u01c <= rgResultData[7:0]; + end + if (state == 5) begin + u10a <= rgResultData[23:16]; + u10b <= rgResultData[15:8]; + u10c <= rgResultData[7:0]; + end + if (state == 3) begin + v01a <= rgResultData[23:16]; + v01b <= rgResultData[15:8]; + v01c <= rgResultData[7:0]; + end + if (state == 6) begin + v10a <= rgResultData[23:16]; + v10b <= rgResultData[15:8]; + v10c <= rgResultData[7:0]; + end + if (state == 4) begin + id10c <= rgResultData[15:0] ; + hit10a <= rgResultData[18]; + hit10b <= rgResultData[17]; + hit10c <= rgResultData[16]; + end + + if (state == 3) begin + valid01 <= 1'b1; + end + else begin + valid01 <= 1'b0; + end + if (state == 6) begin + valid10 <= 1'b1; + end + else begin + valid10 <= 1'b0; + end end end @@ -1723,117 +2071,46 @@ hit10c <= temp_hit10c; end else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) begin - next_state = 4 ; end else begin next_state = 0 ; end - - - temp_valid01 = 1'b0 ; - temp_valid10 = 1'b0 ; - if (rgResultReady == 1'b1 & rgResultSource == 2'b01) - begin - temp_id01a = rgResultData[31:16] ; - temp_id01b = rgResultData[15:0] ; - end - else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) - begin - temp_id10a = rgResultData[31:16] ; - temp_id10b = rgResultData[15:0] ; - end - end 1 : begin next_state = 2 ; - - temp_valid01 = 1'b0 ; - temp_valid10 = 1'b0 ; - temp_id01c = rgResultData[15:0] ; - temp_hit01a = rgResultData[18] ; - temp_hit01b = rgResultData[17] ; - temp_hit01c = rgResultData[16] ; - end 2 : begin next_state = 3 ; - - temp_valid01 = 1'b0 ; - temp_valid10 = 1'b0 ; - temp_u01a = rgResultData[23:16] ; - temp_u01b = rgResultData[15:8] ; - temp_u01c = rgResultData[7:0] ; - end 3 : begin next_state = 0 ; - - temp_valid10 = 1'b0 ; - temp_v01a = rgResultData[23:16] ; - temp_v01b = rgResultData[15:8] ; - temp_v01c = rgResultData[7:0] ; - temp_valid01 = 1'b1 ; - end 4 : begin next_state = 5 ; - - temp_valid01 = 1'b0 ; - temp_valid10 = 1'b0 ; - temp_id10c = rgResultData[15:0] ; - - temp_hit10a = rgResultData[18] ; - temp_hit10b = rgResultData[17] ; - temp_hit10c = rgResultData[16] ; - end 5 : begin next_state = 6 ; - - temp_valid01 = 1'b0 ; - temp_valid10 = 1'b0 ; - temp_u10a = rgResultData[23:16] ; - temp_u10b = rgResultData[15:8] ; - temp_u10c = rgResultData[7:0] ; - end 6 : begin next_state = 0 ; - - temp_valid01 = 1'b0 ; - temp_v10a = rgResultData[23:16] ; - temp_v10b = rgResultData[15:8] ; - temp_v10c = rgResultData[7:0] ; - temp_valid10 = 1'b1 ; - end + default: begin + next_state = state; + end endcase end - endmodule - - - - - - - - - - - - - + endmodule module resultwriter (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, addr, as01, as10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, dataout, addrout, write, ack, globalreset, clk); From 59de2ceacda7b0c9a49d34be4b433245088d58d3 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 14:34:46 -0400 Subject: [PATCH 14/31] Fix latch elimination in raygencont --- vtr_flow/benchmarks/verilog/raygentop.v | 266 +++--------------------- 1 file changed, 26 insertions(+), 240 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index c4a9db33ab0..b02f68be1bb 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -1345,13 +1345,19 @@ rgAddr <= temp_rgAddr; begin if (active == 1'b0) begin - temp_loaded[0] = 1'b1 ; + temp_loaded[0] = 1'b1 ; + temp_loaded[1] = loaded[1]; end else begin - temp_loaded[1] = 1'b1 ; + temp_loaded[1] = 1'b1 ; + temp_loaded[0] = loaded[0]; end - end + end + else begin + temp_loaded = loaded; + end + temp_addr[1:0] = addr; temp_groupID = groupID; temp_count = count; @@ -1397,7 +1403,14 @@ rgAddr <= temp_rgAddr; temp_addr[1:0] = 2'b00 ; temp_raygroupvalid0 = raygroupvalid0; temp_raygroupvalid1 = raygroupvalid1; - end + end + else + begin + temp_addr[1:0] = addr; + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end end else begin temp_addr[1:0] = addr; @@ -1514,6 +1527,10 @@ rgAddr <= temp_rgAddr; temp_nas0 = 1'b1; temp_nas1 = 1'b1; end + else begin + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + end end 2 : begin @@ -1652,245 +1669,14 @@ rgAddr <= temp_rgAddr; next_state = 0 ; end end + // add a default to prevent latch inference + // hold previous state to preserve original design + // intent, even if this is not optimal behavior + default: + next_state = state; endcase end - /* Original below -- delete when done */ - - always @(*) - begin - case (state) - 0 : - begin - as = 1'b0 ; - wantDir = 1'b0 ; - if (go == 1'b1) - begin - next_state = 1 ; - end - else - begin - next_state = 0 ; - end - statepeek = 3'b001 ; - temp_busyout = 1'b0; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; - - - if (go == 1'b1) - begin - temp_cycles = 0; - end - temp_addr[1:0] = 2'b00 ; - temp_loaded = 2'b00 ; - temp_groupID = 2'b00 ; - temp_count = initcount ; - temp_active = 1'b0 ; - - end - 1 : - begin - as = dirReady ; - wantDir = 1'b1 ; - if (dirReady == 1'b1) - begin - next_state = 2 ; - end - else - begin - next_state = 1 ; - end - statepeek = 3'b010 ; - temp_busyout = 1'b1; - if (addr[1:0] == 2'b00 & dirReady == 1'b1 & active == 1'b0) - begin - temp_nas0 = 1'b1; - temp_nas1 = 1'b1; - end - - temp_dir = dirIn ; - if (dirReady == 1'b1 & addr[1:0] == 2'b10) - begin - if (active == 1'b0) - begin - temp_loaded[0] = 1'b1 ; - end - else - begin - temp_loaded[1] = 1'b1 ; - end - end - temp_cycles = cycles + 1 ; - - - end - 2 : - begin - wantDir = 1'b0 ; - as = 1'b1 ; - if ((ack == 1'b1) & (addr[1:0] != 2'b10)) - begin - next_state = 1 ; - end - else if (ack == 1'b1) - begin - if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) - begin - next_state = 3 ; - end - else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) - begin - next_state = 4 ; - end - else if (loaded != 2'b11) - begin - - next_state = 1 ; - end - else - begin - next_state = 2 ; - end - end - else - begin - next_state = 2 ; - end - statepeek = 3'b011 ; - temp_busyout = 1'b1; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; - - if ((ack == 1'b1) & (addr[1:0] != 2'b10)) - begin - temp_addr[1:0] = addr[1:0] + 2'b01 ; - end - else if ((ack == 1'b1) & addr[1:0] == 2'b10) - begin - if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) - begin - temp_raygroupvalid0 = 1'b1 ; - end - else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) - begin - - temp_raygroupvalid1 = 1'b1 ; - end - else if ((loaded[0]) == 1'b0) - begin - temp_active = 1'b0 ; - temp_addr[1:0] = 2'b00 ; - end - else if ((loaded[1]) == 1'b0) - begin - temp_active = 1'b1 ; - temp_addr[1:0] = 2'b00 ; - end - end - - temp_cycles = cycles + 1 ; - end - 3 : - begin - if ((busy[0]) == 1'b0) - begin - next_state = 3 ; - - end - else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) - begin - next_state = 4 ; - end - else if (count > 0) - begin - next_state = 1 ; - end - else - begin - next_state = 0 ; - - end - statepeek = 3'b100 ; - temp_busyout = 1'b1; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; - - if ((busy[0]) == 1'b1) - begin - temp_groupID[0] = ~groupID[0] ; - temp_raygroupvalid0 = 1'b0 ; - temp_count = count - 1 ; - if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) - begin - temp_raygroupvalid1 = 1'b1 ; - - end - else if ((loaded[1]) == 1'b0) - begin - temp_active = 1'b1 ; - end - else - begin - temp_active = 1'b0 ; - end - end - temp_loaded[0] = 1'b0 ; - temp_addr[1:0] = 2'b00 ; - - - temp_cycles = cycles + 1 ; - end - 4 : - begin - if ((busy[1]) == 1'b0) - begin - next_state = 4 ; - end - else if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) - begin - next_state = 3 ; - end - else if (count > 0) - begin - - next_state = 1 ; - end - else - begin - next_state = 0 ; - end - statepeek = 3'b101 ; - temp_busyout = 1'b1; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; - - if ((busy[1]) == 1'b1) - begin - temp_groupID[1] = ~groupID[1] ; - temp_raygroupvalid1 = 1'b0 ; - temp_count = count - 1 ; - if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) - begin - temp_raygroupvalid0 = 1'b1 ; - end - - else if ((loaded[0]) == 1'b0) - begin - temp_active = 1'b0 ; - end - else - begin - temp_active = 1'b1 ; - end - end - temp_loaded[1] = 1'b0 ; - temp_addr[1:0] = 2'b00 ; - - temp_cycles = cycles + 1 ; - end - endcase - end endmodule From e9d0c5ddbd9c6b66664fd3c42c8d393bcca62a0d Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 14:40:05 -0400 Subject: [PATCH 15/31] Eliminate latch inference from raysend --- vtr_flow/benchmarks/verilog/raygentop.v | 123 ++++++++++++++++++++---- 1 file changed, 102 insertions(+), 21 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index b02f68be1bb..0b43babac72 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -959,17 +959,7 @@ waddress <= temp_waddress; endmodule - - - - - - - - - - - module raysend (as, ack, addr, dir, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, clk, statepeek); + module raysend (as, ack, addr, dir, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, clk, statepeek); input as; output ack; @@ -1051,11 +1041,24 @@ rgAddr <= temp_rgAddr; temp_rgWE = 3'b001 ; temp_rgAddrValid = 1'b1 ; temp_rgAddr = addr ; - end + end + //need to hold previous value explicitly to prevent + //latch inference + else begin + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddrValid = temp_rgAddrValid; + temp_rgAddr = addr ; + end if (as == 1'b0 & ack == 1'b1) begin temp_ack = 1'b0 ; - end + end + //need to hold previous value explicitly to prevent + //latch inference + else begin + temp_ack = ack; + end end 1 : @@ -1070,11 +1073,22 @@ rgAddr <= temp_rgAddr; end statepeek = 3'b010 ; + //need to hold previous value explicitly to prevent + //latch inference + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddr = rgAddr; + if (rgDone == 1'b1) begin temp_rgAddrValid = 1'b0 ; end - + //need to hold previous value explicitly to prevent + //latch inference + else begin + temp_rgAddrValid = temp_rgAddrValid; + end + temp_ack = ack; end 2 : begin @@ -1088,11 +1102,21 @@ rgAddr <= temp_rgAddr; end statepeek = 3'b011 ; + //need to hold previous value explicitly to prevent + //latch inference + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddr = rgAddr; + if (rgDone == 1'b1) begin temp_rgAddrValid = 1'b0 ; end + else begin + temp_rgAddrValid = temp_rgAddrValid; + end + temp_ack = ack; end 3 : begin @@ -1106,11 +1130,21 @@ rgAddr <= temp_rgAddr; end statepeek = 3'b100 ; + //need to hold previous value explicitly to prevent + //latch inference + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddr = rgAddr; + if (rgDone == 1'b1) begin temp_rgAddrValid = 1'b0 ; end + else begin + temp_rgAddrValid = temp_rgAddrValid; + end + temp_ack = ack; end 4 : begin @@ -1124,10 +1158,20 @@ rgAddr <= temp_rgAddr; end statepeek = 3'b101 ; + //need to hold previous value explicitly to prevent + //latch inference + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddr = rgAddr; + if (rgDone == 1'b1) begin temp_rgAddrValid = 1'b0 ; end + else begin + temp_rgAddrValid = temp_rgAddrValid; + end + temp_ack = ack; end 5 : @@ -1142,11 +1186,20 @@ rgAddr <= temp_rgAddr; end statepeek = 3'b110 ; + //need to hold previous value explicitly to prevent + //latch inference + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddr = rgAddr; + temp_ack = 1'b1 ; if (rgDone == 1'b1) begin temp_rgAddrValid = 1'b0 ; end + else begin + temp_rgAddrValid = temp_rgAddrValid; + end end @@ -1154,6 +1207,11 @@ rgAddr <= temp_rgAddr; begin next_state = 2 ; + //need to hold previous value explicitly to prevent + //latch inference + temp_rgAddr = rgAddr; + temp_ack = ack; + temp_rgData = {4'b0000, origy} ; temp_rgWE = 3'b010 ; temp_rgAddrValid = 1'b1 ; @@ -1163,6 +1221,11 @@ rgAddr <= temp_rgAddr; begin next_state = 3 ; + //need to hold previous value explicitly to prevent + //latch inference + temp_rgAddr = rgAddr; + temp_ack = ack; + temp_rgData = {4'b0000, origz} ; temp_rgWE = 3'b011 ; temp_rgAddrValid = 1'b1 ; @@ -1171,6 +1234,11 @@ rgAddr <= temp_rgAddr; begin next_state = 4 ; + //need to hold previous value explicitly to prevent + //latch inference + temp_rgAddr = rgAddr; + temp_ack = ack; + temp_rgData = {dir[31:16], dir[47:32]} ; temp_rgWE = 3'b100 ; temp_rgAddrValid = 1'b1 ; @@ -1179,19 +1247,32 @@ rgAddr <= temp_rgAddr; begin next_state = 5 ; + //need to hold previous value explicitly to prevent + //latch inference + temp_rgAddr = rgAddr; + temp_ack = ack; + temp_rgData = {16'b0000000000000000, dir[15:0]} ; temp_rgWE = 3'b101 ; temp_rgAddrValid = 1'b1 ; end + // The original FSM did not have a default case. We want to add one + // to prevent modern synthesis tools from inferring latches in this + // logic. To preserve as much of the original behavior as possible, + // hold the previous flop values whereever possible, even though + // this will cause the FSM to lock up if it gets in an illegal state + default: begin + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddrValid = rgAddrValid; + temp_rgAddr = rgAddr; + temp_ack = ack; + next_state = state; + end endcase end - endmodule - - - - - - + endmodule + module raygencont (go, initcount, busyout, cycles, nextaddr, nas0, nas1, page, dirReady, wantDir, dirIn, addrIn, as, addr, ack, dir, raygroup0, raygroupvalid0, busy0, raygroup1, raygroupvalid1, busy1, globalreset, clk, statepeek); From e14f327cdee4e3eeda248c29c92eabf095f45d42 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 15:02:19 -0400 Subject: [PATCH 16/31] Eliminate latch inference from sram control --- vtr_flow/benchmarks/verilog/raygentop.v | 703 ++++++++++++++---------- 1 file changed, 412 insertions(+), 291 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index 0b43babac72..b67e3cfe077 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -635,327 +635,448 @@ module rgsramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, d fbdata <= tm3_sram_data_in ; fbdatavalid <= fbdatavalidl ; -fbdatavalidl <= temp_fbdatavalidl; -texelready <= temp_texelready; -shadedataready <= temp_shadedataready; -fcount <= temp_fcount; -faddress <= temp_faddress; -waddress <= temp_waddress; + fbdatavalidl <= temp_fbdatavalidl; + texelready <= temp_texelready; + shadedataready <= temp_shadedataready; + fcount <= temp_fcount; + faddress <= temp_faddress; + waddress <= temp_waddress; end end - always @(*) - begin - case (state) + always @(*) + begin + case (state) 0 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - if (addr_ready == 1'b1) - begin - next_state = 1 ; - end - else if (want_read == 1'b1) - begin - next_state = 2 ; - end - else if (data_ready == 1'b1) - begin + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (addr_ready == 1'b1) - next_state = 3 ; - end - else if (wantDir == 1'b1) - begin - next_state = 5 ; - end - else if (wantwriteback == 1'b1) - begin - next_state = 6 ; - end - else if (wantshadedata == 1'b1) - begin + begin + temp_waddress = addrin ; + end + else begin + temp_waddress = waddress; + end + temp_faddress = faddress; + temp_fcount = fcount; + + end + 1 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b0 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = fbdatavalidl; + temp_shadedataready = shadedataready; + temp_texelready = texelready; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + + end + 2 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b0 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (want_read == 1'b0) + begin - next_state = 9 ; - end - else if (wanttexel == 1'b1) - begin - next_state = 10 ; - end - else if (fcount != 0) - begin - next_state = 7 ; - end - else if (fbnextscanline == 1'b1) - begin + temp_waddress = waddress + 1 ; + end + else begin + temp_waddress = waddress; + end + temp_faddress = faddress; + temp_fcount = fcount; + end + 3 : + begin + tm3_sram_we = 8'b00000000 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = datain ; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_waddress = waddress + 1 ; + temp_faddress = faddress; + temp_fcount = fcount; - next_state = 8 ; - end - else - begin - next_state = 0 ; - end - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - if (addr_ready == 1'b1) + end + 4 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = fbdatavalidl; + temp_shadedataready = shadedataready; + temp_texelready = texelready; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + end - begin - temp_waddress = addrin ; - end + 5 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b1 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (wantDir == 1'b0) + begin + temp_waddress = waddress + 1 ; + end + else begin + temp_waddress = waddress; + end + temp_faddress = faddress; + temp_fcount = fcount; + end + 6 : + begin + tm3_sram_we = 8'b00000000 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = writebackdata ; + tm3_sram_addr = {1'b0, writebackaddr} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b1 ; + + temp_fbdatavalidl = fbdatavalidl; + temp_shadedataready = shadedataready; + temp_texelready = texelready; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + end - end - 1 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - want_addr = 1'b0 ; - if (addr_ready == 1'b0) - begin - next_state = 0 ; + 7 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {3'b011, fbpage, faddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_fbdatavalidl = 1'b1 ; + temp_waddress = waddress; + if (fcount != 0) + begin + temp_faddress = faddress + 1 ; + temp_fcount = fcount - 1 ; + end + else begin + temp_faddress = faddress; + temp_fcount = fcount; + end + end + 8 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_waddress = waddress; + temp_fcount = 7'b1101011 ; + if (faddress == 25680) + begin + temp_faddress = 0; + end + else begin + temp_faddress = faddress; + end + end + 9 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {3'b010, triID} ; + + temp_fbdatavalidl = 1'b0 ; + temp_texelready = 1'b0 ; + temp_shadedataready = 1'b1 ; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + end - end - else - begin - next_state = 1 ; - end - end - 2 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - - read_ready = 1'b0 ; - if (want_read == 1'b0) - begin - next_state = 0 ; - end - else - begin - next_state = 2 ; - end + 10 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {1'b0, texeladdr} ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b1 ; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + end + // Create a default case to avoid inferring latches. + // for temp_* variables we can hold previous state to + // preserve design intent. For variables that are + // not re-registered, we must make a choice about + // what the default behavior should be that will + // potentially change functionality vs. previous revision + // for previously undefined state decoding. Make a best + // effort based on how the signals appear to idle when + // not being used by the FSM by matching state 0 + default: begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = fbdatavalidl; + temp_shadedataready = shadedataready; + temp_texelready = texelready; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + end + endcase + end - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - if (want_read == 1'b0) - begin + always @(*) + begin + case (state) + 0 : + begin + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else if (want_read == 1'b1) + begin + next_state = 2 ; + end + else if (data_ready == 1'b1) + begin - temp_waddress = waddress + 1 ; - end + next_state = 3 ; + end + else if (wantDir == 1'b1) + begin + next_state = 5 ; + end + else if (wantwriteback == 1'b1) + begin + next_state = 6 ; + end + else if (wantshadedata == 1'b1) + begin - end - 3 : - begin - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - tm3_sram_data_xhdl0 = datain ; - tm3_sram_we = 8'b00000000 ; - - - tm3_sram_oe = 2'b11 ; - tm3_sram_adsp = 1'b0 ; - want_data = 1'b0 ; - next_state = 4 ; + next_state = 9 ; + end + else if (wanttexel == 1'b1) + begin + next_state = 10 ; + end + else if (fcount != 0) + begin + next_state = 7 ; + end + else if (fbnextscanline == 1'b1) + begin - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - temp_waddress = waddress + 1 ; + next_state = 8 ; + end + else + begin + next_state = 0 ; + end + end + 1 : + begin + if (addr_ready == 1'b0) + begin + next_state = 0 ; - end + end + else + begin + next_state = 1 ; + end + end + 2 : + begin + if (want_read == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + end + end + 3 : + begin + next_state = 4 ; + end 4 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - if (data_ready == 1'b0) - begin - - next_state = 0 ; - end - else - begin - next_state = 4 ; - end - want_data = 1'b0 ; - end + begin + if (data_ready == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 4 ; + end + end 5 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - writebackack = 1'b0 ; - - dirReady = 1'b1 ; - if (wantDir == 1'b0) - begin - next_state = 0 ; - - end - else - begin - next_state = 5 ; - end - - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - if (wantDir == 1'b0) - begin - temp_waddress = waddress + 1 ; - end + begin + if (wantDir == 1'b0) + begin + next_state = 0 ; - end + end + else + begin + next_state = 5 ; + end + end 6 : - begin - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - - tm3_sram_data_xhdl0 = writebackdata ; - tm3_sram_we = 8'b00000000 ; - tm3_sram_oe = 2'b11 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_addr = {1'b0, writebackaddr} ; - writebackack = 1'b1 ; - next_state = 0 ; - end + begin + next_state = 0 ; + end 7 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - tm3_sram_addr = {3'b011, fbpage, faddress} ; - if ((fcount == 1) | (addr_ready == 1'b1) | (want_read == 1'b1) | (data_ready == 1'b1) | (wantDir == 1'b1) | (wantwriteback == 1'b1)) - begin - next_state = 0 ; - - end - else - begin - next_state = 7 ; - end - - - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - temp_fbdatavalidl = 1'b1 ; - if (fcount != 0) - begin - temp_faddress = faddress + 1 ; - temp_fcount = fcount - 1 ; - end + begin + if ((fcount == 1) | (addr_ready == 1'b1) | (want_read == 1'b1) | (data_ready == 1'b1) | (wantDir == 1'b1) | (wantwriteback == 1'b1)) + begin + next_state = 0 ; - end + end + else + begin + next_state = 7 ; + end + end 8 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - next_state = 7 ; - - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - temp_fcount = 7'b1101011 ; - if (faddress == 25680) - begin - temp_faddress = 0; - end - end + begin + next_state = 7 ; + end 9 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - tm3_sram_addr = {3'b010, triID} ; - next_state = 0 ; - - temp_fbdatavalidl = 1'b0 ; - temp_texelready = 1'b0 ; - temp_shadedataready = 1'b1 ; - end + begin + next_state = 0 ; + end 10 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - tm3_sram_addr = {1'b0, texeladdr} ; - next_state = 0 ; + begin + next_state = 0 ; + end + // Add a default to avoid inferring latches. Preserve original functionality + // by holding previous state, even if this is suboptimal for real circuits: + default: begin + next_state = state; + end + endcase + end - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b1 ; - end - endcase - end endmodule From f29e6ae70ac504881efa91dabd5424f248786b2e Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 15:08:11 -0400 Subject: [PATCH 17/31] Eliminate latch inference from onlyoneccycle; all latch inference now eliminated --- vtr_flow/benchmarks/verilog/raygentop.v | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index b67e3cfe077..dfe69df3ff4 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -252,7 +252,7 @@ module delay1x3 (datain, dataout, clk); case (state) 0 : begin - output_xhdl0 = 1'b0 ; + output_xhdl0 = 1'b0 ; if (trigger == 1'b1) begin next_state = 1 ; @@ -280,7 +280,7 @@ module delay1x3 (datain, dataout, clk); end 2 : begin - output_xhdl0 = 1'b0 ; + output_xhdl0 = 1'b0 ; if (trigger == 1'b0) begin next_state = 0 ; @@ -289,8 +289,23 @@ module delay1x3 (datain, dataout, clk); begin next_state = 2 ; - end + end + temp_count = count; end + // Create a default case to avoid inferring latches. + // Preserve original behavior by holding state, even if + // this is suboptimal for real designs + default: begin + //Note that output_xhdl is combinational and drives + //a top level signal called go. To eliminate inferred + //latch for it, default it to zero here to hypothetically + //make sure that go is not asserted when the FSM goes + //awry + output_xhdl0 = 1'b0; + + next_state = state; + temp_count = count; + end endcase end endmodule From 65a1d0ecb59d1adab6f3dea0cee330cad107feba Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 8 Aug 2025 15:22:42 -0400 Subject: [PATCH 18/31] Fix typos --- vtr_flow/benchmarks/verilog/raygentop.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index dfe69df3ff4..f3cbad59469 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -1183,7 +1183,7 @@ rgAddr <= temp_rgAddr; else begin temp_rgData = rgData; temp_rgWE = rgWE; - temp_rgAddrValid = temp_rgAddrValid; + temp_rgAddrValid = rgAddrValid; temp_rgAddr = addr ; end if (as == 1'b0 & ack == 1'b1) @@ -1222,7 +1222,7 @@ rgAddr <= temp_rgAddr; //need to hold previous value explicitly to prevent //latch inference else begin - temp_rgAddrValid = temp_rgAddrValid; + temp_rgAddrValid = rgAddrValid; end temp_ack = ack; end @@ -1249,7 +1249,7 @@ rgAddr <= temp_rgAddr; temp_rgAddrValid = 1'b0 ; end else begin - temp_rgAddrValid = temp_rgAddrValid; + temp_rgAddrValid = rgAddrValid; end temp_ack = ack; @@ -1277,7 +1277,7 @@ rgAddr <= temp_rgAddr; temp_rgAddrValid = 1'b0 ; end else begin - temp_rgAddrValid = temp_rgAddrValid; + temp_rgAddrValid = rgAddrValid; end temp_ack = ack; @@ -1305,7 +1305,7 @@ rgAddr <= temp_rgAddr; temp_rgAddrValid = 1'b0 ; end else begin - temp_rgAddrValid = temp_rgAddrValid; + temp_rgAddrValid = rgAddrValid; end temp_ack = ack; end @@ -1334,7 +1334,7 @@ rgAddr <= temp_rgAddr; temp_rgAddrValid = 1'b0 ; end else begin - temp_rgAddrValid = temp_rgAddrValid; + temp_rgAddrValid = rgAddrValid; end end From 08a9d3c93fee98bcef6ee4dff4939a512f9202a3 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Tue, 26 Aug 2025 15:30:20 -0400 Subject: [PATCH 19/31] Refactor listhandler to eliminate latches --- vtr_flow/benchmarks/verilog/boundtop.v | 602 +++++++++++++++---------- 1 file changed, 364 insertions(+), 238 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index 8ba03ee12de..da37c6036c5 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -2471,7 +2471,7 @@ module listhandler (dataarrayin, commit, hitmask, ack, boundnodeID, level, empty reg[2:0] offset1; reg[2:0] offset2; reg[4:0] address; - reg we; + wire we; reg[12:0] datain; wire[12:0] dataout; reg[2:0] lvempty; @@ -2501,264 +2501,390 @@ module listhandler (dataarrayin, commit, hitmask, ack, boundnodeID, level, empty assign empty = (lvempty == 3'b111 & busy == 1'b0) ? 1'b1 : 1'b0 ; assign dataready = ((((dataout[10]) == 1'b1 & (hitmask[0]) == 1'b1) | ((dataout[11]) == 1'b1 & (hitmask[1]) == 1'b1) | ((dataout[12]) == 1'b1 & (hitmask[2]) == 1'b1)) & (empty == 1'b0) & (busy == 1'b0)) ? 1'b1 : 1'b0 ; - always @(*) - begin - address[4:3] = readlevel ; - - if (address[4:3] == 2'b00) - begin - address[2:0] = offset0 ; - end - else if (address[4:3] == 2'b01) - begin - - address[2:0] = offset1 ; - end - else if (address[4:3] == 2'b10) - begin - address[2:0] = offset2 ; - end - else - begin - address[2:0] = 0; - end - end + always @(*) + begin + address[4:3] = readlevel ; - always @(posedge clk) - begin - if (globalreset == 1'b1) - begin - state <= 0 ; - lvempty <= 1; - busy <= 1'b0 ; - readlevel <= 2'b00 ; - writelevel <= 2'b00 ; - offset0 <= 3'b000 ; - offset1 <= 3'b000 ; - offset2 <= 3'b000 ; + if (address[4:3] == 2'b00) + begin + address[2:0] = offset0 ; + end + else if (address[4:3] == 2'b01) + begin - end - else - begin - state <= next_state ; - peekstate <= temp_peekstate ; - busy <= temp_busy; - lvempty <= temp_lvempty; - readlevel <= temp_readlevel; - writelevel <= temp_writelevel; - offset0 <= temp_offset0; - offset1 <= temp_offset1; - offset2 <= temp_offset2; + address[2:0] = offset1 ; + end + else if (address[4:3] == 2'b10) + begin + address[2:0] = offset2 ; + end + else + begin + address[2:0] = 0; + end + end - end - end + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + lvempty <= 1; + busy <= 1'b0 ; + readlevel <= 2'b00 ; + writelevel <= 2'b00 ; + offset0 <= 3'b000 ; + offset1 <= 3'b000 ; + offset2 <= 3'b000 ; - always @(*) - begin + end + else + begin + state <= next_state ; + peekstate <= temp_peekstate ; + busy <= temp_busy; + lvempty <= temp_lvempty; + readlevel <= temp_readlevel; + writelevel <= temp_writelevel; + offset0 <= temp_offset0; + offset1 <= temp_offset1; + offset2 <= temp_offset2; + end + end - case (state) + //for we and datain we cannot preserve original functionality and stil + //eliminate latches because there were no flops for them in the original + //code. The best we can do is observe that nonzero, valid behavior + //is defined only when state == 2'b01. Since putting these behind flops + //would change their timing, build a mux and set we and datain to zero + //for previously undefined states + assign we = (state == 2'b01); + always @(*) begin + if (state == 2'b01) begin + case(address[2:0]) + 2'b000: datain = dataarrayin[0+:13]; + 2'b001: datain = dataarrayin[13+:13]; + 2'b010: datain = dataarrayin[26+:13]; + 2'b011: datain = dataarrayin[39+:13]; + 2'b100: datain = dataarrayin[52+:13]; + 2'b101: datain = dataarrayin[65+:13]; + 2'b110: datain = dataarrayin[78+:13]; + 2'b111: datain = dataarrayin[91+:13]; + endcase + end + else begin + datain = 'h0; + end + end + + always @(*) + begin + + // Note that throughout this case statement it is necessary to + // add else statements that were not previously present in order + // to prevent latch inference. To preserve previous behavior, + // these else statements should always set the value equal to + // previous state + case (state) 2'b00 : - begin - we = 1'b0 ; - datain = 0; - if (reset == 1'b1) + begin + temp_peekstate = 2'b01 ; + + if (reset == 1'b1) + begin + temp_busy = 1'b0 ; + temp_lvempty = 1; + temp_readlevel = 2'b00 ; + + temp_writelevel = 2'b00 ; + temp_offset0 = 3'b000 ; + temp_offset1 = 3'b000 ; + temp_offset2 = 3'b000 ; + end + else if (commit == 1'b1) + begin + temp_busy = 1'b1 ; + if (writelevel == 2'b00) begin - next_state = 0 ; - end - else if (commit == 1'b1) - begin - next_state = 1 ; + temp_offset0 = 3'b000 ; + temp_offset1 = offset1; + temp_offset2 = offset2; end - else if ((ack == 1'b1) | (dataready == 1'b0 & empty == 1'b0)) + else if (writelevel == 2'b01) begin - next_state = 2 ; + temp_offset1 = 3'b000 ; + temp_offset0 = offset0; + temp_offset2 = offset2; end - else + else if (writelevel == 2'b10) begin - next_state = 0 ; - end - temp_peekstate = 2'b01 ; - - if (reset == 1'b1) - begin - temp_busy = 1'b0 ; - temp_lvempty = 1; - temp_readlevel = 2'b00 ; - - temp_writelevel = 2'b00 ; - temp_offset0 = 3'b000 ; - temp_offset1 = 3'b000 ; - temp_offset2 = 3'b000 ; - end - else if (commit == 1'b1) - begin - temp_busy = 1'b1 ; - if (writelevel == 2'b00) - begin - temp_offset0 = 3'b000 ; - end - - else if (writelevel == 2'b01) - begin - temp_offset1 = 3'b000 ; - end - else if (writelevel == 2'b10) - begin - temp_offset2 = 3'b000 ; - end - temp_readlevel = writelevel ; - end - - else if (ack == 1'b1) - begin - temp_writelevel = readlevel + 1 ; - temp_busy = 1'b1 ; // This will ensure that align skips one - end - - end + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = 3'b000 ; + end + else begin + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + temp_readlevel = writelevel ; + temp_writelevel = writelevel; + temp_lvempty = lvempty; + end + + else if (ack == 1'b1) + begin + temp_writelevel = readlevel + 1 ; + temp_readlevel = readlevel; + temp_busy = 1'b1 ; // This will ensure that align skips one + temp_lvempty = lvempty; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + else begin + temp_busy = busy; + temp_lvempty = lvempty; + temp_readlevel = readlevel; + temp_writelevel = writelevel; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + temp_readlevel = readlevel; + temp_writelevel = writelevel; + end + end 2'b01 : - begin -/* PAJ -- Unrolled loop */ - if (address[2:0] == 0) - begin - datain = dataarrayin[(1) * 13 - 1:0 * 13] ; - end - else if ( address[2:0] == 1) - begin - datain = dataarrayin[(2) * 13 - 1:1 * 13] ; - end - else if ( address[2:0] ==2) - begin - datain = dataarrayin[(3) * 13 - 1:2 * 13] ; - end - else if ( address[2:0] ==3) - begin - datain = dataarrayin[(4) * 13 - 1:3 * 13] ; - end - else if ( address[2:0] ==4) - begin - datain = dataarrayin[(5) * 13 - 1:4 * 13] ; - end - else if ( address[2:0] ==5) - begin - datain = dataarrayin[(6) * 13 - 1:5 * 13] ; - end - else if ( address[2:0] ==6) - begin - datain = dataarrayin[(7) * 13 - 1:6 * 13] ; - end - else if ( address[2:0] ==7) - begin - datain = dataarrayin[(8) * 13 - 1:7 * 13] ; - end - - - we = 1'b1 ; - if (address[2:0] == 3'b111) + begin + temp_peekstate = 2'b10 ; + + if (readlevel == 2'b00) + begin + temp_offset0 = offset0 + 1 ; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + else if (readlevel == 2'b01) + begin + temp_offset1 = offset1 + 1 ; + temp_offset0 = offset0; + temp_offset2 = offset2; + end + else if (readlevel == 2'b10) + begin + temp_offset2 = offset2 + 1 ; + temp_offset0 = offset0; + temp_offset1 = offset1; + end + else + begin + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + + if (address[2:0] == 3'b111) + begin + temp_busy = 1'b0 ; + end + else begin + temp_busy = busy; + end + + if ((datain[10]) == 1'b1 | (datain[11]) == 1'b1 | (datain[12]) == 1'b1) + begin + if (readlevel == 2'b00) begin - next_state = 2 ; - + temp_lvempty[0] = 1'b0 ; + temp_lvempty[1] = lvempty[1] ; + temp_lvempty[2] = lvempty[2] ; end - else + else if (readlevel == 2'b01) begin - next_state = 1 ; - end - temp_peekstate = 2'b10 ; - - if (readlevel == 2'b00) - begin - temp_offset0 = offset0 + 1 ; - end - - else if (readlevel == 2'b01) - begin - temp_offset1 = offset1 + 1 ; - end - else if (readlevel == 2'b10) - begin - temp_offset2 = offset2 + 1 ; - end - if (address[2:0] == 3'b111) - begin - temp_busy = 1'b0 ; - end - - if ((datain[10]) == 1'b1 | (datain[11]) == 1'b1 | (datain[12]) == 1'b1) - begin - if (readlevel == 2'b00) - begin - temp_lvempty[0] = 1'b0 ; - end - else if (readlevel == 2'b01) - begin - temp_lvempty[1] = 1'b0 ; - end - else if (readlevel == 2'b10) - begin - - temp_lvempty[2] = 1'b0 ; - end - end - - end + temp_lvempty[1] = 1'b0 ; + temp_lvempty[0] = lvempty[0] ; + temp_lvempty[2] = lvempty[2] ; + end + else if (readlevel == 2'b10) + begin + temp_lvempty[2] = 1'b0 ; + temp_lvempty[0] = lvempty[0] ; + temp_lvempty[1] = lvempty[1] ; + end + else begin + temp_lvempty = lvempty; + end + end + else begin + temp_lvempty = lvempty; + end + + temp_readlevel = readlevel; + temp_writelevel = writelevel; + + end 2'b10 : - begin - if (empty == 1'b0 & dataready == 1'b0) - begin - next_state = 2 ; - end - else - next_state = 0 ; - - temp_peekstate = 2'b11 ; - temp_busy = 1'b0 ; - if (empty == 1'b0 & dataready == 1'b0) - begin - if (readlevel == 2'b00) - begin - if (offset0 == 3'b111) - begin - temp_lvempty[0] = 1'b1 ; - end - else - begin - temp_offset0 = offset0 + 1 ; - end - end - else if (readlevel == 2'b01) - begin - if (offset1 == 3'b111) + begin + if (empty == 1'b0 & dataready == 1'b0) + temp_peekstate = 2'b11 ; + else + temp_peekstate = peekstate; + + temp_busy = 1'b0 ; + + if (empty == 1'b0 & dataready == 1'b0) + begin + if (readlevel == 2'b00) + begin + if (offset0 == 3'b111) + begin + temp_lvempty[0] = 1'b1 ; + temp_lvempty[1] = lvempty[1]; + temp_lvempty[2] = lvempty[2]; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + else + begin + temp_lvempty = lvempty; + temp_offset0 = offset0 + 1 ; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + temp_readlevel = readlevel; + temp_writelevel = writelevel; + end + else if (readlevel == 2'b01) + begin + if (offset1 == 3'b111) + begin + temp_lvempty[1] = 1'b1 ; + temp_lvempty[0] = lvempty[0]; + temp_lvempty[2] = lvempty[2]; + temp_readlevel = 2'b00 ; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + else + begin + temp_offset1 = offset1 + 1 ; + temp_offset0 = offset0; + temp_offset2 = offset2; + temp_lvempty = lvempty; + temp_readlevel = readlevel; + end + temp_writelevel = writelevel; + end + else if (readlevel == 2'b10) + begin + if (offset2 == 3'b111) + begin + temp_lvempty[2] = 1'b1 ; + temp_lvempty[1:0] = lvempty[1:0]; + if ((lvempty[1]) == 1'b1) begin - temp_lvempty[1] = 1'b1 ; - temp_readlevel = 2'b00 ; + temp_readlevel = 2'b00 ; end - else + else begin - temp_offset1 = offset1 + 1 ; - end - end - else if (readlevel == 2'b10) - begin - if (offset2 == 3'b111) - begin - temp_lvempty[2] = 1'b1 ; - if ((lvempty[1]) == 1'b1) - begin - temp_readlevel = 2'b00 ; - end - else - begin - temp_readlevel = 2'b01 ; - end + temp_readlevel = 2'b01 ; end - else - begin - temp_offset2 = offset2 + 1 ; - end - end - end - end + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + else + begin + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2 + 1 ; + temp_lvempty = lvempty; + temp_readlevel = readlevel; + end + temp_writelevel = writelevel; + end + else + begin + temp_lvempty = lvempty; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + temp_readlevel = readlevel; + temp_writelevel = writelevel; + end + end + else + begin + temp_lvempty = lvempty; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + temp_readlevel = readlevel; + temp_writelevel = writelevel; + end + end + default: begin + // preserve original design intent by holding state, even if + // this behavior is not really sensical + temp_peekstate = peekstate ; + temp_busy = busy; + temp_lvempty = lvempty; + temp_readlevel = readlevel; + temp_writelevel = writelevel; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + endcase + + case (state) + 2'b00 : + begin + if (reset == 1'b1) + begin + next_state = 0 ; + end + else if (commit == 1'b1) + begin + next_state = 1 ; + end + else if ((ack == 1'b1) | (dataready == 1'b0 & empty == 1'b0)) + begin + next_state = 2 ; + end + else + begin + next_state = 0 ; + end + end + 2'b01 : + begin + if (address[2:0] == 3'b111) + begin + next_state = 2 ; + end + else + begin + next_state = 1 ; + end + end + 2'b10 : + begin + if (empty == 1'b0 & dataready == 1'b0) + begin + next_state = 2 ; + end + else + next_state = 0 ; + end + default: begin + // preserve original design intent by holding state, even if + // this behavior is not really sensical + next_state = state; + end endcase end endmodule From a0a97297a91dc88c07ab0175a6c7b13a817f9efb Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Tue, 26 Aug 2025 15:56:45 -0400 Subject: [PATCH 20/31] Refactor resulttransmit to eliminate latches --- vtr_flow/benchmarks/verilog/boundtop.v | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index da37c6036c5..e31ff819d74 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -424,6 +424,9 @@ reg[31:0] temp_rgResultData; begin next_state = 0 ; end + temp_rgResultReady = rgResultReady; + temp_rgResultData = rgResultData; + temp_rgResultSource = rgResultSource; end 1 : begin @@ -482,10 +485,13 @@ reg[31:0] temp_rgResultData; temp_rgResultReady = 1'b0 ; temp_rgResultSource = 2'b10 ; end - default: - begin - temp_rgResultReady = u01a || u01b || u01c || v01a || v01b || v01c || u10a || u10b || u10c || v10a || v10b || v10c; - end + default: + begin + next_state = state; + temp_rgResultReady = u01a || u01b || u01c || v01a || v01b || v01c || u10a || u10b || u10c || v10a || v10b || v10c; + temp_rgResultData = rgResultData; + temp_rgResultSource = rgResultSource; + end endcase end endmodule @@ -778,10 +784,8 @@ module boundcontroller (raygroupout, raygroupwe, raygroupid, enablenear, raygrou end end - - always @* - begin + begin case (state) 0 : begin From 7559f16c0206f9efe650ef9c9ce95a358dd29359 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Tue, 26 Aug 2025 15:57:18 -0400 Subject: [PATCH 21/31] Add default values to next state logic in boundcontroller --- vtr_flow/benchmarks/verilog/boundtop.v | 44 +++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index e31ff819d74..32a41fb08b1 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -784,8 +784,50 @@ module boundcontroller (raygroupout, raygroupwe, raygroupid, enablenear, raygrou end end + // Refactoring this with better style like resulttransmit and listhandler blocks would be very + // time consuming, so instead apply an old trick where we initialize the value to previous state and + // then let the case statement simply superimpose updates on top of that. always @* - begin + begin + next_state = state ; + temp_busy = busy; + temp_statepeek = statepeek; + temp_raygroupoutl = raygroupoutl ; + temp_cts = cts ; + temp_passCTSout = passCTSout ; + temp_resetcount = resetcount ; + temp_l0reset = l0reset ; + temp_addr = addr ; + temp_startAddr = startAddr ; + temp_boundNodeIDout = boundNodeIDout ; + temp_baseaddress = baseaddress ; + temp_hitmask = hitmask ; + temp_hit1 = hit1 ; + temp_hit2 = hit2 ; + temp_hit3 = hit3 ; + temp_triIDvalid = triIDvalid ; + temp_triID = triID ; + temp_lack = lack ; + temp_addrind = addrind ; + temp_addrindvalid = addrindvalid ; + temp_tladdr = tladdr ; + temp_tladdrvalid = tladdrvalid ; + temp_count = count ; + temp_subcount = subcount ; + temp_maskcount = maskcount ; + temp_triDatalatch = triDatalatch ; + temp_t1 = t1 ; + temp_u1 = u1 ; + temp_v1 = v1 ; + temp_id1 = id1 ; + temp_t2 = t2 ; + temp_u2 = u2 ; + temp_v2 = v2 ; + temp_id2 = id2 ; + temp_t3 = t3 ; + temp_u3 = u3 ; + temp_v3 = v3 ; + temp_id3 = id3 ; case (state) 0 : begin From ea656cbd19caaf09fbb9d7fc82e84fcc0768aeea Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Tue, 26 Aug 2025 16:01:00 -0400 Subject: [PATCH 22/31] Add default values to next state logic in resultinterface --- vtr_flow/benchmarks/verilog/boundtop.v | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index 32a41fb08b1..12565ddba8c 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -2059,7 +2059,25 @@ module resultinterface (t1b, t2b, t3b, u1b, u2b, u3b, v1b, v2b, v3b, id1b, id2b, end always @(*) - begin + begin + next_state = state ; + temp_t1b = t1b; + temp_newdata = newdata; + temp_u1b = u1b; + temp_v1b = v1b; + temp_id1b = id1b; + temp_hit1b = hit1b; + temp_resultID = resultID; + temp_t2b = t2b; + temp_u2b = u2b; + temp_id2b = id2b; + temp_t3b = t3b; + temp_u3b = u3b; + temp_v3b = v3b; + temp_id3b = id3b; + temp_hit3b = hit3b; + temp_v2b = v2b; + temp_hit2b = hit2b; case (state) 0 : begin From 48dcce990b6cb53d3ae1c960d9b863348ff7978b Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Tue, 26 Aug 2025 16:06:52 -0400 Subject: [PATCH 23/31] Add default values to state decode in sramcontroller --- vtr_flow/benchmarks/verilog/boundtop.v | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index 12565ddba8c..a1dbc22e771 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -1785,7 +1785,23 @@ new_ram( end always @(*) - begin + begin + next_state = state; + temp_statepeek = statepeek; + temp_data = data; + temp_datavalid = datavalid; + temp_waddress = waddress; + // For the unregistered values, we have to pick default behavior; + // these values are used in enough other defined states to appear to + // be reasonable fallbacks, but putting this here does change design + // intent: + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; case (state) 0 : begin From 5fbee52f8c1050b2b75e0ca6e9d3597e3018db04 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Tue, 26 Aug 2025 16:11:37 -0400 Subject: [PATCH 24/31] Eliminate latches in vblockramcontroller --- vtr_flow/benchmarks/verilog/boundtop.v | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index a1dbc22e771..c55dc77b3c1 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -1561,7 +1561,18 @@ reg temp_datavalid; always @(*) - begin + begin + next_state = state; + temp_data = data; + temp_waddr = waddr; + temp_datavalid = datavalid; + // For the unregistered values, we have to pick default behavior; + // these values are used in enough other defined states to appear to + // be reasonable fallbacks, but putting this here does change design + // intent: + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; case (state) 0 : begin From 6b5e2eefaa5945aab9cdf7ea8d299efb5ed21a2c Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Tue, 26 Aug 2025 16:14:19 -0400 Subject: [PATCH 25/31] Second pass cleaning up boundcontroller --- vtr_flow/benchmarks/verilog/boundtop.v | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index c55dc77b3c1..3ced537ddd6 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -828,6 +828,15 @@ module boundcontroller (raygroupout, raygroupwe, raygroupid, enablenear, raygrou temp_u3 = u3 ; temp_v3 = v3 ; temp_id3 = id3 ; + // For the unregistered values, we have to pick default behavior; + // these values are used in enough other defined states to appear to + // be reasonable fallbacks, but putting this here does change design + // intent: + raygroupid = 0; + enablenear = 1'b0 ; + raygroupwe = 1'b0 ; + bcvalid = 1'b0 ; + lhreset = 1'b1 ; case (state) 0 : begin From 982ef4779b3f12ee376331dd1f27afd239f5e067 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Tue, 26 Aug 2025 16:21:23 -0400 Subject: [PATCH 26/31] Bugfix datain mux --- vtr_flow/benchmarks/verilog/boundtop.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index 3ced537ddd6..bac522503f9 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -2662,14 +2662,14 @@ module listhandler (dataarrayin, commit, hitmask, ack, boundnodeID, level, empty always @(*) begin if (state == 2'b01) begin case(address[2:0]) - 2'b000: datain = dataarrayin[0+:13]; - 2'b001: datain = dataarrayin[13+:13]; - 2'b010: datain = dataarrayin[26+:13]; - 2'b011: datain = dataarrayin[39+:13]; - 2'b100: datain = dataarrayin[52+:13]; - 2'b101: datain = dataarrayin[65+:13]; - 2'b110: datain = dataarrayin[78+:13]; - 2'b111: datain = dataarrayin[91+:13]; + 3'b000: datain = dataarrayin[0+:13]; + 3'b001: datain = dataarrayin[13+:13]; + 3'b010: datain = dataarrayin[26+:13]; + 3'b011: datain = dataarrayin[39+:13]; + 3'b100: datain = dataarrayin[52+:13]; + 3'b101: datain = dataarrayin[65+:13]; + 3'b110: datain = dataarrayin[78+:13]; + 3'b111: datain = dataarrayin[91+:13]; endcase end else begin From eacf45ff9fbff280a2eea70f2b3199762f27b92a Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Tue, 26 Aug 2025 17:08:51 -0400 Subject: [PATCH 27/31] Add default case statement to eliminate latches --- vtr_flow/benchmarks/verilog/stereovision3.v | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/vtr_flow/benchmarks/verilog/stereovision3.v b/vtr_flow/benchmarks/verilog/stereovision3.v index c45692e2a80..d9de7d979b8 100755 --- a/vtr_flow/benchmarks/verilog/stereovision3.v +++ b/vtr_flow/benchmarks/verilog/stereovision3.v @@ -1016,6 +1016,13 @@ module sv_chip3_hierarchy_no_mem (tm3_clk_v0, tm3_clk_v2, tm3_vidin_llc, tm3_vid iic_start = 1'b0 ; reg_prog_nextstate = reg_prog_end ; end + default: + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b0 ; + reg_prog_nextstate = reg_prog_state; + end endcase end From 7358ae12c91c2576683184726864b3ad9ea14e55 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Thu, 25 Sep 2025 09:30:16 -0400 Subject: [PATCH 28/31] Convert flops back to combinational logic, selecting 0 for states that were previously latch holds --- vtr_flow/benchmarks/verilog/ch_intrinsics.v | 34 +++++++++++++++------ 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/vtr_flow/benchmarks/verilog/ch_intrinsics.v b/vtr_flow/benchmarks/verilog/ch_intrinsics.v index 3235899b759..707eab4a97f 100755 --- a/vtr_flow/benchmarks/verilog/ch_intrinsics.v +++ b/vtr_flow/benchmarks/verilog/ch_intrinsics.v @@ -47,20 +47,28 @@ reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag; always @(posedge clk) prevTag <= tag; -always @(posedge clk) +always @(*) begin if (~tag) begin - str_address <= memory_controller_address[4:0]; - str_write_enable <= memory_controller_write_enable; - str_in[7:0] <= memory_controller_in[7:0]; + str_address = memory_controller_address[4:0]; + str_write_enable = memory_controller_write_enable; + str_in[7:0] = memory_controller_in[7:0]; end + else + begin + str_address = 5'h0; + str_write_enable = 1'b0; + str_in[7:0] = 8'h0; + end end -always @(posedge clk) +always @(*) begin if (~prevTag) - memory_controller_out <= str_out; + memory_controller_out = str_out; + else + memory_controller_out = 'h0; end endmodule @@ -272,15 +280,21 @@ case(cur_state) end endcase -always @(posedge clk) +always @(*) begin if (cur_state == 4'b1101) begin - memory_controller_address <= s_07; - memory_controller_write_enable <= 1'b1; - memory_controller_in <= c; + memory_controller_address = s_07; + memory_controller_write_enable = 1'b1; + memory_controller_in = c; end + else + begin + memory_controller_address = 'h0; + memory_controller_write_enable = 1'b0; + memory_controller_in = 'h0; + end end From aefcc22e07ba6235b33cb28634f530ceea698076 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Thu, 25 Sep 2025 13:47:59 -0400 Subject: [PATCH 29/31] Move to alt version of benchmarks for which eliminating latches alters design resource counts signficantly --- vtr_flow/benchmarks/verilog/boundtop.v | 750 ++-- .../benchmarks/verilog/boundtop_nolatches.v | 3053 ++++++++++++++++ vtr_flow/benchmarks/verilog/ch_intrinsics.v | 53 +- .../verilog/ch_intrinsics_nolatches.v | 301 ++ vtr_flow/benchmarks/verilog/raygentop.v | 2840 +++++++-------- .../benchmarks/verilog/raygentop_nolatches.v | 3178 +++++++++++++++++ 6 files changed, 8135 insertions(+), 2040 deletions(-) create mode 100644 vtr_flow/benchmarks/verilog/boundtop_nolatches.v create mode 100755 vtr_flow/benchmarks/verilog/ch_intrinsics_nolatches.v create mode 100644 vtr_flow/benchmarks/verilog/raygentop_nolatches.v diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index bac522503f9..3beb662c402 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -234,7 +234,7 @@ assign raygroupout = raygroupout01 | raygroupout10 ; assign cntreset = cntreset01 | cntreset10 ; // reset <= reset01 or reset10; - always @(*) + always @(BoundNodeID01 or BoundNodeID10 or resultid) begin if (resultid == 2'b01) begin @@ -406,7 +406,7 @@ reg[31:0] temp_rgResultData; end end - always @(*) + always @(state or pending01 or pending10) begin case (state) 0 : @@ -424,9 +424,6 @@ reg[31:0] temp_rgResultData; begin next_state = 0 ; end - temp_rgResultReady = rgResultReady; - temp_rgResultData = rgResultData; - temp_rgResultSource = rgResultSource; end 1 : begin @@ -485,13 +482,10 @@ reg[31:0] temp_rgResultData; temp_rgResultReady = 1'b0 ; temp_rgResultSource = 2'b10 ; end - default: - begin - next_state = state; - temp_rgResultReady = u01a || u01b || u01c || v01a || v01b || v01c || u10a || u10b || u10c || v10a || v10b || v10c; - temp_rgResultData = rgResultData; - temp_rgResultSource = rgResultSource; - end + default: + begin + temp_rgResultReady = u01a || u01b || u01c || v01a || v01b || v01c || u10a || u10b || u10c || v10a || v10b || v10c; + end endcase end endmodule @@ -784,59 +778,10 @@ module boundcontroller (raygroupout, raygroupwe, raygroupid, enablenear, raygrou end end - // Refactoring this with better style like resulttransmit and listhandler blocks would be very - // time consuming, so instead apply an old trick where we initialize the value to previous state and - // then let the case statement simply superimpose updates on top of that. + + always @* - begin - next_state = state ; - temp_busy = busy; - temp_statepeek = statepeek; - temp_raygroupoutl = raygroupoutl ; - temp_cts = cts ; - temp_passCTSout = passCTSout ; - temp_resetcount = resetcount ; - temp_l0reset = l0reset ; - temp_addr = addr ; - temp_startAddr = startAddr ; - temp_boundNodeIDout = boundNodeIDout ; - temp_baseaddress = baseaddress ; - temp_hitmask = hitmask ; - temp_hit1 = hit1 ; - temp_hit2 = hit2 ; - temp_hit3 = hit3 ; - temp_triIDvalid = triIDvalid ; - temp_triID = triID ; - temp_lack = lack ; - temp_addrind = addrind ; - temp_addrindvalid = addrindvalid ; - temp_tladdr = tladdr ; - temp_tladdrvalid = tladdrvalid ; - temp_count = count ; - temp_subcount = subcount ; - temp_maskcount = maskcount ; - temp_triDatalatch = triDatalatch ; - temp_t1 = t1 ; - temp_u1 = u1 ; - temp_v1 = v1 ; - temp_id1 = id1 ; - temp_t2 = t2 ; - temp_u2 = u2 ; - temp_v2 = v2 ; - temp_id2 = id2 ; - temp_t3 = t3 ; - temp_u3 = u3 ; - temp_v3 = v3 ; - temp_id3 = id3 ; - // For the unregistered values, we have to pick default behavior; - // these values are used in enough other defined states to appear to - // be reasonable fallbacks, but putting this here does change design - // intent: - raygroupid = 0; - enablenear = 1'b0 ; - raygroupwe = 1'b0 ; - bcvalid = 1'b0 ; - lhreset = 1'b1 ; + begin case (state) 0 : begin @@ -1453,7 +1398,7 @@ endmodule end end - always @(*) + always @(state or trigger or count) begin case (state) 0 : @@ -1497,10 +1442,6 @@ endmodule end end - //Before adding default this could infer latches, so - //defaulting to holding previous state preserves deisgn intent - default: next_state = state; - endcase end endmodule @@ -1568,20 +1509,9 @@ reg temp_datavalid; end end - always @(*) - - begin - next_state = state; - temp_data = data; - temp_waddr = waddr; - temp_datavalid = datavalid; - // For the unregistered values, we have to pick default behavior; - // these values are used in enough other defined states to appear to - // be reasonable fallbacks, but putting this here does change design - // intent: - we = 1'b0 ; - want_addr = 1'b1 ; - want_data = 1'b0 ; + always @(state or addr_ready or data_ready or addrvalid or datavalid) + + begin case (state) 0 : begin @@ -1718,9 +1648,9 @@ reg temp_datavalid; -single_port_ram - # (.ADDR_WIDTH(10), .DATA_WIDTH(32)) -new_ram( +defparam new_ram.ADDR_WIDTH = 10; +defparam new_ram.DATA_WIDTH = 32; +single_port_ram new_ram( .clk (clk), .we(we), .data(datain), @@ -1804,24 +1734,9 @@ new_ram( end end - always @(*) - begin - next_state = state; - temp_statepeek = statepeek; - temp_data = data; - temp_datavalid = datavalid; - temp_waddress = waddress; - // For the unregistered values, we have to pick default behavior; - // these values are used in enough other defined states to appear to - // be reasonable fallbacks, but putting this here does change design - // intent: - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b11 ; - tm3_sram_adsp = 1'b1 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = 0; - want_addr = 1'b1 ; - want_data = 1'b0 ; + always @(state or addr_ready or data_ready or waddress or datain or addrvalid or + datavalid or addr) + begin case (state) 0 : begin @@ -2094,26 +2009,8 @@ module resultinterface (t1b, t2b, t3b, u1b, u2b, u3b, v1b, v2b, v3b, id1b, id2b, end end - always @(*) - begin - next_state = state ; - temp_t1b = t1b; - temp_newdata = newdata; - temp_u1b = u1b; - temp_v1b = v1b; - temp_id1b = id1b; - temp_hit1b = hit1b; - temp_resultID = resultID; - temp_t2b = t2b; - temp_u2b = u2b; - temp_id2b = id2b; - temp_t3b = t3b; - temp_u3b = u3b; - temp_v3b = v3b; - temp_id3b = id3b; - temp_hit3b = hit3b; - temp_v2b = v2b; - temp_hit2b = hit2b; + always @(state or resultready) + begin case (state) 0 : begin @@ -2320,7 +2217,7 @@ module sortedstack (keyin, datain, write, reset, peekdata, globalreset, clk); assign peekdata[(7 + 1) * (13) - 1:7 * (13)] = ((full7) == 1'b1) ? data7 : 0; // Select the proper insertion point - always @(*) + always @(keyin or key0 or key1 or key2 or key3 or key4 or key5 or key6 or key7 or full0 or full1 or full2 or full3 or full4 or full5 or full6 or full7) begin /* PAJ -- changed for loops */ @@ -2571,7 +2468,7 @@ module listhandler (dataarrayin, commit, hitmask, ack, boundnodeID, level, empty reg[2:0] offset1; reg[2:0] offset2; reg[4:0] address; - wire we; + reg we; reg[12:0] datain; wire[12:0] dataout; reg[2:0] lvempty; @@ -2601,390 +2498,265 @@ module listhandler (dataarrayin, commit, hitmask, ack, boundnodeID, level, empty assign empty = (lvempty == 3'b111 & busy == 1'b0) ? 1'b1 : 1'b0 ; assign dataready = ((((dataout[10]) == 1'b1 & (hitmask[0]) == 1'b1) | ((dataout[11]) == 1'b1 & (hitmask[1]) == 1'b1) | ((dataout[12]) == 1'b1 & (hitmask[2]) == 1'b1)) & (empty == 1'b0) & (busy == 1'b0)) ? 1'b1 : 1'b0 ; - always @(*) - begin - address[4:3] = readlevel ; + always @(offset0 or offset1 or offset2 or address) + begin + address[4:3] = readlevel ; - if (address[4:3] == 2'b00) - begin - address[2:0] = offset0 ; - end - else if (address[4:3] == 2'b01) - begin + if (address[4:3] == 2'b00) + begin + address[2:0] = offset0 ; + end + else if (address[4:3] == 2'b01) + begin - address[2:0] = offset1 ; - end - else if (address[4:3] == 2'b10) - begin - address[2:0] = offset2 ; - end - else - begin - address[2:0] = 0; - end - end + address[2:0] = offset1 ; + end + else if (address[4:3] == 2'b10) + begin + address[2:0] = offset2 ; + end + else + begin + address[2:0] = 0; + end + end - always @(posedge clk) - begin - if (globalreset == 1'b1) - begin - state <= 0 ; - lvempty <= 1; - busy <= 1'b0 ; - readlevel <= 2'b00 ; - writelevel <= 2'b00 ; - offset0 <= 3'b000 ; - offset1 <= 3'b000 ; - offset2 <= 3'b000 ; + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + lvempty <= 1; + busy <= 1'b0 ; + readlevel <= 2'b00 ; + writelevel <= 2'b00 ; + offset0 <= 3'b000 ; + offset1 <= 3'b000 ; + offset2 <= 3'b000 ; - end - else - begin - state <= next_state ; - peekstate <= temp_peekstate ; - busy <= temp_busy; - lvempty <= temp_lvempty; - readlevel <= temp_readlevel; - writelevel <= temp_writelevel; - offset0 <= temp_offset0; - offset1 <= temp_offset1; - offset2 <= temp_offset2; - end - end + end + else + begin + state <= next_state ; + peekstate <= temp_peekstate ; + busy <= temp_busy; + lvempty <= temp_lvempty; + readlevel <= temp_readlevel; + writelevel <= temp_writelevel; + offset0 <= temp_offset0; + offset1 <= temp_offset1; + offset2 <= temp_offset2; + + end + end - //for we and datain we cannot preserve original functionality and stil - //eliminate latches because there were no flops for them in the original - //code. The best we can do is observe that nonzero, valid behavior - //is defined only when state == 2'b01. Since putting these behind flops - //would change their timing, build a mux and set we and datain to zero - //for previously undefined states - assign we = (state == 2'b01); - always @(*) begin - if (state == 2'b01) begin - case(address[2:0]) - 3'b000: datain = dataarrayin[0+:13]; - 3'b001: datain = dataarrayin[13+:13]; - 3'b010: datain = dataarrayin[26+:13]; - 3'b011: datain = dataarrayin[39+:13]; - 3'b100: datain = dataarrayin[52+:13]; - 3'b101: datain = dataarrayin[65+:13]; - 3'b110: datain = dataarrayin[78+:13]; - 3'b111: datain = dataarrayin[91+:13]; - endcase - end - else begin - datain = 'h0; - end - end - - always @(*) - begin - - // Note that throughout this case statement it is necessary to - // add else statements that were not previously present in order - // to prevent latch inference. To preserve previous behavior, - // these else statements should always set the value equal to - // previous state - case (state) + always @(state or commit or ack or address or dataarrayin or reset or dataready or + empty) + begin + + case (state) 2'b00 : - begin - temp_peekstate = 2'b01 ; - - if (reset == 1'b1) - begin - temp_busy = 1'b0 ; - temp_lvempty = 1; - temp_readlevel = 2'b00 ; - - temp_writelevel = 2'b00 ; - temp_offset0 = 3'b000 ; - temp_offset1 = 3'b000 ; - temp_offset2 = 3'b000 ; - end - else if (commit == 1'b1) - begin - temp_busy = 1'b1 ; - if (writelevel == 2'b00) + begin + we = 1'b0 ; + datain = 0; + if (reset == 1'b1) begin - temp_offset0 = 3'b000 ; - temp_offset1 = offset1; - temp_offset2 = offset2; + next_state = 0 ; end - - else if (writelevel == 2'b01) + else if (commit == 1'b1) begin - temp_offset1 = 3'b000 ; - temp_offset0 = offset0; - temp_offset2 = offset2; + next_state = 1 ; end - else if (writelevel == 2'b10) + else if ((ack == 1'b1) | (dataready == 1'b0 & empty == 1'b0)) + begin - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = 3'b000 ; + next_state = 2 ; end - else begin - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2; - end - temp_readlevel = writelevel ; - temp_writelevel = writelevel; - temp_lvempty = lvempty; - end - - else if (ack == 1'b1) - begin - temp_writelevel = readlevel + 1 ; - temp_readlevel = readlevel; - temp_busy = 1'b1 ; // This will ensure that align skips one - temp_lvempty = lvempty; - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2; - end - else begin - temp_busy = busy; - temp_lvempty = lvempty; - temp_readlevel = readlevel; - temp_writelevel = writelevel; - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2; - temp_readlevel = readlevel; - temp_writelevel = writelevel; - end - end + else + begin + next_state = 0 ; + end + temp_peekstate = 2'b01 ; + + if (reset == 1'b1) + begin + temp_busy = 1'b0 ; + temp_lvempty = 1; + temp_readlevel = 2'b00 ; + + temp_writelevel = 2'b00 ; + temp_offset0 = 3'b000 ; + temp_offset1 = 3'b000 ; + temp_offset2 = 3'b000 ; + end + else if (commit == 1'b1) + begin + temp_busy = 1'b1 ; + if (writelevel == 2'b00) + begin + temp_offset0 = 3'b000 ; + end + + else if (writelevel == 2'b01) + begin + temp_offset1 = 3'b000 ; + end + else if (writelevel == 2'b10) + begin + temp_offset2 = 3'b000 ; + end + temp_readlevel = writelevel ; + end + + else if (ack == 1'b1) + begin + temp_writelevel = readlevel + 1 ; + temp_busy = 1'b1 ; // This will ensure that align skips one + end + + end 2'b01 : - begin - temp_peekstate = 2'b10 ; - - if (readlevel == 2'b00) - begin - temp_offset0 = offset0 + 1 ; - temp_offset1 = offset1; - temp_offset2 = offset2; - end - else if (readlevel == 2'b01) - begin - temp_offset1 = offset1 + 1 ; - temp_offset0 = offset0; - temp_offset2 = offset2; - end - else if (readlevel == 2'b10) - begin - temp_offset2 = offset2 + 1 ; - temp_offset0 = offset0; - temp_offset1 = offset1; - end - else - begin - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2; - end - - if (address[2:0] == 3'b111) - begin - temp_busy = 1'b0 ; - end - else begin - temp_busy = busy; - end - - if ((datain[10]) == 1'b1 | (datain[11]) == 1'b1 | (datain[12]) == 1'b1) - begin - if (readlevel == 2'b00) + begin +/* PAJ -- Unrolled loop */ + if (address[2:0] == 0) + begin + datain = dataarrayin[(1) * 13 - 1:0 * 13] ; + end + else if ( address[2:0] == 1) + begin + datain = dataarrayin[(2) * 13 - 1:1 * 13] ; + end + else if ( address[2:0] ==2) + begin + datain = dataarrayin[(3) * 13 - 1:2 * 13] ; + end + else if ( address[2:0] ==3) + begin + datain = dataarrayin[(4) * 13 - 1:3 * 13] ; + end + else if ( address[2:0] ==4) + begin + datain = dataarrayin[(5) * 13 - 1:4 * 13] ; + end + else if ( address[2:0] ==5) + begin + datain = dataarrayin[(6) * 13 - 1:5 * 13] ; + end + else if ( address[2:0] ==6) + begin + datain = dataarrayin[(7) * 13 - 1:6 * 13] ; + end + else if ( address[2:0] ==7) + begin + datain = dataarrayin[(8) * 13 - 1:7 * 13] ; + end + + + we = 1'b1 ; + if (address[2:0] == 3'b111) begin - temp_lvempty[0] = 1'b0 ; - temp_lvempty[1] = lvempty[1] ; - temp_lvempty[2] = lvempty[2] ; + next_state = 2 ; + end - else if (readlevel == 2'b01) - begin - temp_lvempty[1] = 1'b0 ; - temp_lvempty[0] = lvempty[0] ; - temp_lvempty[2] = lvempty[2] ; - end - else if (readlevel == 2'b10) + else begin - temp_lvempty[2] = 1'b0 ; - temp_lvempty[0] = lvempty[0] ; - temp_lvempty[1] = lvempty[1] ; - end - else begin - temp_lvempty = lvempty; - end - end - else begin - temp_lvempty = lvempty; - end - - temp_readlevel = readlevel; - temp_writelevel = writelevel; - - end + next_state = 1 ; + end + temp_peekstate = 2'b10 ; + + if (readlevel == 2'b00) + begin + temp_offset0 = offset0 + 1 ; + end + + else if (readlevel == 2'b01) + begin + temp_offset1 = offset1 + 1 ; + end + else if (readlevel == 2'b10) + begin + temp_offset2 = offset2 + 1 ; + end + if (address[2:0] == 3'b111) + begin + temp_busy = 1'b0 ; + end + + if ((datain[10]) == 1'b1 | (datain[11]) == 1'b1 | (datain[12]) == 1'b1) + begin + if (readlevel == 2'b00) + begin + temp_lvempty[0] = 1'b0 ; + end + else if (readlevel == 2'b01) + begin + temp_lvempty[1] = 1'b0 ; + end + else if (readlevel == 2'b10) + begin + + temp_lvempty[2] = 1'b0 ; + end + end + + end 2'b10 : - begin - if (empty == 1'b0 & dataready == 1'b0) - temp_peekstate = 2'b11 ; - else - temp_peekstate = peekstate; - - temp_busy = 1'b0 ; - - if (empty == 1'b0 & dataready == 1'b0) - begin - if (readlevel == 2'b00) - begin - if (offset0 == 3'b111) - begin - temp_lvempty[0] = 1'b1 ; - temp_lvempty[1] = lvempty[1]; - temp_lvempty[2] = lvempty[2]; - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2; - end - else - begin - temp_lvempty = lvempty; - temp_offset0 = offset0 + 1 ; - temp_offset1 = offset1; - temp_offset2 = offset2; - end - temp_readlevel = readlevel; - temp_writelevel = writelevel; - end - else if (readlevel == 2'b01) - begin - if (offset1 == 3'b111) - begin - temp_lvempty[1] = 1'b1 ; - temp_lvempty[0] = lvempty[0]; - temp_lvempty[2] = lvempty[2]; - temp_readlevel = 2'b00 ; - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2; - end - else - begin - temp_offset1 = offset1 + 1 ; - temp_offset0 = offset0; - temp_offset2 = offset2; - temp_lvempty = lvempty; - temp_readlevel = readlevel; - end - temp_writelevel = writelevel; - end - else if (readlevel == 2'b10) - begin - if (offset2 == 3'b111) - begin - temp_lvempty[2] = 1'b1 ; - temp_lvempty[1:0] = lvempty[1:0]; - if ((lvempty[1]) == 1'b1) + begin + if (empty == 1'b0 & dataready == 1'b0) + begin + next_state = 2 ; + end + else + next_state = 0 ; + + temp_peekstate = 2'b11 ; + temp_busy = 1'b0 ; + if (empty == 1'b0 & dataready == 1'b0) + begin + if (readlevel == 2'b00) + begin + if (offset0 == 3'b111) begin - temp_readlevel = 2'b00 ; + temp_lvempty[0] = 1'b1 ; end - else + else + begin + temp_offset0 = offset0 + 1 ; + end + end + else if (readlevel == 2'b01) + begin + if (offset1 == 3'b111) begin - temp_readlevel = 2'b01 ; + temp_lvempty[1] = 1'b1 ; + temp_readlevel = 2'b00 ; end - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2; - end - else - begin - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2 + 1 ; - temp_lvempty = lvempty; - temp_readlevel = readlevel; - end - temp_writelevel = writelevel; - end - else - begin - temp_lvempty = lvempty; - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2; - temp_readlevel = readlevel; - temp_writelevel = writelevel; - end - end - else - begin - temp_lvempty = lvempty; - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2; - temp_readlevel = readlevel; - temp_writelevel = writelevel; - end - end - default: begin - // preserve original design intent by holding state, even if - // this behavior is not really sensical - temp_peekstate = peekstate ; - temp_busy = busy; - temp_lvempty = lvempty; - temp_readlevel = readlevel; - temp_writelevel = writelevel; - temp_offset0 = offset0; - temp_offset1 = offset1; - temp_offset2 = offset2; - end - endcase - - case (state) - 2'b00 : - begin - if (reset == 1'b1) - begin - next_state = 0 ; - end - else if (commit == 1'b1) - begin - next_state = 1 ; - end - else if ((ack == 1'b1) | (dataready == 1'b0 & empty == 1'b0)) - begin - next_state = 2 ; - end - else - begin - next_state = 0 ; - end - end - 2'b01 : - begin - if (address[2:0] == 3'b111) - begin - next_state = 2 ; - end - else - begin - next_state = 1 ; - end - end - 2'b10 : - begin - if (empty == 1'b0 & dataready == 1'b0) - begin - next_state = 2 ; - end - else - next_state = 0 ; - end - default: begin - // preserve original design intent by holding state, even if - // this behavior is not really sensical - next_state = state; - end + else + begin + temp_offset1 = offset1 + 1 ; + end + end + else if (readlevel == 2'b10) + begin + if (offset2 == 3'b111) + begin + temp_lvempty[2] = 1'b1 ; + if ((lvempty[1]) == 1'b1) + begin + temp_readlevel = 2'b00 ; + end + else + begin + temp_readlevel = 2'b01 ; + end + end + else + begin + temp_offset2 = offset2 + 1 ; + end + end + end + end endcase end endmodule diff --git a/vtr_flow/benchmarks/verilog/boundtop_nolatches.v b/vtr_flow/benchmarks/verilog/boundtop_nolatches.v new file mode 100644 index 00000000000..bac522503f9 --- /dev/null +++ b/vtr_flow/benchmarks/verilog/boundtop_nolatches.v @@ -0,0 +1,3053 @@ + module paj_boundtop_hierarchy_no_mem (triIDvalid, triID, wanttriID, raydata, rayaddr, raywe, resultready, resultdata, globalreset, want_braddr, braddr_ready, braddrin, want_brdata, brdata_ready, brdatain, want_addr2, addr2_ready, addr2in, want_data2, data2_ready, data2in, pglobalreset, tm3_clk_v0, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, rgData, rgAddr, rgWE, rgAddrValid, rgDone, rgResultData, rgResultReady, rgResultSource, input1); + + + output triIDvalid; + wire triIDvalid; + output[15:0] triID; + wire[15:0] triID; + input wanttriID; + output[31:0] raydata; + wire[31:0] raydata; + output[3:0] rayaddr; + wire[3:0] rayaddr; + output[2:0] raywe; + wire[2:0] raywe; + input resultready; + input[31:0] resultdata; + output globalreset; + wire globalreset; + output want_braddr; + wire want_braddr; + input braddr_ready; + input[9:0] braddrin; + output want_brdata; + wire want_brdata; + input brdata_ready; + input[31:0] brdatain; + output want_addr2; + wire want_addr2; + input addr2_ready; + input[17:0] addr2in; + output want_data2; + wire want_data2; + input data2_ready; + input[63:0] data2in; + input pglobalreset; + input tm3_clk_v0; + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_xhdl0; + output[18:0] tm3_sram_addr; + wire[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + wire[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + wire[1:0] tm3_sram_oe; + output tm3_sram_adsp; + wire tm3_sram_adsp; + input[1:0] raygroup01; + input raygroupvalid01; + output busy01; + wire busy01; + input[1:0] raygroup10; + input raygroupvalid10; + output busy10; + wire busy10; + input[31:0] rgData; + input[3:0] rgAddr; + input[2:0] rgWE; + input rgAddrValid; + output rgDone; + wire rgDone; + output[31:0] rgResultData; + wire[31:0] rgResultData; + output rgResultReady; + wire rgResultReady; + output[1:0] rgResultSource; + wire[1:0] rgResultSource; + input input1; + wire raygroupwe; + wire raygroupwe01; + wire raygroupwe10; + wire[1:0] raygroupout; + wire[1:0] raygroupout01; + wire[1:0] raygroupout10; + wire[1:0] raygroupid; + wire[1:0] raygroupid01; + wire[1:0] raygroupid10; + reg[1:0] oldresultid; + wire[1:0] resultid; + wire[31:0] t1i; + wire[31:0] t2i; + wire[31:0] t3i; + wire[15:0] u1i; + wire[15:0] u2i; + wire[15:0] u3i; + wire[15:0] v1i; + wire[15:0] v2i; + wire[15:0] v3i; + wire[15:0] id1i; + wire[15:0] id2i; + wire[15:0] id3i; + wire hit1i; + wire hit2i; + wire hit3i; + wire newresult; + wire write; + reg reset; + wire reset01; + wire reset10; + wire[103:0] peekdata; + reg[103:0] peeklatch; + wire commit01; + wire commit10; + wire[1:0] baseaddress01; + wire[1:0] baseaddress10; + wire[1:0] done; + wire cntreset; + wire cntreset01; + wire cntreset10; + wire passCTS01; + wire passCTS10; + wire triIDvalid01; + wire triIDvalid10; + wire[15:0] triID01; + wire[15:0] triID10; + reg[9:0] boundNodeID; + wire[9:0] BoundNodeID01; + wire[9:0] BoundNodeID10; + wire enablenear; + wire enablenear01; + wire enablenear10; + wire ack01; + wire ack10; + wire empty01; + wire dataready01; + wire empty10; + wire dataready10; + wire lhreset01; + wire lhreset10; + wire[9:0] boundnodeIDout01; + wire[9:0] boundnodeIDout10; + wire[1:0] level01; + wire[1:0] level10; + wire[2:0] hitmask01; + wire[2:0] hitmask10; + // Offset Block Ram Read Signals + wire[9:0] ostaddr; + wire[9:0] addrind01; + wire[9:0] addrind10; + wire ostaddrvalid; + wire addrindvalid01; + wire addrindvalid10; + wire ostdatavalid; + wire[31:0] ostdata; + // Tri List Ram Read Signals + wire[17:0] tladdr; + wire[17:0] tladdr01; + wire[17:0] tladdr10; + wire tladdrvalid; + wire tladdrvalid01; + wire tladdrvalid10; + wire tldatavalid; +wire[63:0] tldata; + // Final Result Signals + wire[31:0] t1_01; + wire[31:0] t2_01; + wire[31:0] t3_01; + wire[31:0] t1_10; + wire[31:0] t2_10; + wire[31:0] t3_10; + wire[15:0] v1_01; + wire[15:0] v2_01; + wire[15:0] v3_01; + wire[15:0] v1_10; + wire[15:0] v2_10; + wire[15:0] v3_10; + wire[15:0] u1_01; + wire[15:0] u2_01; + wire[15:0] u3_01; + wire[15:0] u1_10; + wire[15:0] u2_10; + wire[15:0] u3_10; + wire[15:0] id1_01; + wire[15:0] id2_01; + wire[15:0] id3_01; + wire[15:0] id1_10; + wire[15:0] id2_10; + wire[15:0] id3_10; + wire hit1_01; + wire hit2_01; + wire hit3_01; + wire hit1_10; + wire hit2_10; + wire hit3_10; + wire bcvalid01; + wire bcvalid10; + wire[2:0] peekoffset1a; + wire[2:0] peekoffset1b; + wire[2:0] peekoffset0a; + wire[2:0] peekoffset0b; + wire[2:0] peekoffset2a; + wire[2:0] peekoffset2b; + wire[4:0] peekaddressa; + wire[4:0] peekaddressb; + wire doutput; + wire dack; + wire[4:0] state01; + wire[4:0] state10; + wire[2:0] junk1; + wire[2:0] junk1b; + wire junk2; + wire junk2a; + wire[1:0] junk3; + wire[1:0] junk4; + wire[13:0] debugcount01; + wire[13:0] debugcount10; + wire[1:0] debugsubcount01; + wire[1:0] debugsubcount10; + wire[2:0] statesram; + + onlyonecycle oc (input1, doutput, pglobalreset, tm3_clk_v0); + // Real Stuff Starts Here + assign ostaddr = addrind01 | addrind10 ; + assign ostaddrvalid = addrindvalid01 | addrindvalid10 ; + + vblockramcontroller offsettable(want_braddr, braddr_ready, braddrin, want_brdata, brdata_ready, brdatain, ostaddr, ostaddrvalid, ostdata, ostdatavalid, pglobalreset, tm3_clk_v0); + assign tladdr = tladdr01 | tladdr10 ; + assign tladdrvalid = tladdrvalid01 | tladdrvalid10 ; + sramcontroller trilist (want_addr2, addr2_ready, addr2in, want_data2, data2_ready, data2in, tladdr, tladdrvalid, tldata, tldatavalid, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, pglobalreset, tm3_clk_v0, statesram); + resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0); + rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0); + boundcontroller boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01); + boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount10); + resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0); + +assign raygroupout = raygroupout01 | raygroupout10 ; + assign raygroupwe = raygroupwe01 | raygroupwe10 ; + assign raygroupid = raygroupid01 | raygroupid10 ; + assign triIDvalid = triIDvalid01 | triIDvalid10 ; + assign enablenear = enablenear01 | enablenear10 ; + assign triID = triID01 | triID10 ; + assign cntreset = cntreset01 | cntreset10 ; + + // reset <= reset01 or reset10; + always @(*) + begin + if (resultid == 2'b01) + begin + boundNodeID = BoundNodeID01 ; + end + else if (resultid == 2'b10) + begin + boundNodeID = BoundNodeID10 ; + end + else + begin + boundNodeID = 10'b0000000000 ; + end + end + assign write = ((newresult == 1'b1) & (resultid != 0) & ((hit1i == 1'b1) | (hit2i == 1'b1) | (hit3i == 1'b1))) ? 1'b1 : 1'b0 ; + + sortedstack st(t1i, {hit3i, hit2i, hit1i, boundNodeID}, write, reset, peekdata, pglobalreset, tm3_clk_v0); + assign commit01 = (done == 2'b01) ? 1'b1 : 1'b0 ; + assign commit10 = (done == 2'b10) ? 1'b1 : 1'b0 ; + assign dack = doutput | ack01 ; + listhandler lh01 (peeklatch, commit01, hitmask01, dack, boundnodeIDout01, level01, empty01, dataready01, lhreset01, pglobalreset, tm3_clk_v0, peekoffset0a, peekoffset1a, peekoffset2a, junk2a, junk4); + listhandler lh02 (peeklatch, commit10, hitmask10, ack10, boundnodeIDout10, level10, empty10, dataready10, lhreset10, pglobalreset, tm3_clk_v0, junk1, junk1b, peekoffset2b, junk2, junk3); + + always @(posedge tm3_clk_v0) + begin + if (pglobalreset == 1'b1) + begin + peeklatch <= 0; + reset <= 1'b0 ; + oldresultid <= 2'b00 ; + end + else + begin + oldresultid <= resultid ; + // The reset is only for debugging + if (resultid != oldresultid) + begin + reset <= 1'b1 ; + end + else + begin + reset <= 1'b0 ; + end + if (done != 0) + begin + peeklatch <= peekdata ; + end + end + end + + resultcounter rc (resultid, newresult, done, cntreset, pglobalreset, tm3_clk_v0); + + // global reset as an output should be driven! + assign globalreset = pglobalreset; + + endmodule + + + + + + + + + + + + + + +module resulttransmit (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); + + input valid01; + input valid10; + input[15:0] id01a; + input[15:0] id01b; + input[15:0] id01c; + input[15:0] id10a; + input[15:0] id10b; + input[15:0] id10c; + input hit01a; + input hit01b; + + input hit01c; + input hit10a; + input hit10b; + input hit10c; + input[15:0] u01a; + input[15:0] u01b; + input[15:0] u01c; + input[15:0] v01a; + input[15:0] v01b; + input[15:0] v01c; + input[15:0] u10a; + input[15:0] u10b; + + input[15:0] u10c; + input[15:0] v10a; + input[15:0] v10b; + input[15:0] v10c; + output[31:0] rgResultData; + reg[31:0] rgResultData; + output rgResultReady; + reg rgResultReady; + output[1:0] rgResultSource; + reg[1:0] rgResultSource; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + + reg hit01al; + reg hit01bl; + reg hit01cl; + reg hit10al; + reg hit10bl; + reg hit10cl; + reg pending01; + reg pending10; + reg valid01d; + reg valid10d; + +reg[31:0] temp_rgResultData; + reg temp_rgResultReady; + reg[1:0] temp_rgResultSource; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + pending01 <= 1'b0 ; + pending10 <= 1'b0 ; + rgResultData <= 32'b00000000000000000000000000000000 ; + rgResultSource <= 2'b00 ; + + rgResultReady <= 1'b0 ; + end + else + begin + valid01d <= valid01 ; + valid10d <= valid10 ; + if (valid01 == 1'b1) + begin + pending01 <= 1'b1 ; + end + if (valid01d == 1'b1) + begin + hit01al <= hit01a ; + hit01bl <= hit01b ; + hit01cl <= hit01c ; + end + if (valid10 == 1'b1) + begin + pending10 <= 1'b1 ; + end + if (valid10d == 1'b1) + begin + hit10al <= hit10a ; + hit10bl <= hit10b ; + hit10cl <= hit10c ; + end + state <= next_state ; + + rgResultData <= temp_rgResultData; + rgResultReady <= temp_rgResultReady; + rgResultSource <= temp_rgResultSource; + end + end + + always @(*) + begin + case (state) + 0 : + begin + if (pending01 == 1'b1) + begin + next_state = 1 ; + end + else if (pending10 == 1'b1) + begin + next_state = 5 ; + end + else + + begin + next_state = 0 ; + end + temp_rgResultReady = rgResultReady; + temp_rgResultData = rgResultData; + temp_rgResultSource = rgResultSource; + end + 1 : + begin + next_state = 2 ; + temp_rgResultData = {id01a, id01b} ; + temp_rgResultReady = 1'b1 ; + temp_rgResultSource = 2'b01 ; + end + 2 : + begin + next_state = 3 ; + temp_rgResultData = {13'b0000000000000, hit01al, hit01bl, hit01cl, id01c} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b01 ; + end + + 3 : + begin + next_state = 4 ; + temp_rgResultData = {8'b00000000, u01a[15:8], u01b[15:8], u01c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b01 ; + end + 4 : + begin + next_state = 0 ; + temp_rgResultData = {8'b00000000, v01a[15:8], v01b[15:8], v01c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b01 ; + end + 5 : + begin + next_state = 6 ; + temp_rgResultData = {id10a, id10b} ; + temp_rgResultReady = 1'b1 ; + temp_rgResultSource = 2'b10 ; + end + 6 : + begin + next_state = 7 ; + temp_rgResultData = {13'b0000000000000, hit10al, hit10bl, hit10cl, id10c} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b10 ; + end + 7 : + begin + next_state = 8 ; + temp_rgResultData = {8'b00000000, u10a[15:8], u10b[15:8], u10c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b10 ; + end + 8 : + begin + next_state = 0 ; + temp_rgResultData = {8'b00000000, v10a[15:8], v10b[15:8], v10c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b10 ; + end + default: + begin + next_state = state; + temp_rgResultReady = u01a || u01b || u01c || v01a || v01b || v01c || u10a || u10b || u10c || v10a || v10b || v10c; + temp_rgResultData = rgResultData; + temp_rgResultSource = rgResultSource; + end + endcase + end + endmodule + + + + + + + + + + + + + + + + + + + + + + + + + +module boundcontroller (raygroupout, raygroupwe, raygroupid, enablenear, raygroup, validraygroup, busy, triIDvalid, triID, wanttriID, l0reset, baseaddress, newdata, boundNodeIDout, resultID, hitmask, ldataready, lempty, llevel, lboundNodeID, lack, lhreset, addrind, addrindvalid, dataind, dataindvalid, tladdr, tladdrvalid, tldata, tldatavalid, t1in, t2in, t3in, u1in, u2in, u3in, v1in, v2in, v3in, id1in, id2in, id3in, hit1in, hit2in, hit3in, t1, t2, t3, u1, u2, u3, v1, v2, v3, id1, id2, id3, hit1, hit2, hit3, bcvalid, done, resetcnt, passCTSout, passCTSin, globalreset, clk, statepeek, debugsubcount, debugcount); + + output[1:0] raygroupout; + wire[1:0] raygroupout; + output raygroupwe; + reg raygroupwe; + output[1:0] raygroupid; + reg[1:0] raygroupid; + output enablenear; + reg enablenear; + input[1:0] raygroup; + input validraygroup; + output busy; + reg busy; + reg temp_busy; + output triIDvalid; + reg triIDvalid; + output[15:0] triID; + reg[15:0] triID; + input wanttriID; + output l0reset; + reg l0reset; + output[1:0] baseaddress; + reg[1:0] baseaddress; + input newdata; + output[9:0] boundNodeIDout; + reg[9:0] boundNodeIDout; + input[1:0] resultID; + output[2:0] hitmask; + reg[2:0] hitmask; + input ldataready; + input lempty; + input[1:0] llevel; + input[9:0] lboundNodeID; + output lack; + reg lack; + output lhreset; + reg lhreset; + output[9:0] addrind; + reg[9:0] addrind; + output addrindvalid; + reg addrindvalid; + input[31:0] dataind; + input dataindvalid; + output[17:0] tladdr; + reg[17:0] tladdr; + output tladdrvalid; + reg tladdrvalid; + input[63:0] tldata; + input tldatavalid; + input[31:0] t1in; + input[31:0] t2in; + input[31:0] t3in; + input[15:0] u1in; + input[15:0] u2in; + input[15:0] u3in; + input[15:0] v1in; + input[15:0] v2in; + input[15:0] v3in; + input[15:0] id1in; + input[15:0] id2in; + input[15:0] id3in; + input hit1in; + input hit2in; + input hit3in; + output[31:0] t1; + reg[31:0] t1; + output[31:0] t2; + reg[31:0] t2; + output[31:0] t3; + reg[31:0] t3; + output[15:0] u1; + reg[15:0] u1; + output[15:0] u2; + reg[15:0] u2; + output[15:0] u3; + reg[15:0] u3; + output[15:0] v1; + reg[15:0] v1; + output[15:0] v2; + reg[15:0] v2; + output[15:0] v3; + reg[15:0] v3; + output[15:0] id1; + reg[15:0] id1; + output[15:0] id2; + reg[15:0] id2; + output[15:0] id3; + reg[15:0] id3; + output hit1; + reg hit1; + output hit2; + reg hit2; + output hit3; + reg hit3; + output bcvalid; + reg bcvalid; + input[1:0] done; + output resetcnt; + reg resetcnt; + output passCTSout; + reg passCTSout; + input passCTSin; + input globalreset; + input clk; + output[4:0] statepeek; + reg[4:0] statepeek; + output[1:0] debugsubcount; + wire[1:0] debugsubcount; + output[13:0] debugcount; + wire[13:0] debugcount; + + reg[4:0] state; + reg[4:0] next_state; + reg cts; + reg[11:0] addr; + reg[11:0] startAddr; + reg[2:0] resetcount; + reg[1:0] raygroupoutl; + // Leaf Node Signals + reg[13:0] count; + reg[63:0] triDatalatch; + reg[1:0] subcount; + reg[1:0] maskcount; + + reg[4:0] temp_statepeek; + reg [1:0]temp_raygroupoutl ; + reg temp_cts ; + reg temp_passCTSout ; + reg [2:0]temp_resetcount ; + reg temp_l0reset ; + reg [11:0]temp_addr ; + reg [11:0]temp_startAddr ; + reg [9:0]temp_boundNodeIDout ; + reg [1:0]temp_baseaddress ; + reg [2:0]temp_hitmask ; + reg temp_hit1 ; + reg temp_hit2 ; + reg temp_hit3 ; + reg temp_triIDvalid ; + reg [15:0]temp_triID ; + reg temp_lack ; + reg [9:0]temp_addrind ; + reg temp_addrindvalid ; + reg temp_tladdrvalid ; + reg [17:0]temp_tladdr ; + reg [13:0]temp_count ; + reg [1:0]temp_subcount ; + reg [1:0]temp_maskcount ; + reg [63:0]temp_triDatalatch ; + reg [31:0]temp_t1 ; + reg [15:0]temp_u1 ; + reg [15:0]temp_v1 ; + reg [15:0]temp_id1 ; + reg [31:0]temp_t2 ; + reg [15:0]temp_u2 ; + reg [15:0]temp_v2 ; + reg [15:0]temp_id2 ; + reg [31:0]temp_t3 ; + reg [15:0]temp_u3 ; + reg [15:0]temp_v3 ; + reg [15:0]temp_id3 ; + + assign debugsubcount = subcount ; + assign debugcount = count ; + assign raygroupout = (cts == 1'b1 & state != 8 & state != 19 & state != 1) ? raygroupoutl : 2'b00 ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + raygroupoutl <= 0; + cts <= 1'b0 ; + passCTSout <= 1'b0 ; + addr <= 0; + startAddr <= 0; + boundNodeIDout <= 0; + resetcount <= 0; + hitmask <= 1; + lack <= 1'b0 ; + baseaddress <= 0; + l0reset <= 1'b0 ; + resetcnt <= 1'b0 ; + triIDvalid <= 1'b0 ; + triID <= 0; + addrind <= 0; + addrindvalid <= 1'b0 ; + tladdrvalid <= 1'b0 ; + tladdr <= 0; + triDatalatch <= 0; + maskcount <= 0; + subcount <= 0; + count <= 0; + hit1 <= 1'b0 ; + hit2 <= 1'b0 ; + hit3 <= 1'b0 ; + t1 <= 0; + t2 <= 0; + t3 <= 0; + u1 <= 0; + u2 <= 0; + u3 <= 0; + v1 <= 0; + v2 <= 0; + v3 <= 0; + id1 <= 0; + id2 <= 0; + id3 <= 0; + busy <= 1'b0 ; + end + else + begin + state <= next_state ; + busy <= temp_busy; + if ((done == 2'b00) | (state == 15 & newdata == 1'b1 & resultID == 2'b00)) + begin + resetcnt <= 1'b1 ; + end + else + begin + resetcnt <= 1'b0 ; + end + + statepeek <= temp_statepeek; + raygroupoutl <= temp_raygroupoutl ; + cts <= temp_cts ; + passCTSout <= temp_passCTSout ; + resetcount <= temp_resetcount ; + l0reset <= temp_l0reset ; + addr <= temp_addr ; + startAddr <= temp_startAddr ; + boundNodeIDout <= temp_boundNodeIDout ; + baseaddress <= temp_baseaddress ; + hitmask <= temp_hitmask ; + hit1 <= temp_hit1 ; + hit2 <= temp_hit2 ; + hit3 <= temp_hit3 ; + triIDvalid <= temp_triIDvalid ; + triID <= temp_triID ; + lack <= temp_lack ; + addrind <= temp_addrind ; + addrindvalid <= temp_addrindvalid ; + tladdr <= temp_tladdr ; + tladdrvalid <= temp_tladdrvalid ; + count <= temp_count ; + subcount <= temp_subcount ; + maskcount <= temp_maskcount ; + triDatalatch <= temp_triDatalatch ; + t1 <= temp_t1 ; + u1 <= temp_u1 ; + v1 <= temp_v1 ; + id1 <= temp_id1 ; + t2 <= temp_t2 ; + u2 <= temp_u2 ; + v2 <= temp_v2 ; + id2 <= temp_id2 ; + t3 <= temp_t3 ; + u3 <= temp_u3 ; + v3 <= temp_v3 ; + id3 <= temp_id3 ; + end + end + + // Refactoring this with better style like resulttransmit and listhandler blocks would be very + // time consuming, so instead apply an old trick where we initialize the value to previous state and + // then let the case statement simply superimpose updates on top of that. + always @* + begin + next_state = state ; + temp_busy = busy; + temp_statepeek = statepeek; + temp_raygroupoutl = raygroupoutl ; + temp_cts = cts ; + temp_passCTSout = passCTSout ; + temp_resetcount = resetcount ; + temp_l0reset = l0reset ; + temp_addr = addr ; + temp_startAddr = startAddr ; + temp_boundNodeIDout = boundNodeIDout ; + temp_baseaddress = baseaddress ; + temp_hitmask = hitmask ; + temp_hit1 = hit1 ; + temp_hit2 = hit2 ; + temp_hit3 = hit3 ; + temp_triIDvalid = triIDvalid ; + temp_triID = triID ; + temp_lack = lack ; + temp_addrind = addrind ; + temp_addrindvalid = addrindvalid ; + temp_tladdr = tladdr ; + temp_tladdrvalid = tladdrvalid ; + temp_count = count ; + temp_subcount = subcount ; + temp_maskcount = maskcount ; + temp_triDatalatch = triDatalatch ; + temp_t1 = t1 ; + temp_u1 = u1 ; + temp_v1 = v1 ; + temp_id1 = id1 ; + temp_t2 = t2 ; + temp_u2 = u2 ; + temp_v2 = v2 ; + temp_id2 = id2 ; + temp_t3 = t3 ; + temp_u3 = u3 ; + temp_v3 = v3 ; + temp_id3 = id3 ; + // For the unregistered values, we have to pick default behavior; + // these values are used in enough other defined states to appear to + // be reasonable fallbacks, but putting this here does change design + // intent: + raygroupid = 0; + enablenear = 1'b0 ; + raygroupwe = 1'b0 ; + bcvalid = 1'b0 ; + lhreset = 1'b1 ; + case (state) + 0 : + begin + raygroupid = 0; + enablenear = 1'b0 ; + raygroupwe = 1'b0 ; + bcvalid = 1'b0 ; + + lhreset = 1'b1 ; + if (validraygroup == 1'b1 & cts == 1'b1) + begin + next_state = 2 ; + temp_busy = 1'b1 ; + end + else if (validraygroup == 1'b1 & cts == 1'b0) + begin + next_state = 1 ; + temp_busy = 1'b0 ; + end + else if (validraygroup == 1'b0 & passCTSin == 1'b1 & cts == 1'b1) + begin + next_state = 1 ; + temp_busy = 1'b0 ; + end + else + begin + next_state = 0 ; + temp_busy = 1'b0 ; + end + + temp_statepeek = 5'b00001 ; + // + temp_raygroupoutl = raygroup ; + if (validraygroup == 1'b1 & cts == 1'b0) + begin + temp_cts = 1'b1 ; + temp_passCTSout = 1'b1 ; + end + else if (validraygroup == 1'b0 & cts == 1'b1 & passCTSin == 1'b1) + begin + temp_cts = 1'b0 ; + temp_passCTSout = 1'b1 ; + end + + end + 1 : + begin + if ((passCTSin == cts) & (cts == 1'b1)) + begin + next_state = 2 ; + temp_busy = 1'b1 ; + end + else if (passCTSin == cts) + begin + next_state = 0 ; + temp_busy = 1'b0 ; + end + else + begin + next_state = 1 ; + temp_busy = 1'b0 ; + end + + temp_statepeek = 5'b00010 ; + // + if (passCTSin == cts) + begin + temp_passCTSout = 1'b0 ; + end + + end + 2 : + begin + if (wanttriID == 1'b1) + begin + next_state = 3 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 2 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b00011 ; + // + temp_resetcount = 3'b100 ; + temp_l0reset = 1'b1 ; + temp_addr = 0; + temp_startAddr = 0; + temp_boundNodeIDout = 0; + temp_baseaddress = 0; + temp_hitmask = 1; + temp_hit1 = 1'b0 ; + temp_hit2 = 1'b0 ; + temp_hit3 = 1'b0 ; + end + 3 : + begin + if ((addr - startAddr >= 1) & (addr - startAddr != 49)) + begin + raygroupid = 2'b00 ; + end + next_state = 4 ; + temp_busy = 1'b1 ; + if (resetcount == 5) + begin + raygroupwe = 1'b1 ; + end + enablenear = 1'b1 ; + temp_statepeek = 5'b00100 ; + // + if ((addr - startAddr != 48) & (addr - startAddr != 49)) + begin + temp_triIDvalid = 1'b1 ; + end + temp_triID = {4'b0000, addr} ; + end + 4 : + begin + if (addr - startAddr == 49) + begin + next_state = 6 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 5 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b00101 ; + end + 5 : + begin + next_state = 3 ; + temp_busy = 1'b1 ; + + temp_statepeek = 5'b00111 ; + // + temp_addr = addr + 1 ; + if (resetcount == 5) + begin + temp_resetcount = 3'b000 ; + end + else + begin + temp_resetcount = resetcount + 1 ; + end + + end + 6 : + begin + if (passCTSin == 1'b1 & cts == 1'b1) + begin + next_state = 7; + temp_busy = 1'b1 ; + end + else if (done == 2'b00 & cts == 1'b0) + begin + next_state = 8; + temp_busy = 1'b1 ; + end + else if (done == 2'b00 & cts == 1'b1) + begin + next_state = 9; + temp_busy = 1'b1 ; + end + else + begin + next_state = 6; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01001 ; + // + if (passCTSin == 1'b1 & cts == 1'b1) + begin + temp_cts = 1'b0 ; + temp_passCTSout = 1'b1 ; + end + else if (done == 2'b00 & cts == 1'b0) + begin + temp_cts = 1'b1 ; + temp_passCTSout = 1'b1 ; + end + + end + 7 : + begin + if (passCTSin == 0) + begin + next_state = 6; + temp_busy = 1'b1 ; + end + else + begin + next_state = 7; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01001 ; + // + if (passCTSin == 1'b0) + begin + temp_passCTSout = 1'b0 ; + end + + end + 8 : + begin + if (passCTSin == 1) + begin + next_state = 9; + temp_busy = 1'b1 ; + end + else + begin + next_state = 8 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01010 ; + // + if (passCTSin == 1'b1) + begin + temp_passCTSout = 1'b0 ; + end + end + 9 : + begin + if (lempty == 1'b1) + begin + next_state = 0 ; + temp_busy = 1'b0 ; + bcvalid = 1'b1 ; + end + else if (ldataready == 1'b1 & llevel == 2'b10) + begin + next_state = 10 ; + temp_busy = 1'b1 ; + end + else if (ldataready == 1'b1 & wanttriID == 1'b1) + begin + next_state = 3 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01011 ; + // + temp_resetcount = 3'b100 ; + temp_baseaddress = llevel + 1 ; + // boundNodeIDout = (lBoundNodeID+1)(6 downto 0) & "000"; + //boundNodeIDout = {(lboundNodeID + 1)[6:0], 3'b000} ; + temp_boundNodeIDout = {lboundNodeID[6:0], 3'b000} ; + // temp_addr = (((lBoundNodeID+1)(7 downto 0) & "0000")+ + // ((lBoundNodeID+1)(6 downto 0) & "00000")) (11 downto 0); + //temp_addr = (({(lboundNodeID + 1)[7:0], 4'b0000}) + ({(lboundNodeID + 1)[6:1], 5'b00000}))[11:0] ; + temp_addr = (({lboundNodeID[7:0], 4'b0000}) + ({lboundNodeID[6:1], 5'b00000})); + // startaddr = (((lBoundNodeID+1)(7 downto 0) & "0000")+ + // ((lBoundNodeID+1)(6 downto 0) & "00000")) (11 downto 0); + //startAddr = (({(lboundNodeID + 1), 4'b0000}) + ({(lboundNodeID + 1), 5'b00000})) ; + temp_startAddr = (({lboundNodeID, 4'b0000}) + ({lboundNodeID, 5'b00000})) ; + if (ldataready == 1'b1 & (wanttriID == 1'b1 | llevel == 2'b10)) + begin + temp_lack = 1'b1 ; + temp_l0reset = 1'b1 ; + end + + if (ldataready == 1'b1 & llevel == 2'b10) + begin + temp_addrind = lboundNodeID - 72 ; + temp_addrindvalid = 1'b1 ; + end + end + 10 : + begin + if (dataindvalid == 1'b1) + begin + next_state = 11 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 10 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01100 ; + // + + temp_tladdr = dataind[17:0] ; + temp_count = dataind[31:18] ; + if (dataindvalid == 1'b1) + begin + temp_addrindvalid = 1'b0 ; + temp_tladdrvalid = 1'b1 ; + end + + end + 11 : + begin + if (count == 0 | count == 1) + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + else if (wanttriID == 1'b1 & tldatavalid == 1'b1) + begin + next_state = 12 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 11 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01101 ; + // + + temp_triDatalatch = tldata ; + temp_subcount = 2'b10 ; + temp_maskcount = 2'b00 ; + if ((wanttriID == 1'b1 & tldatavalid == 1'b1) | (count == 0 | count == 1)) + begin + temp_tladdr = tladdr + 1 ; + temp_tladdrvalid = 1'b0 ; + end + + end + 12 : + begin + if (count != 0) + begin + next_state = 13 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 15 ; + temp_busy = 1'b1 ; + end + if (subcount == 2'b01) + begin + raygroupid = 2'b00 ; + end + else + begin + raygroupid = 2'b00 ; + end + enablenear = 1'b0 ; + if (subcount == 2'b01 | count == 0) + begin + raygroupwe = 1'b1 ; + end + + temp_statepeek = 5'b01110 ; + // + + if (maskcount == 2'b11) + begin + // triID = triDataLatch(15 downto 0); + temp_triID = triDatalatch[15:0] ; + end + else if (maskcount == 2'b10) + begin + // triID = triDataLatch(31 downto 16); + temp_triID = triDatalatch[31:16] ; + end + else if (maskcount == 2'b01) + begin + // triID = triDataLatch(47 downto 32); + temp_triID = triDatalatch[47:32] ; + end + else + begin + // triID = triDataLatch(63 downto 48); + temp_triID = triDatalatch[63:48] ; + end + if (count != 0) + begin + temp_count = count - 1 ; + if (count != 1) + begin + temp_triIDvalid = 1'b1 ; + end + + if (maskcount == 2'b01) + begin + temp_tladdrvalid = 1'b1 ; + end + end + + end + 13 : + begin + next_state = 14 ; + temp_busy = 1'b1 ; + + temp_statepeek = 5'b01111 ; + end + 14 : + begin + next_state = 12 ; + temp_busy = 1'b1 ; + temp_statepeek = 5'b10000 ; + // + + if (subcount != 0) + begin + temp_subcount = subcount - 1 ; + end + if (maskcount == 2'b11) + begin + temp_tladdr = tladdr + 1 ; + temp_tladdrvalid = 1'b0 ; + temp_triDatalatch = tldata ; + end + temp_maskcount = maskcount + 1 ; + + end + 15 : + begin + if ((newdata == 1'b0 | resultID != 2'b00) & cts == 1'b1 & passCTSin == 1'b1) + begin + next_state = 16 ; + temp_busy = 1'b1 ; + end + else if (newdata == 1'b1 & resultID == 2'b00) + begin + next_state = 18 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 15 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10001 ; + // + temp_tladdr = 0; + temp_tladdrvalid = 0; + if ((newdata == 0) | (resultID < 2'b00) & (passCTSin == 1)) + begin + temp_cts = 0; + temp_passCTSout = 1; + end + + end + 16 : + begin + if (newdata == 1'b1 & resultID == 2'b00) + begin + next_state = 17 ; + temp_busy = 1'b1 ; + end + else if (passCTSin == 1'b0) + begin + next_state = 15 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 16 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10010 ; + // + if ((passCTSin == 0) & ((newdata == 0) | (resultID == 1))) + begin + temp_passCTSout = 0; + end + + end + 17 : + begin + if (passCTSin == 1'b0) + begin + next_state = 18 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 17 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10011 ; + // + if (passCTSin == 0) + begin + temp_passCTSout = 0; + end + + + end + 18 : + begin + if (cts == 1'b0 & (((hitmask[0]) == 1'b1 & hit1in == 1'b0) | ((hitmask[1]) == 1'b1 & hit2in == 1'b0) | ((hitmask[2]) == 1'b1 & hit3in == 1'b0))) + begin + next_state = 19 ; + temp_busy = 1'b1 ; + end + else if (cts == 1'b1 & (((hitmask[0]) == 1'b1 & hit1in == 1'b0) | ((hitmask[1]) == 1'b1 & hit2in == 1'b0) | ((hitmask[2]) == 1'b1 & hit3in == 1'b0))) + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 0 ; + temp_busy = 1'b0 ; + bcvalid = 1'b1 ; + end + temp_statepeek = 5'b10100 ; + // + + + + if (hit1in == 1'b1 & (hitmask[0]) == 1'b1) + begin + temp_t1 = t1in; + temp_u1 = u1in; + temp_v1 = v1in; + temp_id1 = id1in; + temp_hit1 = 1'b1; + temp_hitmask[0] = 1'b0 ; + end + if (hit2in == 1'b1 & (hitmask[1]) == 1'b1) + begin + temp_t2 = t2in ; + temp_u2 = u2in ; + temp_v2 = v2in ; + temp_id2 = id2in ; + temp_hit2 = 1'b1 ; + temp_hitmask[1] = 1'b0 ; + end + if (hit3in == 1'b1 & (hitmask[2]) == 1'b1) + begin + temp_t3 = t3in ; + temp_u3 = u3in ; + temp_v3 = v3in ; + temp_id3 = id3in ; + temp_hit3 = 1'b1 ; + temp_hitmask[2] = 1'b0 ; + end + if (cts == 1'b0 & (((hitmask[0]) == 1'b1 & hit1in == 1'b0) | ((hitmask[1]) == 1'b1 & hit2in == 1'b0) | ((hitmask[2]) == 1'b1 & hit3in == 1'b0))) + begin + temp_passCTSout = 1'b1 ; + temp_cts = 1'b1 ; + end + + end + 19 : + begin + if (passCTSin == 1'b0) + begin + next_state = 19 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10101 ; + // + if (passCTSin == 1'b1) + begin + temp_passCTSout = 1'b0 ; + end + + end + endcase + end +endmodule + + + + + + // A debugging circuit that allows a single cycle pulse to be + // generated by through the ports package + module onlyonecycle (trigger, output_xhdl0, globalreset, clk); + + input trigger; + output output_xhdl0; + reg output_xhdl0; + input globalreset; + input clk; + + reg[1:0] state; + reg[1:0] next_state; + reg[0:0] count; + reg[0:0] temp_count; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + count <= 0 ; + + end + else + begin + state <= next_state ; + count <= temp_count; + end + end + + always @(*) + begin + case (state) + 0 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + temp_count = 1 - 1 ; + end + 1 : + begin + output_xhdl0 = 1'b1 ; + if (count == 0) + begin + next_state = 2 ; + end + else + + begin + + next_state = 1 ; + end + temp_count = count - 1 ; + end + 2 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + + end + end + //Before adding default this could infer latches, so + //defaulting to holding previous state preserves deisgn intent + default: next_state = state; + + endcase + end + endmodule + + + + + + + + + + + module vblockramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, datain, addr, addrvalid, data, datavalid, globalreset, clk); + + + output want_addr; + reg want_addr; + input addr_ready; + input[10 - 1:0] addrin; + output want_data; + reg want_data; + input data_ready; + input[32 - 1:0] datain; + + input[10 - 1:0] addr; + input addrvalid; + output[32 - 1:0] data; + reg[32 - 1:0] data; + output datavalid; + reg datavalid; + input globalreset; + input clk; + + reg[2:0] state; + reg[2:0] next_state; + reg[10 - 1:0] waddr; + wire[10 - 1:0] saddr; + wire[32 - 1:0] dataout; + reg we; +reg [32 - 1:0]temp_data; +reg [10 - 1:0]temp_waddr ; +reg temp_datavalid; + + assign saddr = (state != 0) ? waddr : addr ; + + spramblock ramblock(we, saddr, datain, dataout, clk); + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + waddr <= 0; + data <= 0; + datavalid <= 1'b0 ; + end + else + + begin + state <= next_state ; + data <= temp_data; + waddr <= temp_waddr ; + datavalid <= temp_datavalid; + end + end + + always @(*) + + begin + next_state = state; + temp_data = data; + temp_waddr = waddr; + temp_datavalid = datavalid; + // For the unregistered values, we have to pick default behavior; + // these values are used in enough other defined states to appear to + // be reasonable fallbacks, but putting this here does change design + // intent: + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + case (state) + 0 : + begin + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + + else if (addrvalid == 1'b1 & datavalid == 1'b0) + begin + next_state = 5 ; + end + else + begin + next_state = 0 ; + end + if (addr_ready == 1'b1) + begin + temp_waddr = addrin ; + end + if (addrvalid == 1'b0) + begin + temp_datavalid = 1'b0 ; + + end + + end + 5 : + begin + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + next_state = 0 ; + + temp_data = dataout ; + + temp_datavalid = 1'b1 ; + + end + 1 : + begin + we = 1'b0 ; + want_addr = 1'b0 ; + want_data = 1'b1 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 2 ; + + end + end + 2 : + begin + want_addr = 1'b1 ; + want_data = 1'b1 ; + if (addr_ready == 1'b1) + begin + next_state = 4 ; + end + else if (data_ready == 1'b1) + begin + we = 1'b1 ; + + next_state = 3 ; + end + else + begin + next_state = 2 ; + end + if (data_ready == 1'b1) + begin + temp_waddr = waddr + 1 ; + end + + end + 3 : + begin + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (data_ready == 1'b1) + begin + next_state = 3 ; + + end + else + begin + next_state = 2 ; + end + end + 4 : + begin + we = 1'b0 ; + want_data = 1'b0 ; + want_addr = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 4 ; + + end + else + begin + next_state = 0 ; + end + end + endcase + end + endmodule + //----------------------------------------------------- + // Single Ported Ram Modual w/Registered Output -- + // - Synpify should infer ram from the coding style -- + // - Depth is the number of bits of address -- + // the true depth is 2**depth -- + + //----------------------------------------------------- + + //modifying this to black box ram implementation + + + module spramblock (we, addr, datain, dataout, clk); + + input we; + input[10 - 1:0] addr; + input[32 - 1:0] datain; + output[32 - 1:0] dataout; + wire[32 - 1:0] dataout; + input clk; + + + +single_port_ram + # (.ADDR_WIDTH(10), .DATA_WIDTH(32)) +new_ram( + .clk (clk), + .we(we), + .data(datain), + .out(dataout), + .addr(addr) + ); + + + endmodule + + + + + + + + + module sramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, datain, addr, addrvalid, data, datavalid, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, clk, statepeek); + + output want_addr; + reg want_addr; + input addr_ready; + input[17:0] addrin; + output want_data; + reg want_data; + input data_ready; + input[63:0] datain; + input[17:0] addr; + input addrvalid; + + output[63:0] data; + reg[63:0] data; + reg[63:0] temp_data; + output datavalid; + reg datavalid; + reg temp_datavalid; + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + output[18:0] tm3_sram_addr; + reg[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + reg[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + + reg[1:0] tm3_sram_oe; + output tm3_sram_adsp; + reg tm3_sram_adsp; + input globalreset; + input clk; + output[2:0] statepeek; + reg[2:0] statepeek; + reg[2:0] temp_statepeek; + + reg[2:0] state; + reg[2:0] next_state; + reg[17:0] waddress; + reg[17:0] temp_waddress; + + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + + begin + state <= 0 ; + waddress <= 0; + data <= 0; + datavalid <= 1'b0 ; + end + else + begin + state <= next_state ; + statepeek <= temp_statepeek; + data <=temp_data; + datavalid <=temp_datavalid; + waddress <= temp_waddress; + end + end + + always @(*) + begin + next_state = state; + temp_statepeek = statepeek; + temp_data = data; + temp_datavalid = datavalid; + temp_waddress = waddress; + // For the unregistered values, we have to pick default behavior; + // these values are used in enough other defined states to appear to + // be reasonable fallbacks, but putting this here does change design + // intent: + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; + case (state) + 0 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else if (addrvalid == 1'b1 & datavalid == 1'b0) + begin + next_state = 5 ; + + tm3_sram_addr = {1'b0, addr} ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_oe = 2'b01 ; + end + + else + begin + next_state = 0 ; + end + + temp_statepeek = 3'b001 ; + if (addr_ready == 1'b1) + begin + temp_waddress = addrin ; + end + if (addrvalid == 1'b0) + begin + temp_datavalid = 1'b0 ; + end + + end + 1 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b0 ; + want_data = 1'b1 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 2 ; + end + + temp_statepeek = 3'b010 ; + end + 2 : + begin + tm3_sram_oe = 2'b11 ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + tm3_sram_addr = {1'b0, waddress} ; + tm3_sram_data_xhdl0 = datain ; + if (addr_ready == 1'b1) + begin + next_state = 4 ; + end + else if (data_ready == 1'b1) + begin + + tm3_sram_we = 8'b00000000 ; + tm3_sram_adsp = 1'b0 ; + next_state = 3 ; + end + else + begin + next_state = 2 ; + end + temp_statepeek = 3'b011 ; + if (data_ready == 1'b1) + + begin + temp_waddress = waddress + 1 ; + end + + end + 3 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (data_ready == 1'b1) + + begin + next_state = 3 ; + end + else + begin + next_state = 2 ; + end + temp_statepeek = 3'b100 ; + end + 4 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_data = 1'b0 ; + want_addr = 1'b0 ; + if (addr_ready == 1'b1) + + begin + next_state = 4 ; + end + else + begin + next_state = 0 ; + end + temp_statepeek = 3'b101 ; + end + 5 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; + next_state = 0 ; + temp_statepeek = 3'b110 ; + temp_data = tm3_sram_data_in ; + temp_datavalid = 1'b1 ; + + end + + + endcase + end + endmodule + + + + + + + + + + + + + +module resultinterface (t1b, t2b, t3b, u1b, u2b, u3b, v1b, v2b, v3b, id1b, id2b, id3b, hit1b, hit2b, hit3b, resultID, newdata, resultready, resultdata, globalreset, clk); + + output[31:0] t1b; + reg[31:0] t1b; + output[31:0] t2b; + reg[31:0] t2b; + output[31:0] t3b; + reg[31:0] t3b; + output[15:0] u1b; + reg[15:0] u1b; + output[15:0] u2b; + reg[15:0] u2b; + + output[15:0] u3b; + reg[15:0] u3b; + output[15:0] v1b; + reg[15:0] v1b; + output[15:0] v2b; + reg[15:0] v2b; + output[15:0] v3b; + reg[15:0] v3b; + output[15:0] id1b; + reg[15:0] id1b; + output[15:0] id2b; + reg[15:0] id2b; + + output[15:0] id3b; + reg[15:0] id3b; + output hit1b; + reg hit1b; + output hit2b; + reg hit2b; + output hit3b; + reg hit3b; + output[1:0] resultID; + reg[1:0] resultID; + output newdata; + reg newdata; + + reg[31:0] temp_t1b; + reg[31:0] temp_t2b; + reg[31:0] temp_t3b; + reg[15:0] temp_u1b; + reg[15:0] temp_u2b; + reg[15:0] temp_u3b; + reg[15:0] temp_v1b; + reg[15:0] temp_v2b; + reg[15:0] temp_v3b; + reg[15:0] temp_id1b; + reg[15:0] temp_id2b; + reg[15:0] temp_id3b; + reg temp_hit1b; + reg temp_hit2b; + reg temp_hit3b; + reg[1:0] temp_resultID; + reg temp_newdata; + + input resultready; + input[31:0] resultdata; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + t1b <= 0; + t2b <= 0; + t3b <= 0; + u1b <= 0; + u2b <= 0; + u3b <= 0; + v1b <= 0; + + v2b <= 0; + v3b <= 0; + id1b <= 0; + id2b <= 0; + id3b <= 0; + hit1b <= 1'b0 ; + hit2b <= 1'b0 ; + hit3b <= 1'b0 ; + resultID <= 0; + newdata <= 1'b0 ; + end + else + begin + state <= next_state ; + + t1b <= temp_t1b; + newdata <= temp_newdata; + u1b <= temp_u1b; + v1b <= temp_v1b; + id1b <= temp_id1b; + hit1b <= temp_hit1b; + resultID <= temp_resultID; + t2b <= temp_t2b; + u2b <= temp_u2b; + id2b <= temp_id2b; + t3b <= temp_t3b; + u3b <= temp_u3b; + v3b <= temp_v3b; + id3b <= temp_id3b; + hit3b <= temp_hit3b; + v2b <= temp_v2b; + hit2b <= temp_hit2b; + end + end + + always @(*) + begin + next_state = state ; + temp_t1b = t1b; + temp_newdata = newdata; + temp_u1b = u1b; + temp_v1b = v1b; + temp_id1b = id1b; + temp_hit1b = hit1b; + temp_resultID = resultID; + temp_t2b = t2b; + temp_u2b = u2b; + temp_id2b = id2b; + temp_t3b = t3b; + temp_u3b = u3b; + temp_v3b = v3b; + temp_id3b = id3b; + temp_hit3b = hit3b; + temp_v2b = v2b; + temp_hit2b = hit2b; + case (state) + 0 : + begin + + if (resultready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + temp_newdata = 1'b0 ; + if (resultready == 1'b1) + begin + temp_t1b = resultdata ; + end + + end + 1 : + begin + next_state = 2 ; + temp_newdata = 1'b0 ; + temp_u1b = resultdata[31:16] ; + temp_v1b = resultdata[15:0] ; + end + 2 : + begin + next_state = 3 ; + temp_newdata = 1'b0 ; + temp_id1b = resultdata[15:0] ; + temp_hit1b = resultdata[16] ; + temp_resultID = resultdata[18:17] ; + end + 3 : + begin + + next_state = 4 ; + temp_newdata = 1'b0 ; + temp_t2b = resultdata ; + end + 4 : + begin + next_state = 5 ; + temp_newdata = 1'b0 ; + temp_u2b = resultdata[31:16] ; + temp_v2b = resultdata[15:0] ; + end + 5 : + begin + next_state = 6 ; + temp_newdata = 1'b0 ; + temp_id2b = resultdata[15:0] ; + temp_hit2b = resultdata[16] ; + end + 6 : + begin + + next_state = 7 ; + temp_newdata = 1'b0 ; + temp_t3b = resultdata ; + end + 7 : + begin + next_state = 8 ; + temp_newdata = 1'b0 ; + temp_u3b = resultdata[31:16] ; + temp_v3b = resultdata[15:0] ; + end + 8 : + begin + next_state = 0 ; + temp_id3b = resultdata[15:0] ; + temp_hit3b = resultdata[16] ; + temp_newdata = 1'b1 ; + end + endcase + end + + endmodule + module rayinterface (raygroup, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, globalreset, clk); + + input[1:0] raygroup; + input raygroupwe; + input[1:0] raygroupid; + input enablenear; + input[31:0] rgData; + input[3:0] rgAddr; + input[2:0] rgWE; + + input rgAddrValid; + output rgDone; + reg rgDone; + output[31:0] raydata; + reg[31:0] raydata; + output[3:0] rayaddr; + reg[3:0] rayaddr; + output[2:0] raywe; + reg[2:0] raywe; + input globalreset; + input clk; + + + reg[31:0] rgDatal; + reg[3:0] rgAddrl; + reg[2:0] rgWEl; + reg rgAddrValidl; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + raydata <= 0; + rayaddr <= 0; + raywe <= 0; + + rgDone <= 1'b0 ; + rgDatal <= 0; + rgAddrl <= 0; + rgWEl <= 0; + rgAddrValidl <= 1'b0 ; + end + else + begin + rgDatal <= rgData ; // Latch interchip signals + rgAddrl <= rgAddr ; // To Meet Timing + rgWEl <= rgWE ; + + rgAddrValidl <= rgAddrValid ; + + if (raygroupwe == 1'b1) + begin + raydata[0] <= enablenear ; + raydata[31:1] <= 0; + raywe <= 3'b111 ; + rayaddr <= {raygroupid, raygroup} ; + if (rgAddrValidl == 1'b0) + rgDone <= 1'b0 ; + end + else if (rgAddrValidl == 1'b1 & rgDone == 1'b0) + begin + raydata <= rgDatal ; + raywe <= rgWEl ; + rayaddr <= rgAddrl ; + rgDone <= 1'b1 ; + end + else + begin + raywe <= 0; + end + end + end + endmodule + + + + +module sortedstack (keyin, datain, write, reset, peekdata, globalreset, clk); + + input[32 - 1:0] keyin; + input[13 - 1:0] datain; + input write; + input reset; + output[13 * 8 - 1:0] peekdata; + + wire[13 * 8 - 1:0] peekdata; + wire big_reset; + input globalreset; + input clk; + + reg[32 - 1:0] key0; + reg[32 - 1:0] key1; + reg[32 - 1:0] key2; + reg[32 - 1:0] key3; + reg[32 - 1:0] key4; + reg[32 - 1:0] key5; + reg[32 - 1:0] key6; + reg[32 - 1:0] key7; + reg[13 - 1:0] data0; + reg[13 - 1:0] data1; + reg[13 - 1:0] data2; + reg[13 - 1:0] data3; + reg[13 - 1:0] data4; + reg[13 - 1:0] data5; + reg[13 - 1:0] data6; + reg[13 - 1:0] data7; + reg full0; + reg full1; + reg full2; + reg full3; + reg full4; + reg full5; + reg full6; + reg full7; + reg[2:0] location; + + assign peekdata[(0 + 1) * (13) - 1:0 * (13)] = ((full0) == 1'b1) ? data0 : 0; + assign peekdata[(1 + 1) * (13) - 1:1 * (13)] = ((full1) == 1'b1) ? data1 : 0; + assign peekdata[(2 + 1) * (13) - 1:2 * (13)] = ((full2) == 1'b1) ? data2 : 0; + assign peekdata[(3 + 1) * (13) - 1:3 * (13)] = ((full3) == 1'b1) ? data3 : 0; + assign peekdata[(4 + 1) * (13) - 1:4 * (13)] = ((full4) == 1'b1) ? data4 : 0; + assign peekdata[(5 + 1) * (13) - 1:5 * (13)] = ((full5) == 1'b1) ? data5 : 0; + assign peekdata[(6 + 1) * (13) - 1:6 * (13)] = ((full6) == 1'b1) ? data6 : 0; + assign peekdata[(7 + 1) * (13) - 1:7 * (13)] = ((full7) == 1'b1) ? data7 : 0; + + // Select the proper insertion point + always @(*) + begin + +/* PAJ -- changed for loops */ + if ((keyin < key0) | ((full0) == 1'b0)) + begin + location = 0 ; + end + else if ((keyin < key1) | ((full1) == 1'b0)) + begin + location = 1 ; + end + else if ((keyin < key2) | ((full2) == 1'b0)) + begin + location = 2 ; + end + else if ((keyin < key3) | ((full3) == 1'b0)) + begin + location = 3 ; + end + else if ((keyin < key4) | ((full4) == 1'b0)) + begin + location = 4 ; + end + else if ((keyin < key5) | ((full5) == 1'b0)) + begin + location = 5 ; + end + else if ((keyin < key6) | ((full6) == 1'b0)) + begin + location = 6 ; + end + else + begin + location = 7; + end + end + + assign big_reset = globalreset | reset; + always @(posedge clk) + begin + if (big_reset == 1'b1) + begin + full0 <= 1'b0 ; + key0 <= 0; + data0 <= 0; + full1 <= 1'b0 ; + key1 <= 0; + data1 <= 0; + full2 <= 1'b0 ; + key2 <= 0; + data2 <= 0; + full3 <= 1'b0 ; + key3 <= 0; + data3 <= 0; + full4 <= 1'b0 ; + key4 <= 0; + data4 <= 0; + full5 <= 1'b0 ; + key5 <= 0; + data5 <= 0; + full6 <= 1'b0 ; + key6 <= 0; + data6 <= 0; + full7 <= 1'b0 ; + key7 <= 0; + data7 <= 0; + end + else + begin + if (write == 1'b1) + begin + if (location == 0) + begin + key0 <= keyin; + data0 <= datain; + full0 <= 1'b1; + key1 <= key0; + data1 <= data0; + full1 <= full0; + key2 <= key1; + data2 <= data1; + full2 <= full1; + key3 <= key2; + data3 <= data2; + full3 <= full2; + key4 <= key3; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 1) + begin + key1 <= keyin; + data1 <= datain; + full1 <= 1'b1; + key2 <= key1; + data2 <= data1; + full2 <= full1; + key3 <= key2; + data3 <= data2; + full3 <= full2; + key4 <= key3; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 2) + begin + key2 <= keyin; + data2 <= datain; + full2 <= 1'b1; + key3 <= key2; + data3 <= data2; + full3 <= full2; + key4 <= key3; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 2) + begin + key3 <= keyin; + data3 <= datain; + full3 <= 1'b1; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 4) + begin + key4 <= keyin; + data4 <= datain; + full4 <= 1'b1; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 5) + begin + key5 <= keyin; + data5 <= datain; + full5 <= 1'b1; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 6) + begin + key6 <= keyin; + data6 <= datain; + full6 <= 1'b1; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 7) + begin + key7 <= keyin; + data7 <= datain; + full7 <= 1'b1; + end + end + end +end +endmodule + + + + +module listhandler (dataarrayin, commit, hitmask, ack, boundnodeID, level, empty, dataready, reset, globalreset, clk, peekoffset0, peekoffset1, peekoffset2, peekhit, peekstate); + + input[8 * 13 - 1:0] dataarrayin; + input commit; + input[2:0] hitmask; + input ack; + output[9:0] boundnodeID; + wire[9:0] boundnodeID; + output[1:0] level; + wire[1:0] level; + + output empty; + wire empty; + output dataready; + wire dataready; + input reset; + input globalreset; + input clk; + output[2:0] peekoffset0; + wire[2:0] peekoffset0; + output[2:0] peekoffset1; + wire[2:0] peekoffset1; + output[2:0] peekoffset2; + + wire[2:0] peekoffset2; + output peekhit; + wire peekhit; + output[1:0] peekstate; + reg[1:0] peekstate; + reg[1:0] temp_peekstate; + + reg[1:0] next_state; + reg[1:0] state; + reg[1:0] readlevel; + + reg[1:0] writelevel; + reg[2:0] offset0; + reg[2:0] offset1; + reg[2:0] offset2; + reg[4:0] address; + wire we; + reg[12:0] datain; + wire[12:0] dataout; + reg[2:0] lvempty; + reg busy; + reg temp_busy; + reg[2:0] temp_lvempty; + reg[1:0] temp_readlevel; + reg[1:0] temp_writelevel; + reg[2:0] temp_offset0; + reg[2:0] temp_offset1; + reg[2:0] temp_offset2; + + // Debug Stuff + + assign peekoffset0 = offset0 ; + assign peekoffset1 = offset1 ; + assign peekoffset2 = offset2 ; + assign peekhit = ((datain[10]) == 1'b1 | (datain[11]) == 1'b1 | (datain[12]) == 1'b1) ? 1'b1 : 1'b0 ; + + // Real Code + + spram ram(we, dataout, datain, clk); + + assign level = readlevel ; + assign boundnodeID = dataout[9:0] ; + + assign empty = (lvempty == 3'b111 & busy == 1'b0) ? 1'b1 : 1'b0 ; + assign dataready = ((((dataout[10]) == 1'b1 & (hitmask[0]) == 1'b1) | ((dataout[11]) == 1'b1 & (hitmask[1]) == 1'b1) | ((dataout[12]) == 1'b1 & (hitmask[2]) == 1'b1)) & (empty == 1'b0) & (busy == 1'b0)) ? 1'b1 : 1'b0 ; + + always @(*) + begin + address[4:3] = readlevel ; + + if (address[4:3] == 2'b00) + begin + address[2:0] = offset0 ; + end + else if (address[4:3] == 2'b01) + begin + + address[2:0] = offset1 ; + end + else if (address[4:3] == 2'b10) + begin + address[2:0] = offset2 ; + end + else + begin + address[2:0] = 0; + end + end + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + lvempty <= 1; + busy <= 1'b0 ; + readlevel <= 2'b00 ; + writelevel <= 2'b00 ; + offset0 <= 3'b000 ; + offset1 <= 3'b000 ; + offset2 <= 3'b000 ; + + end + else + begin + state <= next_state ; + peekstate <= temp_peekstate ; + busy <= temp_busy; + lvempty <= temp_lvempty; + readlevel <= temp_readlevel; + writelevel <= temp_writelevel; + offset0 <= temp_offset0; + offset1 <= temp_offset1; + offset2 <= temp_offset2; + end + end + + //for we and datain we cannot preserve original functionality and stil + //eliminate latches because there were no flops for them in the original + //code. The best we can do is observe that nonzero, valid behavior + //is defined only when state == 2'b01. Since putting these behind flops + //would change their timing, build a mux and set we and datain to zero + //for previously undefined states + assign we = (state == 2'b01); + always @(*) begin + if (state == 2'b01) begin + case(address[2:0]) + 3'b000: datain = dataarrayin[0+:13]; + 3'b001: datain = dataarrayin[13+:13]; + 3'b010: datain = dataarrayin[26+:13]; + 3'b011: datain = dataarrayin[39+:13]; + 3'b100: datain = dataarrayin[52+:13]; + 3'b101: datain = dataarrayin[65+:13]; + 3'b110: datain = dataarrayin[78+:13]; + 3'b111: datain = dataarrayin[91+:13]; + endcase + end + else begin + datain = 'h0; + end + end + + always @(*) + begin + + // Note that throughout this case statement it is necessary to + // add else statements that were not previously present in order + // to prevent latch inference. To preserve previous behavior, + // these else statements should always set the value equal to + // previous state + case (state) + 2'b00 : + begin + temp_peekstate = 2'b01 ; + + if (reset == 1'b1) + begin + temp_busy = 1'b0 ; + temp_lvempty = 1; + temp_readlevel = 2'b00 ; + + temp_writelevel = 2'b00 ; + temp_offset0 = 3'b000 ; + temp_offset1 = 3'b000 ; + temp_offset2 = 3'b000 ; + end + else if (commit == 1'b1) + begin + temp_busy = 1'b1 ; + if (writelevel == 2'b00) + begin + temp_offset0 = 3'b000 ; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + + else if (writelevel == 2'b01) + begin + temp_offset1 = 3'b000 ; + temp_offset0 = offset0; + temp_offset2 = offset2; + end + else if (writelevel == 2'b10) + begin + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = 3'b000 ; + end + else begin + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + temp_readlevel = writelevel ; + temp_writelevel = writelevel; + temp_lvempty = lvempty; + end + + else if (ack == 1'b1) + begin + temp_writelevel = readlevel + 1 ; + temp_readlevel = readlevel; + temp_busy = 1'b1 ; // This will ensure that align skips one + temp_lvempty = lvempty; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + else begin + temp_busy = busy; + temp_lvempty = lvempty; + temp_readlevel = readlevel; + temp_writelevel = writelevel; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + temp_readlevel = readlevel; + temp_writelevel = writelevel; + end + end + 2'b01 : + begin + temp_peekstate = 2'b10 ; + + if (readlevel == 2'b00) + begin + temp_offset0 = offset0 + 1 ; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + else if (readlevel == 2'b01) + begin + temp_offset1 = offset1 + 1 ; + temp_offset0 = offset0; + temp_offset2 = offset2; + end + else if (readlevel == 2'b10) + begin + temp_offset2 = offset2 + 1 ; + temp_offset0 = offset0; + temp_offset1 = offset1; + end + else + begin + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + + if (address[2:0] == 3'b111) + begin + temp_busy = 1'b0 ; + end + else begin + temp_busy = busy; + end + + if ((datain[10]) == 1'b1 | (datain[11]) == 1'b1 | (datain[12]) == 1'b1) + begin + if (readlevel == 2'b00) + begin + temp_lvempty[0] = 1'b0 ; + temp_lvempty[1] = lvempty[1] ; + temp_lvempty[2] = lvempty[2] ; + end + else if (readlevel == 2'b01) + begin + temp_lvempty[1] = 1'b0 ; + temp_lvempty[0] = lvempty[0] ; + temp_lvempty[2] = lvempty[2] ; + end + else if (readlevel == 2'b10) + begin + temp_lvempty[2] = 1'b0 ; + temp_lvempty[0] = lvempty[0] ; + temp_lvempty[1] = lvempty[1] ; + end + else begin + temp_lvempty = lvempty; + end + end + else begin + temp_lvempty = lvempty; + end + + temp_readlevel = readlevel; + temp_writelevel = writelevel; + + end + 2'b10 : + begin + if (empty == 1'b0 & dataready == 1'b0) + temp_peekstate = 2'b11 ; + else + temp_peekstate = peekstate; + + temp_busy = 1'b0 ; + + if (empty == 1'b0 & dataready == 1'b0) + begin + if (readlevel == 2'b00) + begin + if (offset0 == 3'b111) + begin + temp_lvempty[0] = 1'b1 ; + temp_lvempty[1] = lvempty[1]; + temp_lvempty[2] = lvempty[2]; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + else + begin + temp_lvempty = lvempty; + temp_offset0 = offset0 + 1 ; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + temp_readlevel = readlevel; + temp_writelevel = writelevel; + end + else if (readlevel == 2'b01) + begin + if (offset1 == 3'b111) + begin + temp_lvempty[1] = 1'b1 ; + temp_lvempty[0] = lvempty[0]; + temp_lvempty[2] = lvempty[2]; + temp_readlevel = 2'b00 ; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + else + begin + temp_offset1 = offset1 + 1 ; + temp_offset0 = offset0; + temp_offset2 = offset2; + temp_lvempty = lvempty; + temp_readlevel = readlevel; + end + temp_writelevel = writelevel; + end + else if (readlevel == 2'b10) + begin + if (offset2 == 3'b111) + begin + temp_lvempty[2] = 1'b1 ; + temp_lvempty[1:0] = lvempty[1:0]; + if ((lvempty[1]) == 1'b1) + begin + temp_readlevel = 2'b00 ; + end + else + begin + temp_readlevel = 2'b01 ; + end + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + else + begin + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2 + 1 ; + temp_lvempty = lvempty; + temp_readlevel = readlevel; + end + temp_writelevel = writelevel; + end + else + begin + temp_lvempty = lvempty; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + temp_readlevel = readlevel; + temp_writelevel = writelevel; + end + end + else + begin + temp_lvempty = lvempty; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + temp_readlevel = readlevel; + temp_writelevel = writelevel; + end + end + default: begin + // preserve original design intent by holding state, even if + // this behavior is not really sensical + temp_peekstate = peekstate ; + temp_busy = busy; + temp_lvempty = lvempty; + temp_readlevel = readlevel; + temp_writelevel = writelevel; + temp_offset0 = offset0; + temp_offset1 = offset1; + temp_offset2 = offset2; + end + endcase + + case (state) + 2'b00 : + begin + if (reset == 1'b1) + begin + next_state = 0 ; + end + else if (commit == 1'b1) + begin + next_state = 1 ; + end + else if ((ack == 1'b1) | (dataready == 1'b0 & empty == 1'b0)) + begin + next_state = 2 ; + end + else + begin + next_state = 0 ; + end + end + 2'b01 : + begin + if (address[2:0] == 3'b111) + begin + next_state = 2 ; + end + else + begin + next_state = 1 ; + end + end + 2'b10 : + begin + if (empty == 1'b0 & dataready == 1'b0) + begin + next_state = 2 ; + end + else + next_state = 0 ; + end + default: begin + // preserve original design intent by holding state, even if + // this behavior is not really sensical + next_state = state; + end + endcase +end +endmodule + + + + module spram (we, dataout, datain, clk); + + input we; + output[13 - 1:0] dataout; + wire[13 - 1:0] dataout; + input[13 - 1:0] datain; + input clk; + reg[13 - 1:0] temp_reg; + + reg[13 - 1:0] mem1; + reg[13 - 1:0] mem2; + + assign dataout = mem2 ; + + always @(posedge clk) + begin + temp_reg <= 0; + if (we == 1'b1) + begin + mem1 <= datain + temp_reg; + mem2 <= mem1; + end + end + endmodule + module resultcounter (resultID, newresult, done, reset, globalreset, clk); + + input[1:0] resultID; + input newresult; + output[1:0] done; + wire[1:0] done; + input reset; + input globalreset; + input clk; + + wire big_reset; + + reg[3:0] count; + reg[1:0] curr; + + assign done = (count == 0) ? curr : 2'b00 ; + assign big_reset = globalreset | reset; + + always @(posedge clk) + begin + if (big_reset == 1'b1) + begin + count <= 4'b1000 ; + curr <= 0; + end + else + begin + if ((resultID != 0) & (newresult == 1'b1) & (count != 0)) + begin + count <= count - 1 ; + curr <= resultID ; + end + end + end + endmodule + diff --git a/vtr_flow/benchmarks/verilog/ch_intrinsics.v b/vtr_flow/benchmarks/verilog/ch_intrinsics.v index 707eab4a97f..919263007ad 100755 --- a/vtr_flow/benchmarks/verilog/ch_intrinsics.v +++ b/vtr_flow/benchmarks/verilog/ch_intrinsics.v @@ -28,9 +28,10 @@ reg str_write_enable; reg [7:0] str_in; wire [7:0] str_out; -single_port_ram - # (.ADDR_WIDTH(5), .DATA_WIDTH(8)) -_str ( + +defparam _str.ADDR_WIDTH = 5; +defparam _str.DATA_WIDTH = 8; +single_port_ram _str ( .clk( clk ), .addr( str_address ), .we( str_write_enable ), @@ -42,33 +43,28 @@ _str ( wire tag; //must use all wires inside module..... -assign tag = |memory_controller_address & | memory_controller_in; +assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in; reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag; always @(posedge clk) prevTag <= tag; - -always @(*) +always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in) begin - if (~tag) + +case(tag) + + 1'b0: begin - str_address = memory_controller_address[4:0]; + str_address = memory_controller_address[5-1+0:0]; str_write_enable = memory_controller_write_enable; - str_in[7:0] = memory_controller_in[7:0]; + str_in[8-1:0] = memory_controller_in[8-1:0]; end - else - begin - str_address = 5'h0; - str_write_enable = 1'b0; - str_in[7:0] = 8'h0; - end -end +endcase -always @(*) -begin - if (~prevTag) - memory_controller_out = str_out; - else - memory_controller_out = 'h0; +case(prevTag) + + 1'b0: + memory_controller_out = str_out; +endcase end endmodule @@ -280,22 +276,17 @@ case(cur_state) end endcase -always @(*) +always @(cur_state) begin - if (cur_state == 4'b1101) + case(cur_state) + 4'b1101: begin memory_controller_address = s_07; memory_controller_write_enable = 1'b1; memory_controller_in = c; end - else - begin - memory_controller_address = 'h0; - memory_controller_write_enable = 1'b0; - memory_controller_in = 'h0; - end - + endcase end endmodule diff --git a/vtr_flow/benchmarks/verilog/ch_intrinsics_nolatches.v b/vtr_flow/benchmarks/verilog/ch_intrinsics_nolatches.v new file mode 100755 index 00000000000..707eab4a97f --- /dev/null +++ b/vtr_flow/benchmarks/verilog/ch_intrinsics_nolatches.v @@ -0,0 +1,301 @@ + + +`define MEMORY_CONTROLLER_TAGS 1 +`define MEMORY_CONTROLLER_TAG_SIZE 1 +`define TAG__str 1'b0 +`define MEMORY_CONTROLLER_ADDR_SIZE 32 +`define MEMORY_CONTROLLER_DATA_SIZE 32 + + +module memory_controller +( + clk, + memory_controller_address, + memory_controller_write_enable, + memory_controller_in, + memory_controller_out +); +input clk; +input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; +input memory_controller_write_enable; +input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; +reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; + + +reg [4:0] str_address; +reg str_write_enable; +reg [7:0] str_in; +wire [7:0] str_out; + +single_port_ram + # (.ADDR_WIDTH(5), .DATA_WIDTH(8)) +_str ( + .clk( clk ), + .addr( str_address ), + .we( str_write_enable ), + .data( str_in ), + .out( str_out ) +); + + +wire tag; + +//must use all wires inside module..... +assign tag = |memory_controller_address & | memory_controller_in; +reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag; +always @(posedge clk) + prevTag <= tag; + +always @(*) +begin + if (~tag) + begin + str_address = memory_controller_address[4:0]; + str_write_enable = memory_controller_write_enable; + str_in[7:0] = memory_controller_in[7:0]; + end + else + begin + str_address = 5'h0; + str_write_enable = 1'b0; + str_in[7:0] = 8'h0; + end +end + +always @(*) +begin + if (~prevTag) + memory_controller_out = str_out; + else + memory_controller_out = 'h0; +end + +endmodule + + +module memset + ( + clk, + reset, + start, + finish, + return_val, + m, + c, + n, + memory_controller_write_enable, + memory_controller_address, + memory_controller_in, + memory_controller_out + ); + +output[`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val; +input clk; +input reset; +input start; + +output finish; +reg finish; + +input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m; +input [31:0] c; +input [31:0] n; + +output [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; + +output memory_controller_write_enable; +reg memory_controller_write_enable; + +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; +reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; + +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; + +reg [3:0] cur_state; + +/* +parameter Wait = 4'd0; +parameter entry = 4'd1; +parameter entry_1 = 4'd2; +parameter entry_2 = 4'd3; +parameter bb = 4'd4; +parameter bb_1 = 4'd5; +parameter bb1 = 4'd6; +parameter bb1_1 = 4'd7; +parameter bb_nph = 4'd8; +parameter bb2 = 4'd9; +parameter bb2_1 = 4'd10; +parameter bb2_2 = 4'd11; +parameter bb2_3 = 4'd12; +parameter bb2_4 = 4'd13; +parameter bb4 = 4'd14; +*/ + +memory_controller memtroll (clk,memory_controller_address, memory_controller_write_enable, memory_controller_in, memory_controller_out); + + +reg [31:0] indvar; +reg var1; +reg [31:0] tmp; +reg [31:0] tmp8; +reg var2; +reg [31:0] var0; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07; +reg [31:0] indvar_next; +reg exitcond; + +always @(posedge clk) +if (reset) + cur_state <= 4'b0000; +else +case(cur_state) + 4'b0000: + begin + finish <= 1'b0; + if (start == 1'b1) + cur_state <= 4'b0001; + else + cur_state <= 4'b0000; + end + 4'b0001: + begin + + + + var0 <= n & 32'b00000000000000000000000000000011; + + cur_state <= 4'b0010; + end + 4'b0010: + begin + + var1 <= 1'b0; + var0 <= 32'b00000000000000000000000000000000; + + cur_state <= 4'b0011; + end + 4'b0011: + begin + + + if (|var1) begin + cur_state <= 4'b0110; + end + else + begin + + cur_state <= 4'b0100; + end + end + 4'b0100: + begin + + cur_state <= 4'b0101; + end + 4'b0101: + begin + cur_state <= 4'b0110; + end + 4'b0110: + begin + + var2 <= | (n [31:4]); + + cur_state <= 4'b0111; + end + 4'b0111: + begin + + if (|var2) + begin + cur_state <= 4'b1110; + end + else + begin + cur_state <= 4'b1000; + end + end + 4'b1000: + begin + + tmp <= n ; + + indvar <= 32'b00000000000000000000000000000000; + cur_state <= 4'b1001; + end + 4'b1001: + begin + + cur_state <= 4'b1010; + end + 4'b1010: + begin + tmp8 <= indvar; + indvar_next <= indvar; + cur_state <= 4'b1011; + end + 4'b1011: + begin + + scevgep <= (m & tmp8); + + exitcond <= (indvar_next == tmp); + + cur_state <= 4'b1100; + end + 4'b1100: + begin + + s_07 <= scevgep; + + cur_state <= 4'b1101; + end + 4'b1101: + + begin + + + if (exitcond) + begin + cur_state <= 4'b1110; + end + else + begin + indvar <= indvar_next; + cur_state <= 4'b1001; + end + end + + + 4'b1110: + begin + + return_val <= m; + finish <= 1'b1; + cur_state <= 4'b0000; + end +endcase + +always @(*) +begin + + if (cur_state == 4'b1101) + begin + memory_controller_address = s_07; + memory_controller_write_enable = 1'b1; + memory_controller_in = c; + end + else + begin + memory_controller_address = 'h0; + memory_controller_write_enable = 1'b0; + memory_controller_in = 'h0; + end + +end + +endmodule diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index f3cbad59469..256b3aeadc1 100644 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -247,12 +247,12 @@ module delay1x3 (datain, dataout, clk); end end - always @(*) + always @(state or trigger or count) begin case (state) 0 : begin - output_xhdl0 = 1'b0 ; + output_xhdl0 = 1'b0 ; if (trigger == 1'b1) begin next_state = 1 ; @@ -280,7 +280,7 @@ module delay1x3 (datain, dataout, clk); end 2 : begin - output_xhdl0 = 1'b0 ; + output_xhdl0 = 1'b0 ; if (trigger == 1'b0) begin next_state = 0 ; @@ -289,23 +289,8 @@ module delay1x3 (datain, dataout, clk); begin next_state = 2 ; - end - temp_count = count; - end - // Create a default case to avoid inferring latches. - // Preserve original behavior by holding state, even if - // this is suboptimal for real designs - default: begin - //Note that output_xhdl is combinational and drives - //a top level signal called go. To eliminate inferred - //latch for it, default it to zero here to hypothetically - //make sure that go is not asserted when the FSM goes - //awry - output_xhdl0 = 1'b0; - - next_state = state; - temp_count = count; - end + end + end endcase end endmodule @@ -413,6 +398,20 @@ module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, ori reg next_state; wire we; + reg[27:0] temp_origx; + reg[27:0] temp_origy; + reg[27:0] temp_origz; + reg[15:0] temp_m11; + reg[15:0] temp_m12; + reg[15:0] temp_m13; + reg[15:0] temp_m21; + reg[15:0] temp_m22; + reg[15:0] temp_m23; + reg[15:0] temp_m31; + reg[15:0] temp_m32; + reg[15:0] temp_m33; + reg[20:0] temp_bkcolour; + // <> Can't find translated component 'spram'. Module name may not match spram21x4 spraminst(we, texinfo, CfgData[20:0], clk); assign we = ((CfgData_Ready == 1'b1) & (CfgAddr == 4'b1110)) ? 1'b1 : 1'b0 ; @@ -439,26 +438,24 @@ module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, ori end else begin - state <= next_state ; - if (CfgData_Ready) begin - if (CfgAddr == 4'b0001) origx <= CfgData; - if (CfgAddr == 4'b0010) origy <= CfgData; - if (CfgAddr == 4'b0011) origz <= CfgData; - if (CfgAddr == 4'b0100) m11 <= CfgData[15:0]; - if (CfgAddr == 4'b0101) m12 <= CfgData[15:0]; - if (CfgAddr == 4'b0110) m13 <= CfgData[15:0]; - if (CfgAddr == 4'b0111) m21 <= CfgData[15:0]; - if (CfgAddr == 4'b1000) m22 <= CfgData[15:0]; - if (CfgAddr == 4'b1001) m23 <= CfgData[15:0]; - if (CfgAddr == 4'b1010) m31 <= CfgData[15:0]; - if (CfgAddr == 4'b1011) m32 <= CfgData[15:0]; - if (CfgAddr == 4'b1100) m33 <= CfgData[15:0]; - if (CfgAddr == 4'b1101) bkcolour <= CfgData[20:0]; - end + state <= next_state ; + origx <= temp_origx; + origy <= temp_origy; + origz <= temp_origz; + m11 <= temp_m11; + m12 <= temp_m12; + m13 <= temp_m13; + m21 <= temp_m21; + m22 <= temp_m22; + m23 <= temp_m23; + m31 <= temp_m31; + m32 <= temp_m32; + m33 <= temp_m33; + bkcolour <= bkcolour; end end - always @(*) + always @(state or CfgData_Ready) begin case (state) 0 : @@ -473,6 +470,59 @@ module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, ori begin next_state = 0 ; end + + if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0001)) + begin + temp_origx = CfgData ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0010)) + begin + temp_origy = CfgData ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0011)) + begin + temp_origz = CfgData ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0100)) + begin + temp_m11 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0101)) + begin + temp_m12 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0110)) + begin + temp_m13 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0111)) + begin + temp_m21 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1000)) + begin + temp_m22 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1001)) + begin + temp_m23 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1010)) + begin + temp_m31 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1011)) + begin + temp_m32 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1100)) + begin + temp_m33 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1101)) + begin + temp_bkcolour = CfgData[20:0] ; + end end 1 : begin @@ -516,9 +566,9 @@ module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, ori end //changed to odin 2 ram specifications -single_port_ram - # (.ADDR_WIDTH(8), .DATA_WIDTH(21)) -new_ram( +defparam new_ram.ADDR_WIDTH = 8; +defparam new_ram.DATA_WIDTH = 21; +single_port_ram new_ram( .clk (clk), .we(we), .data(datain), @@ -650,452 +700,345 @@ module rgsramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, d fbdata <= tm3_sram_data_in ; fbdatavalid <= fbdatavalidl ; - fbdatavalidl <= temp_fbdatavalidl; - texelready <= temp_texelready; - shadedataready <= temp_shadedataready; - fcount <= temp_fcount; - faddress <= temp_faddress; - waddress <= temp_waddress; +fbdatavalidl <= temp_fbdatavalidl; +texelready <= temp_texelready; +shadedataready <= temp_shadedataready; +fcount <= temp_fcount; +faddress <= temp_faddress; +waddress <= temp_waddress; end end + always @(state or addr_ready or data_ready or waddress or datain or wantDir or + want_read or wantwriteback or writebackdata or writebackaddr or + fcount or fbpage or faddress or fbnextscanline or triID or wantshadedata or + wanttexel or texeladdr) + + begin + case (state) - always @(*) - begin - case (state) 0 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - if (addr_ready == 1'b1) - - begin - temp_waddress = addrin ; - end - else begin - temp_waddress = waddress; - end - temp_faddress = faddress; - temp_fcount = fcount; - - end - 1 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b0 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - - temp_fbdatavalidl = fbdatavalidl; - temp_shadedataready = shadedataready; - temp_texelready = texelready; - temp_waddress = waddress; - temp_faddress = faddress; - temp_fcount = fcount; - - end - 2 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b0 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - if (want_read == 1'b0) - begin - - temp_waddress = waddress + 1 ; - end - else begin - temp_waddress = waddress; - end - temp_faddress = faddress; - temp_fcount = fcount; - end - 3 : - begin - tm3_sram_we = 8'b00000000 ; - tm3_sram_oe = 2'b11 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = datain ; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b0 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - temp_waddress = waddress + 1 ; - temp_faddress = faddress; - temp_fcount = fcount; - - end - 4 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b0 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - - temp_fbdatavalidl = fbdatavalidl; - temp_shadedataready = shadedataready; - temp_texelready = texelready; - temp_waddress = waddress; - temp_faddress = faddress; - temp_fcount = fcount; - end + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else if (want_read == 1'b1) + begin + next_state = 2 ; + end + else if (data_ready == 1'b1) + begin - 5 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b1 ; - writebackack = 1'b0 ; - - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - if (wantDir == 1'b0) - begin - temp_waddress = waddress + 1 ; - end - else begin - temp_waddress = waddress; - end - temp_faddress = faddress; - temp_fcount = fcount; - end - 6 : - begin - tm3_sram_we = 8'b00000000 ; - tm3_sram_oe = 2'b11 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = writebackdata ; - tm3_sram_addr = {1'b0, writebackaddr} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b1 ; - - temp_fbdatavalidl = fbdatavalidl; - temp_shadedataready = shadedataready; - temp_texelready = texelready; - temp_waddress = waddress; - temp_faddress = faddress; - temp_fcount = fcount; - end + next_state = 3 ; + end + else if (wantDir == 1'b1) + begin + next_state = 5 ; + end + else if (wantwriteback == 1'b1) + begin + next_state = 6 ; + end + else if (wantshadedata == 1'b1) + begin - 7 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {3'b011, fbpage, faddress} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - temp_fbdatavalidl = 1'b1 ; - temp_waddress = waddress; - if (fcount != 0) - begin - temp_faddress = faddress + 1 ; - temp_fcount = fcount - 1 ; - end - else begin - temp_faddress = faddress; - temp_fcount = fcount; - end - end - 8 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b0 ; - temp_waddress = waddress; - temp_fcount = 7'b1101011 ; - if (faddress == 25680) - begin - temp_faddress = 0; - end - else begin - temp_faddress = faddress; - end - end - 9 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - tm3_sram_addr = {3'b010, triID} ; - - temp_fbdatavalidl = 1'b0 ; - temp_texelready = 1'b0 ; - temp_shadedataready = 1'b1 ; - temp_waddress = waddress; - temp_faddress = faddress; - temp_fcount = fcount; - end + next_state = 9 ; + end + else if (wanttexel == 1'b1) + begin + next_state = 10 ; + end + else if (fcount != 0) + begin + next_state = 7 ; + end + else if (fbnextscanline == 1'b1) + begin - 10 : - begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - tm3_sram_addr = {1'b0, texeladdr} ; - - temp_fbdatavalidl = 1'b0 ; - temp_shadedataready = 1'b0 ; - temp_texelready = 1'b1 ; - temp_waddress = waddress; - temp_faddress = faddress; - temp_fcount = fcount; - end - // Create a default case to avoid inferring latches. - // for temp_* variables we can hold previous state to - // preserve design intent. For variables that are - // not re-registered, we must make a choice about - // what the default behavior should be that will - // potentially change functionality vs. previous revision - // for previously undefined state decoding. Make a best - // effort based on how the signals appear to idle when - // not being used by the FSM by matching state 0 - default: begin - tm3_sram_we = 8'b11111111 ; - tm3_sram_oe = 2'b01 ; - tm3_sram_adsp = 1'b0 ; - tm3_sram_data_xhdl0 = 0; - tm3_sram_addr = {1'b0, waddress} ; - want_addr = 1'b1 ; - want_data = 1'b1 ; - read_ready = 1'b1 ; - dirReady = 1'b0 ; - writebackack = 1'b0 ; - - temp_fbdatavalidl = fbdatavalidl; - temp_shadedataready = shadedataready; - temp_texelready = texelready; - temp_waddress = waddress; - temp_faddress = faddress; - temp_fcount = fcount; - end - endcase - end + next_state = 8 ; + end + else + begin + next_state = 0 ; + end + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (addr_ready == 1'b1) - always @(*) - begin - case (state) - 0 : - begin - if (addr_ready == 1'b1) - begin - next_state = 1 ; - end - else if (want_read == 1'b1) - begin - next_state = 2 ; - end - else if (data_ready == 1'b1) - begin - - next_state = 3 ; - end - else if (wantDir == 1'b1) - begin - next_state = 5 ; - end - else if (wantwriteback == 1'b1) - begin - next_state = 6 ; - end - else if (wantshadedata == 1'b1) - begin - - next_state = 9 ; - end - else if (wanttexel == 1'b1) - begin - next_state = 10 ; - end - else if (fcount != 0) - begin - next_state = 7 ; - end - else if (fbnextscanline == 1'b1) - begin - - next_state = 8 ; - end - else - begin - next_state = 0 ; - end - end + begin + temp_waddress = addrin ; + end + + end 1 : - begin - if (addr_ready == 1'b0) - begin - next_state = 0 ; - - end - else - begin - next_state = 1 ; - end - end + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + want_addr = 1'b0 ; + if (addr_ready == 1'b0) + begin + next_state = 0 ; + + end + else + begin + next_state = 1 ; + end + end 2 : - begin - if (want_read == 1'b0) - begin - next_state = 0 ; - end - else - begin - next_state = 2 ; - end - end + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + read_ready = 1'b0 ; + if (want_read == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + end + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (want_read == 1'b0) + begin + + temp_waddress = waddress + 1 ; + end + + end 3 : - begin - next_state = 4 ; - end + begin + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_data_xhdl0 = datain ; + tm3_sram_we = 8'b00000000 ; + + + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b0 ; + want_data = 1'b0 ; + next_state = 4 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_waddress = waddress + 1 ; + + end 4 : - begin - if (data_ready == 1'b0) - begin - - next_state = 0 ; - end - else - begin - next_state = 4 ; - end - end + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + if (data_ready == 1'b0) + begin + + next_state = 0 ; + end + else + begin + next_state = 4 ; + end + want_data = 1'b0 ; + end + 5 : - begin - if (wantDir == 1'b0) - begin - next_state = 0 ; - - end - else - begin - next_state = 5 ; - end - end + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + writebackack = 1'b0 ; + + dirReady = 1'b1 ; + if (wantDir == 1'b0) + begin + next_state = 0 ; + + end + else + begin + next_state = 5 ; + end + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (wantDir == 1'b0) + begin + temp_waddress = waddress + 1 ; + end + + end 6 : - begin - next_state = 0 ; - end + begin + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + + tm3_sram_data_xhdl0 = writebackdata ; + tm3_sram_we = 8'b00000000 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_addr = {1'b0, writebackaddr} ; + writebackack = 1'b1 ; + next_state = 0 ; + end 7 : - begin - if ((fcount == 1) | (addr_ready == 1'b1) | (want_read == 1'b1) | (data_ready == 1'b1) | (wantDir == 1'b1) | (wantwriteback == 1'b1)) - begin - next_state = 0 ; - - end - else - begin - next_state = 7 ; - end - end + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {3'b011, fbpage, faddress} ; + if ((fcount == 1) | (addr_ready == 1'b1) | (want_read == 1'b1) | (data_ready == 1'b1) | (wantDir == 1'b1) | (wantwriteback == 1'b1)) + begin + next_state = 0 ; + + end + else + begin + next_state = 7 ; + end + + + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_fbdatavalidl = 1'b1 ; + if (fcount != 0) + begin + temp_faddress = faddress + 1 ; + temp_fcount = fcount - 1 ; + end + + end 8 : - begin - next_state = 7 ; - end + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + next_state = 7 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_fcount = 7'b1101011 ; + if (faddress == 25680) + begin + temp_faddress = 0; + end + end 9 : - begin - next_state = 0 ; - end + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {3'b010, triID} ; + next_state = 0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_texelready = 1'b0 ; + temp_shadedataready = 1'b1 ; + end 10 : - begin - next_state = 0 ; - end - // Add a default to avoid inferring latches. Preserve original functionality - // by holding previous state, even if this is suboptimal for real circuits: - default: begin - next_state = state; - end - endcase - end + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {1'b0, texeladdr} ; + next_state = 0 ; + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b1 ; + end + endcase + end endmodule - module raysend (as, ack, addr, dir, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, clk, statepeek); + + + + + + + + + + + module raysend (as, ack, addr, dir, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, clk, statepeek); input as; output ack; @@ -1155,7 +1098,7 @@ rgAddr <= temp_rgAddr; end end - always @(*) + always @(state or ack or as or rgDone) begin case (state) @@ -1177,24 +1120,11 @@ rgAddr <= temp_rgAddr; temp_rgWE = 3'b001 ; temp_rgAddrValid = 1'b1 ; temp_rgAddr = addr ; - end - //need to hold previous value explicitly to prevent - //latch inference - else begin - temp_rgData = rgData; - temp_rgWE = rgWE; - temp_rgAddrValid = rgAddrValid; - temp_rgAddr = addr ; - end + end if (as == 1'b0 & ack == 1'b1) begin temp_ack = 1'b0 ; - end - //need to hold previous value explicitly to prevent - //latch inference - else begin - temp_ack = ack; - end + end end 1 : @@ -1209,22 +1139,11 @@ rgAddr <= temp_rgAddr; end statepeek = 3'b010 ; - //need to hold previous value explicitly to prevent - //latch inference - temp_rgData = rgData; - temp_rgWE = rgWE; - temp_rgAddr = rgAddr; - if (rgDone == 1'b1) begin temp_rgAddrValid = 1'b0 ; end - //need to hold previous value explicitly to prevent - //latch inference - else begin - temp_rgAddrValid = rgAddrValid; - end - temp_ack = ack; + end 2 : begin @@ -1238,21 +1157,11 @@ rgAddr <= temp_rgAddr; end statepeek = 3'b011 ; - //need to hold previous value explicitly to prevent - //latch inference - temp_rgData = rgData; - temp_rgWE = rgWE; - temp_rgAddr = rgAddr; - if (rgDone == 1'b1) begin temp_rgAddrValid = 1'b0 ; end - else begin - temp_rgAddrValid = rgAddrValid; - end - temp_ack = ack; end 3 : begin @@ -1266,21 +1175,11 @@ rgAddr <= temp_rgAddr; end statepeek = 3'b100 ; - //need to hold previous value explicitly to prevent - //latch inference - temp_rgData = rgData; - temp_rgWE = rgWE; - temp_rgAddr = rgAddr; - if (rgDone == 1'b1) begin temp_rgAddrValid = 1'b0 ; end - else begin - temp_rgAddrValid = rgAddrValid; - end - temp_ack = ack; end 4 : begin @@ -1294,20 +1193,10 @@ rgAddr <= temp_rgAddr; end statepeek = 3'b101 ; - //need to hold previous value explicitly to prevent - //latch inference - temp_rgData = rgData; - temp_rgWE = rgWE; - temp_rgAddr = rgAddr; - if (rgDone == 1'b1) begin temp_rgAddrValid = 1'b0 ; end - else begin - temp_rgAddrValid = rgAddrValid; - end - temp_ack = ack; end 5 : @@ -1322,20 +1211,11 @@ rgAddr <= temp_rgAddr; end statepeek = 3'b110 ; - //need to hold previous value explicitly to prevent - //latch inference - temp_rgData = rgData; - temp_rgWE = rgWE; - temp_rgAddr = rgAddr; - temp_ack = 1'b1 ; if (rgDone == 1'b1) begin temp_rgAddrValid = 1'b0 ; end - else begin - temp_rgAddrValid = rgAddrValid; - end end @@ -1343,11 +1223,6 @@ rgAddr <= temp_rgAddr; begin next_state = 2 ; - //need to hold previous value explicitly to prevent - //latch inference - temp_rgAddr = rgAddr; - temp_ack = ack; - temp_rgData = {4'b0000, origy} ; temp_rgWE = 3'b010 ; temp_rgAddrValid = 1'b1 ; @@ -1357,11 +1232,6 @@ rgAddr <= temp_rgAddr; begin next_state = 3 ; - //need to hold previous value explicitly to prevent - //latch inference - temp_rgAddr = rgAddr; - temp_ack = ack; - temp_rgData = {4'b0000, origz} ; temp_rgWE = 3'b011 ; temp_rgAddrValid = 1'b1 ; @@ -1370,11 +1240,6 @@ rgAddr <= temp_rgAddr; begin next_state = 4 ; - //need to hold previous value explicitly to prevent - //latch inference - temp_rgAddr = rgAddr; - temp_ack = ack; - temp_rgData = {dir[31:16], dir[47:32]} ; temp_rgWE = 3'b100 ; temp_rgAddrValid = 1'b1 ; @@ -1383,32 +1248,19 @@ rgAddr <= temp_rgAddr; begin next_state = 5 ; - //need to hold previous value explicitly to prevent - //latch inference - temp_rgAddr = rgAddr; - temp_ack = ack; - temp_rgData = {16'b0000000000000000, dir[15:0]} ; temp_rgWE = 3'b101 ; temp_rgAddrValid = 1'b1 ; end - // The original FSM did not have a default case. We want to add one - // to prevent modern synthesis tools from inferring latches in this - // logic. To preserve as much of the original behavior as possible, - // hold the previous flop values whereever possible, even though - // this will cause the FSM to lock up if it gets in an illegal state - default: begin - temp_rgData = rgData; - temp_rgWE = rgWE; - temp_rgAddrValid = rgAddrValid; - temp_rgAddr = rgAddr; - temp_ack = ack; - next_state = state; - end endcase end - endmodule - + endmodule + + + + + + module raygencont (go, initcount, busyout, cycles, nextaddr, nas0, nas1, page, dirReady, wantDir, dirIn, addrIn, as, addr, ack, dir, raygroup0, raygroupvalid0, busy0, raygroup1, raygroupvalid1, busy1, globalreset, clk, statepeek); @@ -1507,25 +1359,8 @@ rgAddr <= temp_rgAddr; addr[1:0] <= temp_addr[1:0]; state <= next_state ; - // dir is only loaded if state == 1, make enable logic here rather - // than risk latch inference below - if (state == 1) begin - dir <= dirIn; - end - - // This matches original logic for all explicitly defined - // states; with a simulation testbench, we could show whether - // there are bugs introduced by allowing this to increment - // during states that are not part of the next state logic - if (state == 0) begin - if (go) begin - cycles <= 0; - end - end - else begin - cycles <= cycles + 1; - end - + dir <= temp_dir; + cycles <= temp_cycles; loaded <= temp_loaded; groupID <= temp_groupID; count <= temp_count; @@ -1543,361 +1378,250 @@ rgAddr <= temp_rgAddr; assign nas0 = temp_nas0; assign nas1 = temp_nas1; - always @(*) - begin - case (state) + always @(state or go or ack or busy or dirReady or addr or count or loaded) + begin + case (state) 0 : - begin - temp_addr[1:0] = 2'b00 ; - temp_loaded = 2'b00 ; - temp_groupID = 2'b00 ; - temp_count = initcount ; - temp_active = 1'b0 ; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = raygroupvalid1; - end - 1 : - begin - if (dirReady == 1'b1 & addr[1:0] == 2'b10) - begin - if (active == 1'b0) + begin + as = 1'b0 ; + wantDir = 1'b0 ; + if (go == 1'b1) begin - temp_loaded[0] = 1'b1 ; - temp_loaded[1] = loaded[1]; + next_state = 1 ; end - else + else begin - temp_loaded[1] = 1'b1 ; - temp_loaded[0] = loaded[0]; + next_state = 0 ; end - end - else begin - temp_loaded = loaded; - end - - temp_addr[1:0] = addr; - temp_groupID = groupID; - temp_count = count; - temp_active = active; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = raygroupvalid1; - end - 2 : - begin - if ((ack == 1'b1) & (addr[1:0] != 2'b10)) - begin - temp_active = active; - temp_addr[1:0] = addr[1:0] + 2'b01 ; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = raygroupvalid1; - end - else if ((ack == 1'b1) & addr[1:0] == 2'b10) - begin - if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) - begin - temp_active = active; - temp_addr[1:0] = addr; - temp_raygroupvalid0 = 1'b1 ; - temp_raygroupvalid1 = raygroupvalid1; - end - else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) - begin - temp_active = active; - temp_addr[1:0] = addr; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = 1'b1 ; - end - else if ((loaded[0]) == 1'b0) - begin - temp_active = 1'b0 ; + statepeek = 3'b001 ; + temp_busyout = 1'b0; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + + if (go == 1'b1) + begin + temp_cycles = 0; + end temp_addr[1:0] = 2'b00 ; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = raygroupvalid1; - end - else if ((loaded[1]) == 1'b0) + temp_loaded = 2'b00 ; + temp_groupID = 2'b00 ; + temp_count = initcount ; + temp_active = 1'b0 ; + + end + 1 : + begin + as = dirReady ; + wantDir = 1'b1 ; + if (dirReady == 1'b1) begin - temp_active = 1'b1 ; - temp_addr[1:0] = 2'b00 ; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = raygroupvalid1; + next_state = 2 ; end - else + else begin - temp_addr[1:0] = addr; - temp_active = active; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = raygroupvalid1; - end - end - else begin - temp_addr[1:0] = addr; - temp_active = active; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = raygroupvalid1; - end - temp_loaded = loaded; - temp_groupID = groupID; - temp_count = count; - end - 3 : - begin - if ((busy[0]) == 1'b1) - begin - temp_groupID = {groupID[1], ~groupID[0]} ; - temp_raygroupvalid0 = 1'b0 ; - temp_count = count - 1 ; - if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) - begin - temp_raygroupvalid1 = 1'b1 ; - temp_active = active; - - end - else if ((loaded[1]) == 1'b0) + next_state = 1 ; + end + statepeek = 3'b010 ; + temp_busyout = 1'b1; + if (addr[1:0] == 2'b00 & dirReady == 1'b1 & active == 1'b0) + begin + temp_nas0 = 1'b1; + temp_nas1 = 1'b1; + end + + temp_dir = dirIn ; + if (dirReady == 1'b1 & addr[1:0] == 2'b10) + begin + if (active == 1'b0) + begin + temp_loaded[0] = 1'b1 ; + end + else + begin + temp_loaded[1] = 1'b1 ; + end + end + temp_cycles = cycles + 1 ; + + + end + 2 : + begin + wantDir = 1'b0 ; + as = 1'b1 ; + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) begin - temp_raygroupvalid1 = raygroupvalid1 ; - temp_active = 1'b1 ; + next_state = 1 ; end - else + else if (ack == 1'b1) begin - temp_raygroupvalid1 = raygroupvalid1 ; - temp_active = 1'b0 ; - end - end - else begin - temp_active = active; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = raygroupvalid1; - temp_count = count; - temp_groupID = groupID; - end - temp_loaded = {loaded[1], 1'b0} ; - temp_addr[1:0] = 2'b00 ; - end - 4 : - begin - if ((busy[1]) == 1'b1) - begin - temp_groupID = {~groupID[1], groupID[0]} ; - temp_raygroupvalid1 = 1'b0 ; - temp_count = count - 1 ; - if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) - begin - temp_raygroupvalid0 = 1'b1 ; - temp_active = active; - end + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (loaded != 2'b11) + begin - else if ((loaded[0]) == 1'b0) - begin - temp_raygroupvalid0 = raygroupvalid0 ; - temp_active = 1'b0 ; + next_state = 1 ; + end + else + begin + next_state = 2 ; + end end - else + else begin - temp_raygroupvalid0 = raygroupvalid0; - temp_active = 1'b1 ; + next_state = 2 ; end - end - else begin - temp_active = active; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = raygroupvalid1; - temp_count = count; - temp_groupID = groupID; - end - temp_loaded = {1'b0, loaded[0]} ; - temp_addr[1:0] = 2'b00 ; - end - // add a default to prevent latch inference. preserve original - // design intent and hold previous state - default: begin - temp_addr[1:0] = addr; - temp_loaded = loaded; - temp_groupID = groupID; - temp_count = count; - temp_active = active; - temp_raygroupvalid0 = raygroupvalid0; - temp_raygroupvalid1 = raygroupvalid1; - end - endcase - end - - always @(*) - begin - case (state) - 0 : - begin - as = 1'b0 ; - wantDir = 1'b0 ; - statepeek = 3'b001 ; - temp_busyout = 1'b0; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; - end - 1 : - begin - as = dirReady ; - wantDir = 1'b1 ; - statepeek = 3'b010 ; - temp_busyout = 1'b1; - if (addr[1:0] == 2'b00 & dirReady == 1'b1 & active == 1'b0) - begin - temp_nas0 = 1'b1; - temp_nas1 = 1'b1; - end - else begin - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; - end - end - 2 : - begin - wantDir = 1'b0 ; - as = 1'b1 ; - statepeek = 3'b011 ; - temp_busyout = 1'b1; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; - end - // Create a default to avoid latch inference - // use the pattern from other states to make - // choices about how to calculate each value. - // this preserves design intent for defined states - // while not guaranteeing identical behavior for - // undefined states. - // Note that states 3 and 4 were previously explicitly - // defined for these signals but match the defaults. - default: begin - //***NOTE: The original behavior of "wantDir" and "as" is almost - // certainly buggy, as the values are undefined for - // states 3-7 and so behavior during states 3-4 (which are - // actually used unlike states 5-7) would have - // held as = 1 and wantDir = 0 regardless of whether - // that was the desired effect or not. It seems unlikely - // that latched behavior was envisioned, as the clock - // for these latches is not well defined. We thus have - // to guess as to the desired value for these bits in - // states 3, 4, (and 5-7 for that matter). The next state - // logic bounces around, so there's not much insight - // to be gleaned from it. The safe choice appears to be - // to set them both inactive even though that definitely - // changes the behavior of the circuit by allowing as to - // clear on transitions from states 2-3 or 2-4. - wantDir = 1'b0; - as = 1'b0; - statepeek = state + 1 ; - temp_busyout = 1'b1; - temp_nas0 = 1'b0; - temp_nas1 = 1'b0; - end - endcase - end + statepeek = 3'b011 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; - always @(*) - begin - case (state) - 0 : - begin - if (go == 1'b1) - begin - next_state = 1 ; - end - else - begin - next_state = 0 ; - end - end - 1 : - begin - if (dirReady == 1'b1) - begin - next_state = 2 ; - end - else - begin - next_state = 1 ; - end - end - 2 : - begin - if ((ack == 1'b1) & (addr[1:0] != 2'b10)) - begin - next_state = 1 ; - end - else if (ack == 1'b1) - begin - if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + temp_addr[1:0] = addr[1:0] + 2'b01 ; + end + else if ((ack == 1'b1) & addr[1:0] == 2'b10) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_raygroupvalid0 = 1'b1 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + + temp_raygroupvalid1 = 1'b1 ; + end + else if ((loaded[0]) == 1'b0) + begin + temp_active = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + end + else if ((loaded[1]) == 1'b0) + begin + temp_active = 1'b1 ; + temp_addr[1:0] = 2'b00 ; + end + end + + temp_cycles = cycles + 1 ; + end + 4 : + begin + if ((busy[1]) == 1'b0) begin - next_state = 3 ; + next_state = 4 ; end - else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + else if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) begin - next_state = 4 ; + next_state = 3 ; end - else if (loaded != 2'b11) + else if (count > 0) begin + next_state = 1 ; end - else + else begin - next_state = 2 ; + next_state = 0 ; end - end - else - begin - next_state = 2 ; - end - end + statepeek = 3'b101 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + if ((busy[1]) == 1'b1) + begin + temp_groupID[1] = ~groupID[1] ; + temp_raygroupvalid1 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_raygroupvalid0 = 1'b1 ; + end + + else if ((loaded[0]) == 1'b0) + begin + temp_active = 1'b0 ; + end + else + begin + temp_active = 1'b1 ; + end + end + temp_loaded[1] = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + + temp_cycles = cycles + 1 ; + end 3 : - begin - if ((busy[0]) == 1'b0) - begin - next_state = 3 ; - end - else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) - begin - next_state = 4 ; - end - else if (count > 0) - begin - next_state = 1 ; - end - else - begin - next_state = 0 ; - end - end - 4 : - begin - if ((busy[1]) == 1'b0) - begin - next_state = 4 ; - end - else if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) - begin - next_state = 3 ; - end - else if (count > 0) - begin - - next_state = 1 ; - end - else - begin - next_state = 0 ; - end - end - // add a default to prevent latch inference - // hold previous state to preserve original design - // intent, even if this is not optimal behavior - default: - next_state = state; - endcase - end + begin + if ((busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (count > 0) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + + end + statepeek = 3'b100 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + if ((busy[0]) == 1'b1) + begin + temp_groupID[0] = ~groupID[0] ; + temp_raygroupvalid0 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + temp_raygroupvalid1 = 1'b1 ; + + end + else if ((loaded[1]) == 1'b0) + begin + temp_active = 1'b1 ; + end + else + begin + temp_active = 1'b0 ; + end + end + temp_loaded[0] = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + + + temp_cycles = cycles + 1 ; + end + endcase + end endmodule - module resultrecieve (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); + + + + + + + module resultrecieve (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); output valid01; reg valid01; @@ -1961,6 +1685,34 @@ rgAddr <= temp_rgAddr; input globalreset; input clk; + reg temp_valid01; + reg temp_valid10; + reg[15:0] temp_id01a; + reg[15:0] temp_id01b; + reg[15:0] temp_id01c; + reg[15:0] temp_id10a; + reg[15:0] temp_id10b; + reg[15:0] temp_id10c; + reg temp_hit01a; + reg temp_hit01b; + reg temp_hit01c; + reg temp_hit10a; + reg temp_hit10b; + reg temp_hit10c; + reg[7:0] temp_u01a; + reg[7:0] temp_u01b; + reg[7:0] temp_u01c; + reg[7:0] temp_v01a; + reg[7:0] temp_v01b; + reg[7:0] temp_v01c; + reg[7:0] temp_u10a; + reg[7:0] temp_u10b; + reg[7:0] temp_u10c; + reg[7:0] temp_v10a; + reg[7:0] temp_v10b; + reg[7:0] temp_v10c; + + reg[2:0] state; reg[2:0] next_state; @@ -2002,68 +1754,34 @@ rgAddr <= temp_rgAddr; begin state <= next_state ; - if (state == 0) begin - if (rgResultReady == 1'b1 & rgResultSource == 2'b01) - begin - id01a <= rgResultData[31:16] ; - id01b <= rgResultData[15:0] ; - end - else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) - begin - id10a <= rgResultData[31:16] ; - id10b <= rgResultData[15:0] ; - end - end - if (state == 1) begin - id01c <= rgResultData[15:0]; - hit01a <= rgResultData[18]; - hit01b <= rgResultData[17]; - hit01c <= rgResultData[16]; - end - if (state == 2) begin - u01a <= rgResultData[23:16]; - u01b <= rgResultData[15:8]; - u01c <= rgResultData[7:0]; - end - if (state == 5) begin - u10a <= rgResultData[23:16]; - u10b <= rgResultData[15:8]; - u10c <= rgResultData[7:0]; - end - if (state == 3) begin - v01a <= rgResultData[23:16]; - v01b <= rgResultData[15:8]; - v01c <= rgResultData[7:0]; - end - if (state == 6) begin - v10a <= rgResultData[23:16]; - v10b <= rgResultData[15:8]; - v10c <= rgResultData[7:0]; - end - if (state == 4) begin - id10c <= rgResultData[15:0] ; - hit10a <= rgResultData[18]; - hit10b <= rgResultData[17]; - hit10c <= rgResultData[16]; - end - - if (state == 3) begin - valid01 <= 1'b1; - end - else begin - valid01 <= 1'b0; - end - if (state == 6) begin - valid10 <= 1'b1; - end - else begin - valid10 <= 1'b0; - end +valid01 <= temp_valid01; +valid10 <= temp_valid10; +id01a <= temp_id01a; +id01b <= temp_id01b; +id01c <= temp_id01c; +hit01a <= temp_hit01a; +hit01b <= temp_hit01b; +hit01c <= temp_hit01c; +u01a <= temp_u01a; +u01b <= temp_u01b; +u01c <= temp_u01c; +u10a <= temp_u10a; +u10b <= temp_u10b; +u10c <= temp_u10c; +v01a <= temp_v01a; +v01b <= temp_v01b; +v01c <= temp_v01c; +v10a <= temp_v10a; +v10b <= temp_v10b; +v10c <= temp_v10c; +hit10a <= temp_hit10a; +hit10b <= temp_hit10b; +hit10c <= temp_hit10c; end end - always @(*) + always @(state or rgResultReady or rgResultSource) begin case (state) 0 : @@ -2074,46 +1792,117 @@ rgAddr <= temp_rgAddr; end else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) begin + next_state = 4 ; end else begin next_state = 0 ; end + + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + if (rgResultReady == 1'b1 & rgResultSource == 2'b01) + begin + temp_id01a = rgResultData[31:16] ; + temp_id01b = rgResultData[15:0] ; + end + else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) + begin + temp_id10a = rgResultData[31:16] ; + temp_id10b = rgResultData[15:0] ; + end + end 1 : begin next_state = 2 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_id01c = rgResultData[15:0] ; + temp_hit01a = rgResultData[18] ; + temp_hit01b = rgResultData[17] ; + temp_hit01c = rgResultData[16] ; + end 2 : begin next_state = 3 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_u01a = rgResultData[23:16] ; + temp_u01b = rgResultData[15:8] ; + temp_u01c = rgResultData[7:0] ; + end 3 : begin next_state = 0 ; + + temp_valid10 = 1'b0 ; + temp_v01a = rgResultData[23:16] ; + temp_v01b = rgResultData[15:8] ; + temp_v01c = rgResultData[7:0] ; + temp_valid01 = 1'b1 ; + end 4 : begin next_state = 5 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_id10c = rgResultData[15:0] ; + + temp_hit10a = rgResultData[18] ; + temp_hit10b = rgResultData[17] ; + temp_hit10c = rgResultData[16] ; + end 5 : begin next_state = 6 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_u10a = rgResultData[23:16] ; + temp_u10b = rgResultData[15:8] ; + temp_u10c = rgResultData[7:0] ; + end 6 : begin next_state = 0 ; + + temp_valid01 = 1'b0 ; + temp_v10a = rgResultData[23:16] ; + temp_v10b = rgResultData[15:8] ; + temp_v10c = rgResultData[7:0] ; + temp_valid10 = 1'b1 ; + end - default: begin - next_state = state; - end endcase end - endmodule + endmodule + + + + + + + + + + + + + module resultwriter (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, addr, as01, as10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, dataout, addrout, write, ack, globalreset, clk); @@ -2211,6 +2000,7 @@ rgAddr <= temp_rgAddr; reg temp_pending01; reg temp_pending10; + reg temp_process01; reg temp_texmap; reg[20:0] temp_texinfol; reg[20:0] temp_shadedataa; @@ -2250,592 +2040,601 @@ rgAddr <= temp_rgAddr; begin state <= next_state ; - if (state == 0) begin - process01 <= pending01; - end - - pending01 <= temp_pending01; - pending10 <= temp_pending10; - texmap <= temp_texmap; - texinfol <= temp_texinfol; - shadedataa <= temp_shadedataa; - shadedatab <= temp_shadedatab; - shadedatac <= temp_shadedatac; - - dataout <= {1'b0, shadedataa, shadedatab, shadedatac} ; +process01 <= temp_process01; +pending01 <= temp_pending01; +pending10 <= temp_pending10; +texmap <= temp_texmap; +texinfol <= temp_texinfol; +shadedataa <= temp_shadedataa; +shadedatab <= temp_shadedatab; +shadedatac <= temp_shadedatac; + + dataout <= {1'b0, + shadedataa[20], + shadedataa[19], + shadedataa[18], + shadedataa[17], + shadedataa[16], + shadedataa[15], + shadedataa[14], + shadedataa[13], + shadedataa[12], + shadedataa[11], + shadedataa[10], + shadedataa[9], + shadedataa[8], + shadedataa[7], + shadedataa[6], + shadedataa[5], + shadedataa[4], + shadedataa[3], + shadedataa[2], + shadedataa[1], + shadedataa[0], + shadedatab[20], + shadedatab[19], + shadedatab[18], + shadedatab[17], + shadedatab[16], + shadedatab[15], + shadedatab[14], + shadedatab[13], + shadedatab[12], + shadedatab[11], + shadedatab[10], + shadedatab[9], + shadedatab[8], + shadedatab[7], + shadedatab[6], + shadedatab[5], + shadedatab[4], + shadedatab[3], + shadedatab[2], + shadedatab[1], + shadedatab[0], + shadedatac[20], + shadedatac[19], + shadedatac[18], + shadedatac[17], + shadedatac[16], + shadedatac[15], + shadedatac[14], + shadedatac[13], + shadedatac[12], + shadedatac[11], + shadedatac[10], + shadedatac[9], + shadedatac[8], + shadedatac[7], + shadedatac[6], + shadedatac[5], + shadedatac[4], + shadedatac[3], + shadedatac[2], + shadedatac[1], + shadedatac[0]} ; end // end // PAJ used to be assign, but weird error, so added as register assign dataout = {1'b0, end assign addrout = (process01 == 1'b1) ? addrout01 : addrout10 ; - always @(*) - begin - case (state) + always @(state or process01 or pending10 or ack or shadedataready or id01a or + id01b or id01c or id10a or id10b or id10c or selectuv or hita or + hitb or hitc or shadedata or pending01 or texmap or texelready) + begin + case (state) 0 : - begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - end - 1 : - begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + if (pending01 == 1'b1 | pending10 == 1'b1) + begin + next_state = 2 ; + end + else + + begin + next_state = 0 ; + end + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_process01 = pending01 ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end 2 : - begin - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - wantshadedata = 1'b1 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b00 ; - if (process01 == 1'b1) - begin - triID = id01a ; - - end - else - begin - triID = id10a ; - end - end + begin + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + wantshadedata = 1'b1 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + if (process01 == 1'b1) + begin + triID = id01a ; + + end + else + begin + triID = id10a ; + end + if (shadedataready == 1'b1) + begin + if (hita == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 3 ; + end + else + + begin + next_state = 4 ; + end + end + else + begin + next_state = 2 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + if (hita == 1'b1) + begin + temp_shadedataa = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedataa = bkcolour ; + end + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end 3 : - begin - wantshadedata = 1'b0 ; - triID = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b00 ; - end - 4 : - begin - wantshadedata = 1'b0 ; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b01 ; - if (process01 == 1'b1) - begin - triID = id01b ; - end - else - begin - triID = id10b ; - end - end - 5 : - begin - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - wantshadedata = 1'b1 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b10 ; - if (process01 == 1'b1) - begin - triID = id01c ; - end - else - begin - triID = id10c ; - end - end - 6 : - begin - wantshadedata = 1'b0 ; - triID = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b01 ; - end - 7 : - begin - wantshadedata = 1'b0 ; - triID = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b10 ; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + + selectuv[1:0] = 2'b00 ; + next_state = 8 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_texinfol = texinfo ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + + end 8 : - begin - wantshadedata = 1'b0 ; - triID = 0; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b00 ; - lmenable = 1'b1 ; - end - 9 : - begin - wantshadedata = 1'b0 ; - triID = 0; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b01 ; - lmenable = 1'b1 ; - end - 10 : - begin - wantshadedata = 1'b0 ; - triID = 0; - wanttexel = 1'b0 ; - selectuv[2] = ~process01 ; - selectuv[1:0] = 2'b10 ; - lmenable = 1'b1 ; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + lmenable = 1'b1 ; + if (texmap == 1'b1) + begin + + next_state = 11 ; + end + else + begin + next_state = 4 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_shadedataa[6:0] = blb ; + temp_shadedataa[13:7] = blg ; + temp_shadedataa[20:14] = blr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end 11 : - begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - wanttexel = 1'b1 ; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + + wanttexel = 1'b1 ; + if (texelready == 1'b1) + begin + next_state = 4 ; + end + else + begin + next_state = 11 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + temp_shadedataa[6:0] = texelb ; + temp_shadedataa[13:7] = texelg ; + temp_shadedataa[20:14] = texelr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end 12 : - begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - wanttexel = 1'b1 ; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + + wanttexel = 1'b1 ; + if (texelready == 1'b1) + begin + next_state = 5 ; + end + else + begin + next_state = 12 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_shadedatab[6:0] = texelb ; + temp_shadedatab[13:7] = texelg ; + temp_shadedatab[20:14] = texelr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end 13 : - begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - wanttexel = 1'b1 ; - end - // Default needed to prevent latch inference; set everything to zero - // for undefined state. This represents a change in design intent - // vs. original code, albeit a subtle one - default: begin - wantshadedata = 1'b0 ; - triID = 0; - selectuv = 0; - lmenable = 1'b0 ; - wanttexel = 1'b0 ; - end - endcase - end + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; - always @(*) - begin - case (state) - 1 : - begin - if (ack == 1'b1 & process01 == 1'b1) - begin - temp_pending01 = 1'b0 ; - temp_pending10 = pending10; - end - - else if (ack == 1'b1 & process01 == 1'b0) - begin - temp_pending10 = 1'b0 ; - temp_pending01 = pending01; - end - //add an else to hold the register value to prevent - //latch inference while preserving design intent - else begin - temp_pending01 = pending01; - temp_pending10 = pending10; - end - end - // Create a default to avoid latch inference. This has a couple of side effects: - // 1. the two unused states in the FSM will pick up this logic (subtle change - // in design intent) - // 2. We can collapse the case statement to eliminate redundancy -- most - // states calculate these values as follows: - default : - begin - if (valid01 == 1'b1) - begin - temp_pending01 = 1'b1 ; - end - //add an else to hold the register value to prevent - //latch inference while preserving design intent - else begin - temp_pending01 = pending01; - end - - if (valid10 == 1'b1) - begin - temp_pending10 = 1'b1 ; - end - //add an else to hold the register value to prevent - //latch inference while preserving design intent - else begin - temp_pending10 = pending10; - end - end - endcase - end - - always @(*) - begin - case (state) - 1 : - begin - if (process01 == 1'b1 & ack == 1'b1) - begin - temp_shiften01 = 1'b1; - temp_shiften10 = 1'b1; - end - else begin - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - end - temp_write = 1'b1; - end - // Create a default to avoid latch inference. This has a couple of side effects: - // 1. the two unused states in the FSM will pick up this logic (subtle change - // in design intent) - // 2. We can collapse the case statement to eliminate redundancy -- most - // states calculate these values as follows: - default: begin - temp_shiften01 = 1'b0; - temp_shiften10 = 1'b0; - temp_write = 1'b0; - end - endcase - end - - always @(*) - begin - case (state) - 2 : - begin - if (hita == 1'b1) - begin - temp_shadedataa = shadedata[20:0] ; - temp_texmap = (~shadedata[63]) & shadedata[62] ; - end - else - begin - temp_shadedataa = bkcolour ; - temp_texmap = texmap; - end - - temp_shadedatab = shadedatab; - temp_shadedatac = shadedatac; - temp_texinfol = texinfol; - - end - 3 : - begin - temp_texinfol = texinfo ; - - temp_shadedataa = shadedataa; - temp_shadedatab = shadedatab; - temp_shadedatac = shadedatac; - temp_texmap = texmap; - end - 4 : - begin - if (hitb == 1'b1) - begin - temp_shadedatab = shadedata[20:0] ; - temp_texmap = (~shadedata[63]) & shadedata[62] ; - end - else - begin - temp_shadedatab = bkcolour ; - temp_texmap = texmap; - end - temp_shadedataa = shadedataa; - temp_shadedatac = shadedatac; - temp_texinfol = texinfol; - end - 5 : - begin - if (hitc == 1'b1) - begin - temp_shadedatac = shadedata[20:0] ; - temp_texmap = (~shadedata[63]) & shadedata[62] ; - end - else - begin - temp_shadedatac = bkcolour ; - temp_texmap = texmap; - end - temp_shadedataa = shadedataa; - temp_shadedatab = shadedatab; - temp_texinfol = texinfol; - end + wanttexel = 1'b1 ; + if (texelready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 13 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + temp_shadedatac[6:0] = texelb ; + temp_shadedatac[13:7] = texelg ; + temp_shadedatac[20:14] = texelr ; + + end 6 : - begin - temp_texinfol = texinfo ; - - temp_shadedataa = shadedataa; - temp_shadedatab = shadedatab; - temp_shadedatac = shadedatac; - temp_texmap = texmap; - end - 7 : - begin - temp_texinfol = texinfo ; - - temp_shadedataa = shadedataa; - temp_shadedatab = shadedatab; - temp_shadedatac = shadedatac; - temp_texmap = texmap; - end - 8 : - begin - temp_shadedataa[6:0] = blb ; - temp_shadedataa[13:7] = blg ; - temp_shadedataa[20:14] = blr ; - - temp_shadedatab = shadedatab; - temp_shadedatac = shadedatac; - temp_texinfol = texinfol ; - temp_texmap = texmap; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + next_state = 9 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_texinfol = texinfo ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end 9 : - begin - temp_shadedatab[6:0] = blb ; - temp_shadedatab[13:7] = blg ; - temp_shadedatab[20:14] = blr ; - - temp_shadedataa = shadedataa; - temp_shadedatac = shadedatac; - temp_texinfol = texinfol ; - temp_texmap = texmap; - end + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + lmenable = 1'b1 ; + if (texmap == 1'b1) + begin + next_state = 12 ; + + end + else + begin + next_state = 5 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + temp_shadedatab[6:0] = blb ; + temp_shadedatab[13:7] = blg ; + temp_shadedatab[20:14] = blr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 7 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + next_state = 10 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_texinfol = texinfo ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 10 : - begin - temp_shadedatac[6:0] = blb ; - temp_shadedatac[13:7] = blg ; - temp_shadedatac[20:14] = blr ; - - temp_shadedataa = shadedataa; - temp_shadedatab = shadedatab; - temp_texinfol = texinfol ; - temp_texmap = texmap; - end - 11 : - begin - temp_shadedataa[6:0] = texelb ; - temp_shadedataa[13:7] = texelg ; - temp_shadedataa[20:14] = texelr ; - - temp_shadedatab = shadedatab; - temp_shadedatac = shadedatac; - temp_texinfol = texinfol ; - temp_texmap = texmap; - end - 12 : - begin - temp_shadedatab[6:0] = texelb ; - temp_shadedatab[13:7] = texelg ; - temp_shadedatab[20:14] = texelr ; - - temp_shadedataa = shadedataa; - temp_shadedatac = shadedatac; - temp_texinfol = texinfol ; - temp_texmap = texmap; - end - 13 : - begin - temp_shadedatac[6:0] = texelb ; - temp_shadedatac[13:7] = texelg ; - temp_shadedatac[20:14] = texelr ; - - temp_shadedataa = shadedataa; - temp_shadedatab = shadedatab; - temp_texinfol = texinfol ; - temp_texmap = texmap; - end - //create a default to avoid latch inference; use to hold - //previous state and thus preserve design intent - default: begin - temp_shadedataa = shadedataa; - temp_shadedatab = shadedatab; - temp_shadedatac = shadedatac; - temp_texinfol = texinfol; - temp_texmap = texmap; - end - endcase - end + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + if (texmap == 1'b1) + begin + next_state = 13 ; + end + else + begin + next_state = 1 ; + end - always @(*) - begin - case (state) - 0 : - begin - if (pending01 == 1'b1 | pending10 == 1'b1) - begin - next_state = 2 ; - end - else - begin - next_state = 0 ; - end - end - 1 : - begin - if (ack == 1'b1) - begin - next_state = 0 ; - end - else - begin - next_state = 1 ; - end - end - 2 : - begin - if (shadedataready == 1'b1) - begin - if (hita == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + lmenable = 1'b1 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_shadedatac[6:0] = blb ; + temp_shadedatac[13:7] = blg ; + temp_shadedatac[20:14] = blr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 4 : + begin + wantshadedata = 1'b0 ; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + if (process01 == 1'b1) begin - next_state = 3 ; + triID = id01b ; end - else + else + begin + + triID = id10b ; + end + if (shadedataready == 1'b1) + begin + if (hitb == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 6 ; + end + else + begin + next_state = 5 ; + end + end + else begin next_state = 4 ; end - end - else - begin - next_state = 2 ; - end - end - 3 : - begin - next_state = 8 ; - end - 4 : - begin - if (shadedataready == 1'b1) - begin - if (hitb == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + if (hitb == 1'b1) + begin + temp_shadedatab = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedatab = bkcolour ; + end + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 5 : + begin + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + wantshadedata = 1'b1 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + if (process01 == 1'b1) + begin - next_state = 6 ; + triID = id01c ; end - else + else begin - next_state = 5 ; + triID = id10c ; end + if (shadedataready == 1'b1) + begin + if (hitc == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 7 ; - end - else - begin - next_state = 4 ; - end - end - 5 : - begin - if (shadedataready == 1'b1) - begin - if (hitc == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + end + else + begin + next_state = 1 ; + end + end + else begin - next_state = 7 ; + next_state = 5 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + if (hitc == 1'b1) + begin + temp_shadedatac = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedatac = bkcolour ; + end + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 1 : + + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + if (ack == 1'b1) + begin + next_state = 0 ; end - else + else begin next_state = 1 ; end - end - else - begin - next_state = 5 ; - end - end - 6 : - begin - next_state = 9 ; - end - 7 : - begin - next_state = 10 ; - end - 8 : - begin - if (texmap == 1'b1) - begin - next_state = 11 ; - end - else - begin - next_state = 4 ; - end - end - 9 : - begin - if (texmap == 1'b1) - begin - next_state = 12 ; - - end - else - begin - next_state = 5 ; - end - end - 10 : - begin - if (texmap == 1'b1) - begin - next_state = 13 ; - end - else - begin - next_state = 1 ; - end - end - 11 : - begin - if (texelready == 1'b1) - begin - next_state = 4 ; - end - else - begin - next_state = 11 ; - end - end - 12 : - begin - if (texelready == 1'b1) - begin - next_state = 5 ; - end - else - begin - next_state = 12 ; - end - end - 13 : - begin - if (texelready == 1'b1) - begin - next_state = 1 ; - end - else - begin - next_state = 13 ; - end - end - // create a default to avoid latch inference; preserving intent by holding - // circuit in invalid states - default: begin - next_state = state; - end - endcase - end + + if (ack == 1'b1 & process01 == 1'b1) + begin + temp_pending01 = 1'b0 ; + end + + else if (ack == 1'b1 & process01 == 1'b0) + begin + temp_pending10 = 1'b0 ; + end + + if (process01 == 1'b1 & ack == 1'b1) + begin + temp_shiften01 = 1'b1; + temp_shiften10 = 1'b1; + end + temp_write = 1'b1; + end + endcase + end endmodule ////////////////////////////////////////////////////////////////////////////////////////////// // @@ -2865,7 +2664,7 @@ rgAddr <= temp_rgAddr; reg[15:0] col16; - always @(*) + always @(dataline or texelselect) begin case (texelselect) 2'b00 : @@ -3016,7 +2815,8 @@ rgAddr <= temp_rgAddr; reg[6:0] bvl; reg[6:0] bwl; - always @(*) + always @(selectuv or u01a or u01b or u01c or v01a or v01b or v01c or u10a or + u10b or u10c or v10a or v10b or v10c) begin case (selectuv) 3'b000 : diff --git a/vtr_flow/benchmarks/verilog/raygentop_nolatches.v b/vtr_flow/benchmarks/verilog/raygentop_nolatches.v new file mode 100644 index 00000000000..f3cbad59469 --- /dev/null +++ b/vtr_flow/benchmarks/verilog/raygentop_nolatches.v @@ -0,0 +1,3178 @@ + module paj_raygentop_hierarchy_no_mem (rgwant_addr, rgwant_data, rgread_ready, rgaddr_ready, rgdata_ready, rgwant_read, rgdatain, rgdataout, rgaddrin, rgCont, rgStat, rgCfgData, rgwant_CfgData, rgCfgData_ready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, clk, fbdata, fbdatavalid, fbnextscanline, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, rgData, rgAddr, rgWE, rgAddrValid, rgDone, rgResultData, rgResultReady, rgResultSource); + + output rgwant_addr; + wire rgwant_addr; + output rgwant_data; + wire rgwant_data; + output rgread_ready; + wire rgread_ready; + input rgaddr_ready; + input rgdata_ready; + + input rgwant_read; + input[63:0] rgdatain; + output[63:0] rgdataout; + wire[63:0] rgdataout; + input[17:0] rgaddrin; + input[31:0] rgCont; + output[31:0] rgStat; + wire[31:0] rgStat; + input[31:0] rgCfgData; + output rgwant_CfgData; + wire rgwant_CfgData; + input rgCfgData_ready; + + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_xhdl0; + output[18:0] tm3_sram_addr; + wire[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + wire[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + wire[1:0] tm3_sram_oe; + output tm3_sram_adsp; + wire tm3_sram_adsp; + input clk; + + output[63:0] fbdata; + wire[63:0] fbdata; + output fbdatavalid; + wire fbdatavalid; + input fbnextscanline; + output[1:0] raygroup01; + wire[1:0] raygroup01; + output raygroupvalid01; + wire raygroupvalid01; + input busy01; + output[1:0] raygroup10; + wire[1:0] raygroup10; + + output raygroupvalid10; + wire raygroupvalid10; + input busy10; + input globalreset; + output[31:0] rgData; + wire[31:0] rgData; + output[3:0] rgAddr; + wire[3:0] rgAddr; + output[2:0] rgWE; + wire[2:0] rgWE; + output rgAddrValid; + wire rgAddrValid; + + input rgDone; + input[31:0] rgResultData; + input rgResultReady; + input[1:0] rgResultSource; + + wire[2:0] statepeek2; + wire as01; + wire ack01; + + wire[3:0] addr01; + wire[47:0] dir01; + wire[47:0] dir; + wire[47:0] sramdatal; + wire wantDir; + wire dirReady; + wire dirReadyl; + wire[14:0] address; + wire[30:0] cyclecounter; + + wire nas01; + wire nas10; + wire go; + reg page; + wire[2:0] statepeekct; + // result Signals + wire valid01; + wire valid10; + wire[15:0] id01a; + wire[15:0] id01b; + wire[15:0] id01c; + wire[15:0] id10a; + + wire[15:0] id10b; + wire[15:0] id10c; + wire hit01a; + wire hit01b; + wire hit01c; + wire hit10a; + wire hit10b; + wire hit10c; + wire[7:0] u01a; + wire[7:0] u01b; + wire[7:0] u01c; + wire[7:0] v01a; + + wire[7:0] v01b; + wire[7:0] v01c; + wire[7:0] u10a; + wire[7:0] u10b; + wire[7:0] u10c; + wire[7:0] v10a; + wire[7:0] v10b; + wire[7:0] v10c; + wire wantwriteback; + wire writebackack; + wire[63:0] writebackdata; + wire[17:0] writebackaddr; + + wire[17:0] nextaddr01; + // Shading Signals + wire[63:0] shadedata; + wire[15:0] triID; + wire wantshadedata; + wire shadedataready; + // CfgData Signals + wire[27:0] origx; + wire[27:0] origy; + wire[27:0] origz; + wire[15:0] m11; + wire[15:0] m12; + + wire[15:0] m13; + wire[15:0] m21; + wire[15:0] m22; + wire[15:0] m23; + wire[15:0] m31; + wire[15:0] m32; + wire[15:0] m33; + wire[20:0] bkcolour; + // Texture signals + wire[20:0] texinfo; + wire[3:0] texaddr; + wire[63:0] texel; + + wire[17:0] texeladdr; + wire wanttexel; + wire texelready; + // Frame Buffer Read Signals + wire fbpage; + // debug signals + wire wantcfg; + wire debugglobalreset; + + assign rgwant_CfgData = wantcfg ; + + onlyonecycle onlyeonecycleinst (rgCont[0], go, globalreset, clk); + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + page <= 1'b1 ; // Reset to 1 such that first flip sets to 0 + end + else + + begin + page <= ~page ; + end + end + assign fbpage = ~page ; + + matmult matmultinst(sramdatal[47:32], sramdatal[31:16], sramdatal[15:0], m11, m12, m13, m21, m22, m23, m31, m32, m33, dir[47:32], dir[31:16], dir[15:0], clk); + + delay1x3 dir01delay(dirReady, dirReadyl, clk); + rgconfigmemory ConfigMemoryInst (rgCfgData[31:28], rgCfgData[27:0], rgCfgData_ready, wantcfg, origx, origy, origz, m11, m12, m13, m21, m22, m23, m31, m32, m33, bkcolour, texinfo, globalreset, clk); + + rgsramcontroller sramcont (rgwant_addr, rgaddr_ready, rgaddrin, rgwant_data, rgdata_ready, rgdatain, rgwant_read, rgread_ready, rgdataout, dirReady, wantDir, sramdatal, address, wantwriteback, writebackack, writebackdata, writebackaddr, fbdata, fbnextscanline, fbdatavalid, fbpage, shadedata, triID, wantshadedata, shadedataready, texeladdr, texel, wanttexel, texelready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, clk); + raysend raysendinst (as01, ack01, addr01, dir01, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, clk, statepeek2); + + raygencont raygencontinst(go, rgCont[15:1], rgStat[31], cyclecounter, nextaddr01, nas01, nas10, page, dirReadyl, wantDir, dir, address, as01, addr01, ack01, dir01, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, clk, statepeekct); + resultrecieve resultrecieveinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); + assign debugglobalreset = globalreset | go ; + resultwriter resultwriteinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, nextaddr01, nas01, nas10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, writebackdata, writebackaddr, wantwriteback, writebackack, debugglobalreset, clk); + assign rgStat[30:0] = cyclecounter ; + endmodule + + +module delay1x3 (datain, dataout, clk); + + input datain; + output dataout; + wire dataout; + input clk; + + reg buff0; + reg buff1; + reg buff2; + + assign dataout = buff2 ; + + always @(posedge clk) + begin +/* PAJ expanded for loop to hard definition the size of `depth */ + buff0 <= datain ; + buff1 <= buff0; + buff2 <= buff1; + end + endmodule + + + + + + + // A debugging circuit that allows a single cycle pulse to be + // generated by through the ports package + module onlyonecycle (trigger, output_xhdl0, globalreset, clk); + + input trigger; + output output_xhdl0; + reg output_xhdl0; + input globalreset; + input clk; + + reg[1:0] state; + reg[1:0] next_state; + reg count; + reg temp_count; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + count <= 0 ; + + end + else + begin + state <= next_state ; + count <= temp_count; + end + end + + always @(*) + begin + case (state) + 0 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + temp_count = 1 - 1 ; + end + 1 : + begin + output_xhdl0 = 1'b1 ; + if (count == 0) + begin + next_state = 2 ; + end + else + + begin + + next_state = 1 ; + end + temp_count = count - 1 ; + end + 2 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + + end + temp_count = count; + end + // Create a default case to avoid inferring latches. + // Preserve original behavior by holding state, even if + // this is suboptimal for real designs + default: begin + //Note that output_xhdl is combinational and drives + //a top level signal called go. To eliminate inferred + //latch for it, default it to zero here to hypothetically + //make sure that go is not asserted when the FSM goes + //awry + output_xhdl0 = 1'b0; + + next_state = state; + temp_count = count; + end + endcase + end + endmodule + +module matmult (Ax, Ay, Az, m11, m12, m13, m21, m22, m23, m31, m32, m33, Cx, Cy, Cz, clk); + + input[16 - 1:0] Ax; + input[16 - 1:0] Ay; + input[16 - 1:0] Az; + input[16 - 1:0] m11; + input[16 - 1:0] m12; + + input[16 - 1:0] m13; + input[16 - 1:0] m21; + input[16 - 1:0] m22; + input[16 - 1:0] m23; + input[16 - 1:0] m31; + input[16 - 1:0] m32; + input[16 - 1:0] m33; + output[16 - 1:0] Cx; + reg[16 - 1:0] Cx; + output[16 - 1:0] Cy; + reg[16 - 1:0] Cy; + output[16 - 1:0] Cz; + + reg[16 - 1:0] Cz; + input clk; + + reg[16 + 16 - 1:0] am11; + reg[16 + 16 - 1:0] am12; + reg[16 + 16 - 1:0] am13; + reg[16 + 16 - 1:0] am21; + reg[16 + 16 - 1:0] am22; + reg[16 + 16 - 1:0] am23; + reg[16 + 16 - 1:0] am31; + reg[16 + 16 - 1:0] am32; + reg[16 + 16 - 1:0] am33; + + + always @(posedge clk) + begin + am11 <= Ax * m11 ; + am12 <= Ay * m12 ; + am13 <= Az * m13 ; + am21 <= Ax * m21 ; + am22 <= Ay * m22 ; + am23 <= Az * m23 ; + am31 <= Ax * m31 ; + am32 <= Ay * m32 ; + am33 <= Az * m33 ; + + // Cx <= (am11 + am12 + am13) (`widthA+`widthB-2 downto `widthB-1); + // Cy <= (am21 + am22 + am23) (`widthA+`widthB-2 downto `widthB-1); + // Cz <= (am31 + am32 + am33) (`widthA+`widthB-2 downto `widthB-1); + Cx <= (am11[16+16-2:16-1] + am12[16+16-2:16-1] + am13[16+16-2:16-1]) ; + Cy <= (am21[16+16-2:16-1] + am22[16+16-2:16-1] + am23[16+16-2:16-1]); + Cz <= (am31[16+16-2:16-1] + am32[16+16-2:16-1] + am33[16+16-2:16-1]) ; + end + endmodule + + + + +module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, origy, origz, m11, m12, m13, m21, m22, m23, m31, m32, m33, bkcolour, texinfo, globalreset, clk); + + + input[3:0] CfgAddr; + input[27:0] CfgData; + input CfgData_Ready; + output want_CfgData; + reg want_CfgData; + output[27:0] origx; + reg[27:0] origx; + output[27:0] origy; + reg[27:0] origy; + output[27:0] origz; + reg[27:0] origz; + output[15:0] m11; + reg[15:0] m11; + output[15:0] m12; + reg[15:0] m12; + output[15:0] m13; + reg[15:0] m13; + output[15:0] m21; + reg[15:0] m21; + output[15:0] m22; + reg[15:0] m22; + output[15:0] m23; + reg[15:0] m23; + output[15:0] m31; + reg[15:0] m31; + output[15:0] m32; + reg[15:0] m32; + output[15:0] m33; + reg[15:0] m33; + output[20:0] bkcolour; + reg[20:0] bkcolour; + output[20:0] texinfo; + + wire[20:0] texinfo; + input globalreset; + input clk; + + reg state; + reg next_state; + wire we; + + // <> Can't find translated component 'spram'. Module name may not match + spram21x4 spraminst(we, texinfo, CfgData[20:0], clk); + assign we = ((CfgData_Ready == 1'b1) & (CfgAddr == 4'b1110)) ? 1'b1 : 1'b0 ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + origx <= 0; + origy <= 0; + + origz <= 0; + m11 <= 1; + m12 <= 0; + m13 <= 0; + m21 <= 0; + m22 <= 1; + m23 <= 0; + m31 <= 0; + m32 <= 0; + m33 <= 1; + bkcolour <= 0; + end + else + begin + state <= next_state ; + if (CfgData_Ready) begin + if (CfgAddr == 4'b0001) origx <= CfgData; + if (CfgAddr == 4'b0010) origy <= CfgData; + if (CfgAddr == 4'b0011) origz <= CfgData; + if (CfgAddr == 4'b0100) m11 <= CfgData[15:0]; + if (CfgAddr == 4'b0101) m12 <= CfgData[15:0]; + if (CfgAddr == 4'b0110) m13 <= CfgData[15:0]; + if (CfgAddr == 4'b0111) m21 <= CfgData[15:0]; + if (CfgAddr == 4'b1000) m22 <= CfgData[15:0]; + if (CfgAddr == 4'b1001) m23 <= CfgData[15:0]; + if (CfgAddr == 4'b1010) m31 <= CfgData[15:0]; + if (CfgAddr == 4'b1011) m32 <= CfgData[15:0]; + if (CfgAddr == 4'b1100) m33 <= CfgData[15:0]; + if (CfgAddr == 4'b1101) bkcolour <= CfgData[20:0]; + end + end + end + + always @(*) + begin + case (state) + 0 : + begin + want_CfgData = 1'b1 ; + if (CfgData_Ready == 1'b1) + begin + next_state = 1 ; + end + + else + begin + next_state = 0 ; + end + end + 1 : + begin + want_CfgData = 1'b0 ; + if (CfgData_Ready == 1'b0) + begin + next_state = 0 ; + end + + else + begin + next_state = 1 ; + end + end + endcase + end + endmodule + + + + module spram21x4 (we, dataout, datain, clk); + + input we; + output[21 - 1:0] dataout; + wire[21 - 1:0] dataout; + input[21 - 1:0] datain; + input clk; + + reg [7:0] addr; + + always @ (posedge clk) + begin + addr[0] <= we; + addr [1] <= addr[0]; + addr [2] <= addr[1]; + addr [3] <= addr[2]; + addr [4] <= addr[3]; + addr [5] <= addr[4]; + addr [6] <= addr[5]; + addr [7] <= addr[6]; + end +//changed to odin 2 ram specifications + +single_port_ram + # (.ADDR_WIDTH(8), .DATA_WIDTH(21)) +new_ram( + .clk (clk), + .we(we), + .data(datain), + .out(dataout), + .addr(addr) + ); + + + endmodule + + + + + + + + + + + + +module rgsramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, datain, want_read, read_ready, dataout, dirReady, wantDir, sramdatal, addr, wantwriteback, writebackack, writebackdata, writebackaddr, fbdata, fbnextscanline, fbdatavalid, fbpage, shadedata, triID, wantshadedata, shadedataready, texeladdr, texel, wanttexel, texelready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, clk); + + output want_addr; + reg want_addr; + input addr_ready; + input[17:0] addrin; + output want_data; + reg want_data; + input data_ready; + input[63:0] datain; + input want_read; + output read_ready; + + reg read_ready; + output[63:0] dataout; + wire[63:0] dataout; + output dirReady; + reg dirReady; + input wantDir; + output[47:0] sramdatal; + reg[47:0] sramdatal; + output[14:0] addr; + wire[14:0] addr; + input wantwriteback; + output writebackack; + + reg writebackack; + input[63:0] writebackdata; + input[17:0] writebackaddr; + output[63:0] fbdata; + reg[63:0] fbdata; + input fbnextscanline; + output fbdatavalid; + reg fbdatavalid; + input fbpage; + output[63:0] shadedata; + wire[63:0] shadedata; + input[15:0] triID; + + input wantshadedata; + output shadedataready; + reg shadedataready; + input[17:0] texeladdr; + output[63:0] texel; + wire[63:0] texel; + input wanttexel; + output texelready; + reg texelready; + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + + output[18:0] tm3_sram_addr; + reg[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + reg[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + reg[1:0] tm3_sram_oe; + output tm3_sram_adsp; + reg tm3_sram_adsp; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + reg[17:0] waddress; + reg[14:0] faddress; + reg[6:0] fcount; + reg fbdatavalidl; + + reg[17:0] temp_waddress; + reg[14:0] temp_faddress; + reg[6:0] temp_fcount; + reg temp_fbdatavalidl; + reg temp_texelready; + reg temp_shadedataready; + + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + + assign dataout = tm3_sram_data_in ; + assign addr = tm3_sram_data_in[62:48] ; + assign shadedata = tm3_sram_data_in ; + assign texel = tm3_sram_data_in ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + + state <= 0 ; + waddress <= 0; + faddress <= 0; + fcount <= 7'b1101011 ; + fbdatavalid <= 1'b0 ; + fbdatavalidl <= 1'b0 ; + shadedataready <= 1'b0 ; + texelready <= 1'b0 ; + sramdatal <= 0; + fbdata <= 0; + end + else + + begin + state <= next_state ; + sramdatal <= tm3_sram_data_in[47:0] ; + fbdata <= tm3_sram_data_in ; + fbdatavalid <= fbdatavalidl ; + + fbdatavalidl <= temp_fbdatavalidl; + texelready <= temp_texelready; + shadedataready <= temp_shadedataready; + fcount <= temp_fcount; + faddress <= temp_faddress; + waddress <= temp_waddress; + + end + end + + + always @(*) + begin + case (state) + 0 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (addr_ready == 1'b1) + + begin + temp_waddress = addrin ; + end + else begin + temp_waddress = waddress; + end + temp_faddress = faddress; + temp_fcount = fcount; + + end + 1 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b0 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = fbdatavalidl; + temp_shadedataready = shadedataready; + temp_texelready = texelready; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + + end + 2 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b0 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (want_read == 1'b0) + begin + + temp_waddress = waddress + 1 ; + end + else begin + temp_waddress = waddress; + end + temp_faddress = faddress; + temp_fcount = fcount; + end + 3 : + begin + tm3_sram_we = 8'b00000000 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = datain ; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_waddress = waddress + 1 ; + temp_faddress = faddress; + temp_fcount = fcount; + + end + 4 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = fbdatavalidl; + temp_shadedataready = shadedataready; + temp_texelready = texelready; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + end + + 5 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b1 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (wantDir == 1'b0) + begin + temp_waddress = waddress + 1 ; + end + else begin + temp_waddress = waddress; + end + temp_faddress = faddress; + temp_fcount = fcount; + end + 6 : + begin + tm3_sram_we = 8'b00000000 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = writebackdata ; + tm3_sram_addr = {1'b0, writebackaddr} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b1 ; + + temp_fbdatavalidl = fbdatavalidl; + temp_shadedataready = shadedataready; + temp_texelready = texelready; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + end + + 7 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {3'b011, fbpage, faddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_fbdatavalidl = 1'b1 ; + temp_waddress = waddress; + if (fcount != 0) + begin + temp_faddress = faddress + 1 ; + temp_fcount = fcount - 1 ; + end + else begin + temp_faddress = faddress; + temp_fcount = fcount; + end + end + 8 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_waddress = waddress; + temp_fcount = 7'b1101011 ; + if (faddress == 25680) + begin + temp_faddress = 0; + end + else begin + temp_faddress = faddress; + end + end + 9 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {3'b010, triID} ; + + temp_fbdatavalidl = 1'b0 ; + temp_texelready = 1'b0 ; + temp_shadedataready = 1'b1 ; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + end + + 10 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {1'b0, texeladdr} ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b1 ; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + end + // Create a default case to avoid inferring latches. + // for temp_* variables we can hold previous state to + // preserve design intent. For variables that are + // not re-registered, we must make a choice about + // what the default behavior should be that will + // potentially change functionality vs. previous revision + // for previously undefined state decoding. Make a best + // effort based on how the signals appear to idle when + // not being used by the FSM by matching state 0 + default: begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + temp_fbdatavalidl = fbdatavalidl; + temp_shadedataready = shadedataready; + temp_texelready = texelready; + temp_waddress = waddress; + temp_faddress = faddress; + temp_fcount = fcount; + end + endcase + end + + always @(*) + begin + case (state) + 0 : + begin + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else if (want_read == 1'b1) + begin + next_state = 2 ; + end + else if (data_ready == 1'b1) + begin + + next_state = 3 ; + end + else if (wantDir == 1'b1) + begin + next_state = 5 ; + end + else if (wantwriteback == 1'b1) + begin + next_state = 6 ; + end + else if (wantshadedata == 1'b1) + begin + + next_state = 9 ; + end + else if (wanttexel == 1'b1) + begin + next_state = 10 ; + end + else if (fcount != 0) + begin + next_state = 7 ; + end + else if (fbnextscanline == 1'b1) + begin + + next_state = 8 ; + end + else + begin + next_state = 0 ; + end + end + 1 : + begin + if (addr_ready == 1'b0) + begin + next_state = 0 ; + + end + else + begin + next_state = 1 ; + end + end + 2 : + begin + if (want_read == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + end + end + 3 : + begin + next_state = 4 ; + end + 4 : + begin + if (data_ready == 1'b0) + begin + + next_state = 0 ; + end + else + begin + next_state = 4 ; + end + end + 5 : + begin + if (wantDir == 1'b0) + begin + next_state = 0 ; + + end + else + begin + next_state = 5 ; + end + end + 6 : + begin + next_state = 0 ; + end + + 7 : + begin + if ((fcount == 1) | (addr_ready == 1'b1) | (want_read == 1'b1) | (data_ready == 1'b1) | (wantDir == 1'b1) | (wantwriteback == 1'b1)) + begin + next_state = 0 ; + + end + else + begin + next_state = 7 ; + end + end + 8 : + begin + next_state = 7 ; + end + 9 : + begin + next_state = 0 ; + end + + 10 : + begin + next_state = 0 ; + end + // Add a default to avoid inferring latches. Preserve original functionality + // by holding previous state, even if this is suboptimal for real circuits: + default: begin + next_state = state; + end + endcase + end + + endmodule + + + module raysend (as, ack, addr, dir, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, clk, statepeek); + + input as; + output ack; + reg ack; + input[3:0] addr; + input[47:0] dir; + input[27:0] origx; + input[27:0] origy; + input[27:0] origz; + output[31:0] rgData; + reg[31:0] rgData; + + output[3:0] rgAddr; + reg[3:0] rgAddr; + output[2:0] rgWE; + reg[2:0] rgWE; + output rgAddrValid; + reg rgAddrValid; + input rgDone; + input globalreset; + input clk; + output[2:0] statepeek; + reg[2:0] statepeek; + + reg[3:0] state; + reg[3:0] next_state; + + + + reg[31:0] temp_rgData; + reg[2:0] temp_rgWE; + reg temp_rgAddrValid; + reg temp_ack; + reg[3:0] temp_rgAddr; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + ack <= 1'b0 ; + rgWE <= 3'b000 ; + rgData <= 0; + rgAddrValid <= 1'b0 ; + rgAddr <= 0; + end + else + begin + state <= next_state ; + +rgData <= temp_rgData; +rgWE <= temp_rgWE; +rgAddrValid <= temp_rgAddrValid; +ack <= temp_ack; +rgAddr <= temp_rgAddr; + + end + end + + always @(*) + begin + + case (state) + 0 : + begin + if ((as == 1'b1) & (ack == 1'b0)) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + statepeek = 3'b001 ; + + if ((as == 1'b1) & (ack == 1'b0)) + begin + temp_rgData = {4'b0000, origx} ; + temp_rgWE = 3'b001 ; + temp_rgAddrValid = 1'b1 ; + temp_rgAddr = addr ; + end + //need to hold previous value explicitly to prevent + //latch inference + else begin + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddrValid = rgAddrValid; + temp_rgAddr = addr ; + end + if (as == 1'b0 & ack == 1'b1) + begin + temp_ack = 1'b0 ; + end + //need to hold previous value explicitly to prevent + //latch inference + else begin + temp_ack = ack; + end + + end + 1 : + begin + if (rgDone == 1'b1) + begin + next_state = 6 ; + end + else + begin + next_state = 1 ; + end + statepeek = 3'b010 ; + + //need to hold previous value explicitly to prevent + //latch inference + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddr = rgAddr; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + //need to hold previous value explicitly to prevent + //latch inference + else begin + temp_rgAddrValid = rgAddrValid; + end + temp_ack = ack; + end + 2 : + begin + if (rgDone == 1'b1) + begin + next_state = 7 ; + end + else + begin + next_state = 2 ; + end + statepeek = 3'b011 ; + + //need to hold previous value explicitly to prevent + //latch inference + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddr = rgAddr; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + else begin + temp_rgAddrValid = rgAddrValid; + end + + temp_ack = ack; + end + 3 : + begin + if (rgDone == 1'b1) + begin + next_state = 8 ; + end + else + begin + next_state = 3 ; + end + statepeek = 3'b100 ; + + //need to hold previous value explicitly to prevent + //latch inference + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddr = rgAddr; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + else begin + temp_rgAddrValid = rgAddrValid; + end + + temp_ack = ack; + end + 4 : + begin + if (rgDone == 1'b1) + begin + next_state = 9 ; + end + else + begin + next_state = 4 ; + end + statepeek = 3'b101 ; + + //need to hold previous value explicitly to prevent + //latch inference + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddr = rgAddr; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + else begin + temp_rgAddrValid = rgAddrValid; + end + temp_ack = ack; + end + + 5 : + begin + if (rgDone == 1'b1) + begin + next_state = 0 ; + end + else + begin + next_state = 5 ; + end + statepeek = 3'b110 ; + + //need to hold previous value explicitly to prevent + //latch inference + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddr = rgAddr; + + temp_ack = 1'b1 ; + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + else begin + temp_rgAddrValid = rgAddrValid; + end + + end + + 6 : + begin + next_state = 2 ; + + //need to hold previous value explicitly to prevent + //latch inference + temp_rgAddr = rgAddr; + temp_ack = ack; + + temp_rgData = {4'b0000, origy} ; + temp_rgWE = 3'b010 ; + temp_rgAddrValid = 1'b1 ; + + end + 7 : + begin + next_state = 3 ; + + //need to hold previous value explicitly to prevent + //latch inference + temp_rgAddr = rgAddr; + temp_ack = ack; + + temp_rgData = {4'b0000, origz} ; + temp_rgWE = 3'b011 ; + temp_rgAddrValid = 1'b1 ; + end + 8 : + begin + next_state = 4 ; + + //need to hold previous value explicitly to prevent + //latch inference + temp_rgAddr = rgAddr; + temp_ack = ack; + + temp_rgData = {dir[31:16], dir[47:32]} ; + temp_rgWE = 3'b100 ; + temp_rgAddrValid = 1'b1 ; + end + 9 : + begin + next_state = 5 ; + + //need to hold previous value explicitly to prevent + //latch inference + temp_rgAddr = rgAddr; + temp_ack = ack; + + temp_rgData = {16'b0000000000000000, dir[15:0]} ; + temp_rgWE = 3'b101 ; + temp_rgAddrValid = 1'b1 ; + end + // The original FSM did not have a default case. We want to add one + // to prevent modern synthesis tools from inferring latches in this + // logic. To preserve as much of the original behavior as possible, + // hold the previous flop values whereever possible, even though + // this will cause the FSM to lock up if it gets in an illegal state + default: begin + temp_rgData = rgData; + temp_rgWE = rgWE; + temp_rgAddrValid = rgAddrValid; + temp_rgAddr = rgAddr; + temp_ack = ack; + next_state = state; + end + endcase + end + endmodule + + + module raygencont (go, initcount, busyout, cycles, nextaddr, nas0, nas1, page, dirReady, wantDir, dirIn, addrIn, as, addr, ack, dir, raygroup0, raygroupvalid0, busy0, raygroup1, raygroupvalid1, busy1, globalreset, clk, statepeek); + + input go; + input[14:0] initcount; + output busyout; + wire busyout; + reg temp_busyout; + output[30:0] cycles; + reg[30:0] cycles; + output[17:0] nextaddr; + wire[17:0] nextaddr; + output nas0; + + wire nas0; + reg temp_nas0; + output nas1; + wire nas1; + reg temp_nas1; + input page; + input dirReady; + output wantDir; + reg wantDir; + input[47:0] dirIn; + input[14:0] addrIn; + output as; + reg as; + output[3:0] addr; + + reg[3:0] addr; + input ack; + output[47:0] dir; + reg[47:0] dir; + output[1:0] raygroup0; + wire[1:0] raygroup0; + output raygroupvalid0; + reg raygroupvalid0; + input busy0; + output[1:0] raygroup1; + wire[1:0] raygroup1; + output raygroupvalid1; + + reg raygroupvalid1; + input busy1; + input globalreset; + input clk; + output[2:0] statepeek; + reg[2:0] statepeek; + + + reg[2:0] state; + reg[2:0] next_state; + reg[14:0] count; + reg first; + reg[17:0] destaddr; + wire[1:0] busy; + reg[1:0] loaded; + reg[1:0] groupID; + reg active; + + reg[47:0] temp_dir; + reg[30:0] temp_cycles; + reg[1:0] temp_addr; + reg[1:0] temp_loaded; + reg[1:0] temp_groupID; + reg[14:0] temp_count; + reg temp_active; + reg temp_raygroupvalid1; + reg temp_raygroupvalid0; + + assign busy = {busy1, busy0} ; + + always @(posedge clk) + begin + + if (globalreset == 1'b1) + + begin + state <= 0 ; + cycles <= 0; + dir <= 0; + addr[1:0] <= 2'b00 ; + groupID <= 2'b00 ; + count <= 0; + first <= 1'b0 ; + destaddr <= 0; + raygroupvalid0 <= 1'b0 ; + raygroupvalid1 <= 1'b0 ; + loaded <= 2'b00 ; + + active <= 1'b0 ; + end + else + begin + addr[3:2] <= (active == 1'b0) ? {1'b0, groupID[0]} : {1'b1, groupID[1]} ; + addr[1:0] <= temp_addr[1:0]; + state <= next_state ; + + // dir is only loaded if state == 1, make enable logic here rather + // than risk latch inference below + if (state == 1) begin + dir <= dirIn; + end + + // This matches original logic for all explicitly defined + // states; with a simulation testbench, we could show whether + // there are bugs introduced by allowing this to increment + // during states that are not part of the next state logic + if (state == 0) begin + if (go) begin + cycles <= 0; + end + end + else begin + cycles <= cycles + 1; + end + + loaded <= temp_loaded; + groupID <= temp_groupID; + count <= temp_count; + active <= temp_active; + raygroupvalid0 <= temp_raygroupvalid0; + raygroupvalid1 <= temp_raygroupvalid1; + + end + end + + assign raygroup0 = {1'b0, groupID[0]} ; + assign raygroup1 = {1'b1, groupID[1]} ; + assign nextaddr = {2'b11, page, addrIn} ; + assign busyout = temp_busyout; + assign nas0 = temp_nas0; + assign nas1 = temp_nas1; + + always @(*) + begin + case (state) + 0 : + begin + temp_addr[1:0] = 2'b00 ; + temp_loaded = 2'b00 ; + temp_groupID = 2'b00 ; + temp_count = initcount ; + temp_active = 1'b0 ; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + 1 : + begin + if (dirReady == 1'b1 & addr[1:0] == 2'b10) + begin + if (active == 1'b0) + begin + temp_loaded[0] = 1'b1 ; + temp_loaded[1] = loaded[1]; + end + else + begin + temp_loaded[1] = 1'b1 ; + temp_loaded[0] = loaded[0]; + end + end + else begin + temp_loaded = loaded; + end + + temp_addr[1:0] = addr; + temp_groupID = groupID; + temp_count = count; + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + 2 : + begin + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + temp_active = active; + temp_addr[1:0] = addr[1:0] + 2'b01 ; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + else if ((ack == 1'b1) & addr[1:0] == 2'b10) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_active = active; + temp_addr[1:0] = addr; + temp_raygroupvalid0 = 1'b1 ; + temp_raygroupvalid1 = raygroupvalid1; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + temp_active = active; + temp_addr[1:0] = addr; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = 1'b1 ; + end + else if ((loaded[0]) == 1'b0) + begin + temp_active = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + else if ((loaded[1]) == 1'b0) + begin + temp_active = 1'b1 ; + temp_addr[1:0] = 2'b00 ; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + else + begin + temp_addr[1:0] = addr; + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + end + else begin + temp_addr[1:0] = addr; + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + temp_loaded = loaded; + temp_groupID = groupID; + temp_count = count; + end + 3 : + begin + if ((busy[0]) == 1'b1) + begin + temp_groupID = {groupID[1], ~groupID[0]} ; + temp_raygroupvalid0 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + temp_raygroupvalid1 = 1'b1 ; + temp_active = active; + + end + else if ((loaded[1]) == 1'b0) + begin + temp_raygroupvalid1 = raygroupvalid1 ; + temp_active = 1'b1 ; + end + else + begin + temp_raygroupvalid1 = raygroupvalid1 ; + temp_active = 1'b0 ; + end + end + else begin + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + temp_count = count; + temp_groupID = groupID; + end + temp_loaded = {loaded[1], 1'b0} ; + temp_addr[1:0] = 2'b00 ; + end + 4 : + begin + if ((busy[1]) == 1'b1) + begin + temp_groupID = {~groupID[1], groupID[0]} ; + temp_raygroupvalid1 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_raygroupvalid0 = 1'b1 ; + temp_active = active; + end + + else if ((loaded[0]) == 1'b0) + begin + temp_raygroupvalid0 = raygroupvalid0 ; + temp_active = 1'b0 ; + end + else + begin + temp_raygroupvalid0 = raygroupvalid0; + temp_active = 1'b1 ; + end + end + else begin + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + temp_count = count; + temp_groupID = groupID; + end + temp_loaded = {1'b0, loaded[0]} ; + temp_addr[1:0] = 2'b00 ; + end + // add a default to prevent latch inference. preserve original + // design intent and hold previous state + default: begin + temp_addr[1:0] = addr; + temp_loaded = loaded; + temp_groupID = groupID; + temp_count = count; + temp_active = active; + temp_raygroupvalid0 = raygroupvalid0; + temp_raygroupvalid1 = raygroupvalid1; + end + endcase + end + + always @(*) + begin + case (state) + 0 : + begin + as = 1'b0 ; + wantDir = 1'b0 ; + statepeek = 3'b001 ; + temp_busyout = 1'b0; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + end + 1 : + begin + as = dirReady ; + wantDir = 1'b1 ; + statepeek = 3'b010 ; + temp_busyout = 1'b1; + if (addr[1:0] == 2'b00 & dirReady == 1'b1 & active == 1'b0) + begin + temp_nas0 = 1'b1; + temp_nas1 = 1'b1; + end + else begin + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + end + end + 2 : + begin + wantDir = 1'b0 ; + as = 1'b1 ; + statepeek = 3'b011 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + end + // Create a default to avoid latch inference + // use the pattern from other states to make + // choices about how to calculate each value. + // this preserves design intent for defined states + // while not guaranteeing identical behavior for + // undefined states. + // Note that states 3 and 4 were previously explicitly + // defined for these signals but match the defaults. + default: begin + //***NOTE: The original behavior of "wantDir" and "as" is almost + // certainly buggy, as the values are undefined for + // states 3-7 and so behavior during states 3-4 (which are + // actually used unlike states 5-7) would have + // held as = 1 and wantDir = 0 regardless of whether + // that was the desired effect or not. It seems unlikely + // that latched behavior was envisioned, as the clock + // for these latches is not well defined. We thus have + // to guess as to the desired value for these bits in + // states 3, 4, (and 5-7 for that matter). The next state + // logic bounces around, so there's not much insight + // to be gleaned from it. The safe choice appears to be + // to set them both inactive even though that definitely + // changes the behavior of the circuit by allowing as to + // clear on transitions from states 2-3 or 2-4. + wantDir = 1'b0; + as = 1'b0; + statepeek = state + 1 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + end + endcase + end + + always @(*) + begin + case (state) + 0 : + begin + if (go == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + end + 1 : + begin + if (dirReady == 1'b1) + begin + next_state = 2 ; + end + else + begin + next_state = 1 ; + end + end + 2 : + begin + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + next_state = 1 ; + end + else if (ack == 1'b1) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (loaded != 2'b11) + begin + next_state = 1 ; + end + else + begin + next_state = 2 ; + end + end + else + begin + next_state = 2 ; + end + end + 3 : + begin + if ((busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (count > 0) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + end + 4 : + begin + if ((busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if (count > 0) + begin + + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + end + // add a default to prevent latch inference + // hold previous state to preserve original design + // intent, even if this is not optimal behavior + default: + next_state = state; + endcase + end + + endmodule + + + module resultrecieve (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); + + output valid01; + reg valid01; + output valid10; + reg valid10; + output[15:0] id01a; + reg[15:0] id01a; + output[15:0] id01b; + reg[15:0] id01b; + output[15:0] id01c; + reg[15:0] id01c; + + output[15:0] id10a; + reg[15:0] id10a; + output[15:0] id10b; + reg[15:0] id10b; + output[15:0] id10c; + reg[15:0] id10c; + output hit01a; + reg hit01a; + output hit01b; + reg hit01b; + output hit01c; + reg hit01c; + + output hit10a; + reg hit10a; + output hit10b; + reg hit10b; + output hit10c; + reg hit10c; + output[7:0] u01a; + reg[7:0] u01a; + output[7:0] u01b; + reg[7:0] u01b; + output[7:0] u01c; + reg[7:0] u01c; + + output[7:0] v01a; + reg[7:0] v01a; + output[7:0] v01b; + reg[7:0] v01b; + output[7:0] v01c; + reg[7:0] v01c; + output[7:0] u10a; + reg[7:0] u10a; + output[7:0] u10b; + reg[7:0] u10b; + output[7:0] u10c; + reg[7:0] u10c; + + output[7:0] v10a; + reg[7:0] v10a; + output[7:0] v10b; + reg[7:0] v10b; + output[7:0] v10c; + reg[7:0] v10c; + input[31:0] rgResultData; + input rgResultReady; + input[1:0] rgResultSource; + input globalreset; + input clk; + + reg[2:0] state; + reg[2:0] next_state; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + valid01 <= 1'b0 ; + valid10 <= 1'b0 ; + hit01a <= 1'b0 ; + hit01b <= 1'b0 ; + hit01c <= 1'b0 ; + hit10a <= 1'b0 ; + hit10b <= 1'b0 ; + hit10c <= 1'b0 ; + id01a <= 0; + + id01b <= 0; + id01c <= 0; + id10a <= 0; + id10b <= 0; + id10c <= 0; + u01a <= 0; + u01b <= 0; + u01c <= 0; + v01a <= 0; + v01b <= 0; + v01c <= 0; + u10a <= 0; + + u10b <= 0; + u10c <= 0; + v10a <= 0; + v10b <= 0; + v10c <= 0; + end + else + begin + state <= next_state ; + + if (state == 0) begin + if (rgResultReady == 1'b1 & rgResultSource == 2'b01) + begin + id01a <= rgResultData[31:16] ; + id01b <= rgResultData[15:0] ; + end + else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) + begin + id10a <= rgResultData[31:16] ; + id10b <= rgResultData[15:0] ; + end + end + if (state == 1) begin + id01c <= rgResultData[15:0]; + hit01a <= rgResultData[18]; + hit01b <= rgResultData[17]; + hit01c <= rgResultData[16]; + end + if (state == 2) begin + u01a <= rgResultData[23:16]; + u01b <= rgResultData[15:8]; + u01c <= rgResultData[7:0]; + end + if (state == 5) begin + u10a <= rgResultData[23:16]; + u10b <= rgResultData[15:8]; + u10c <= rgResultData[7:0]; + end + if (state == 3) begin + v01a <= rgResultData[23:16]; + v01b <= rgResultData[15:8]; + v01c <= rgResultData[7:0]; + end + if (state == 6) begin + v10a <= rgResultData[23:16]; + v10b <= rgResultData[15:8]; + v10c <= rgResultData[7:0]; + end + if (state == 4) begin + id10c <= rgResultData[15:0] ; + hit10a <= rgResultData[18]; + hit10b <= rgResultData[17]; + hit10c <= rgResultData[16]; + end + + if (state == 3) begin + valid01 <= 1'b1; + end + else begin + valid01 <= 1'b0; + end + if (state == 6) begin + valid10 <= 1'b1; + end + else begin + valid10 <= 1'b0; + end + end + end + + + always @(*) + begin + case (state) + 0 : + begin + if (rgResultReady == 1'b1 & rgResultSource == 2'b01) + begin + next_state = 1 ; + end + else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) + begin + next_state = 4 ; + end + else + begin + next_state = 0 ; + end + end + + 1 : + begin + next_state = 2 ; + end + 2 : + + begin + next_state = 3 ; + end + 3 : + begin + next_state = 0 ; + end + 4 : + begin + next_state = 5 ; + end + 5 : + + begin + next_state = 6 ; + end + 6 : + begin + next_state = 0 ; + end + default: begin + next_state = state; + end + endcase + end + endmodule + + + module resultwriter (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, addr, as01, as10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, dataout, addrout, write, ack, globalreset, clk); + + input valid01; + input valid10; + input[15:0] id01a; + input[15:0] id01b; + input[15:0] id01c; + input[15:0] id10a; + input[15:0] id10b; + input[15:0] id10c; + + input hit01a; + input hit01b; + input hit01c; + input hit10a; + input hit10b; + input hit10c; + input[7:0] u01a; + input[7:0] u01b; + input[7:0] u01c; + input[7:0] v01a; + input[7:0] v01b; + input[7:0] v01c; + + input[7:0] u10a; + input[7:0] u10b; + input[7:0] u10c; + input[7:0] v10a; + input[7:0] v10b; + input[7:0] v10c; + input[17:0] addr; + input as01; + input as10; + input[20:0] bkcolour; + input[63:0] shadedata; + output[15:0] triID; + + reg[15:0] triID; + output wantshadedata; + reg wantshadedata; + input shadedataready; + input[20:0] texinfo; + output[3:0] texaddr; + wire[3:0] texaddr; + output[17:0] texeladdr; + wire[17:0] texeladdr; + input[63:0] texel; + output wanttexel; + reg wanttexel; + + input texelready; + output[63:0] dataout; + // PAJ see lower note wire[63:0] dataout; + reg[63:0] dataout; + output[17:0] addrout; + wire[17:0] addrout; + output write; + wire write; + reg temp_write; + input ack; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + reg pending01; + reg pending10; + reg process01; + wire[17:0] addrout01; + wire[17:0] addrout10; + wire shiften01; + wire shiften10; + reg temp_shiften01; + reg temp_shiften10; + reg[20:0] shadedataa; + reg[20:0] shadedatab; + reg[20:0] shadedatac; + wire hita; + wire hitb; + wire hitc; + + reg[2:0] selectuv; + wire[6:0] blr; + wire[6:0] blg; + wire[6:0] blb; + reg texmap; + reg lmenable; + wire[1:0] texelselect; + wire[6:0] texelr; + wire[6:0] texelg; + wire[6:0] texelb; + reg[20:0] texinfol; + + reg temp_pending01; + reg temp_pending10; + reg temp_texmap; + reg[20:0] temp_texinfol; + reg[20:0] temp_shadedataa; + reg[20:0] temp_shadedatab; + reg[20:0] temp_shadedatac; + + col16to21 col16to21inst (texel, texelselect, texelr, texelg, texelb); + linearmap linearmapinst (blb, blg, texinfol[17:0], texeladdr, texelselect, texinfol[20:18], lmenable, clk); + bilinearintrp bilinearimp (u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, selectuv, shadedata[41:35], shadedata[62:56], shadedata[20:14], shadedata[34:28], shadedata[55:49], shadedata[13:7], shadedata[27:21], shadedata[48:42], shadedata[6:0], blr, blg, blb, clk); + fifo3 fifo3insta (addr, as01, addrout01, shiften01, globalreset, clk); + fifo3 fifo3instb (addr, as10, addrout10, shiften10, globalreset, clk); + assign hita = (hit01a & process01) | (hit10a & ~process01) ; + assign hitb = (hit01b & process01) | (hit10b & ~process01) ; + assign hitc = (hit01c & process01) | (hit10c & ~process01) ; + assign texaddr = shadedata[59:56] ; + assign shiften01 = temp_shiften01; + assign shiften10 = temp_shiften10; + assign write = temp_write; + + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + pending01 <= 1'b0 ; + pending10 <= 1'b0 ; + shadedataa <= 0; + shadedatab <= 0; + shadedatac <= 0; + process01 <= 1'b0 ; + texmap <= 1'b0 ; + + texinfol <= 0; + end + else + begin + state <= next_state ; + + if (state == 0) begin + process01 <= pending01; + end + + pending01 <= temp_pending01; + pending10 <= temp_pending10; + texmap <= temp_texmap; + texinfol <= temp_texinfol; + shadedataa <= temp_shadedataa; + shadedatab <= temp_shadedatab; + shadedatac <= temp_shadedatac; + + dataout <= {1'b0, shadedataa, shadedatab, shadedatac} ; + end +// end +// PAJ used to be assign, but weird error, so added as register assign dataout = {1'b0, + end + assign addrout = (process01 == 1'b1) ? addrout01 : addrout10 ; + + always @(*) + begin + case (state) + 0 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + end + 1 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + end + 2 : + begin + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + wantshadedata = 1'b1 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + if (process01 == 1'b1) + begin + triID = id01a ; + + end + else + begin + triID = id10a ; + end + end + 3 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + end + 4 : + begin + wantshadedata = 1'b0 ; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + if (process01 == 1'b1) + begin + triID = id01b ; + end + else + begin + triID = id10b ; + end + end + 5 : + begin + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + wantshadedata = 1'b1 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + if (process01 == 1'b1) + begin + triID = id01c ; + end + else + begin + triID = id10c ; + end + end + 6 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + end + 7 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + end + 8 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + lmenable = 1'b1 ; + end + 9 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + lmenable = 1'b1 ; + end + 10 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + lmenable = 1'b1 ; + end + 11 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b1 ; + end + 12 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b1 ; + end + 13 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b1 ; + end + // Default needed to prevent latch inference; set everything to zero + // for undefined state. This represents a change in design intent + // vs. original code, albeit a subtle one + default: begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + end + endcase + end + + always @(*) + begin + case (state) + 1 : + begin + if (ack == 1'b1 & process01 == 1'b1) + begin + temp_pending01 = 1'b0 ; + temp_pending10 = pending10; + end + + else if (ack == 1'b1 & process01 == 1'b0) + begin + temp_pending10 = 1'b0 ; + temp_pending01 = pending01; + end + //add an else to hold the register value to prevent + //latch inference while preserving design intent + else begin + temp_pending01 = pending01; + temp_pending10 = pending10; + end + end + // Create a default to avoid latch inference. This has a couple of side effects: + // 1. the two unused states in the FSM will pick up this logic (subtle change + // in design intent) + // 2. We can collapse the case statement to eliminate redundancy -- most + // states calculate these values as follows: + default : + begin + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + //add an else to hold the register value to prevent + //latch inference while preserving design intent + else begin + temp_pending01 = pending01; + end + + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + //add an else to hold the register value to prevent + //latch inference while preserving design intent + else begin + temp_pending10 = pending10; + end + end + endcase + end + + always @(*) + begin + case (state) + 1 : + begin + if (process01 == 1'b1 & ack == 1'b1) + begin + temp_shiften01 = 1'b1; + temp_shiften10 = 1'b1; + end + else begin + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + end + temp_write = 1'b1; + end + // Create a default to avoid latch inference. This has a couple of side effects: + // 1. the two unused states in the FSM will pick up this logic (subtle change + // in design intent) + // 2. We can collapse the case statement to eliminate redundancy -- most + // states calculate these values as follows: + default: begin + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + endcase + end + + always @(*) + begin + case (state) + 2 : + begin + if (hita == 1'b1) + begin + temp_shadedataa = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedataa = bkcolour ; + temp_texmap = texmap; + end + + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol; + + end + 3 : + begin + temp_texinfol = texinfo ; + + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texmap = texmap; + end + 4 : + begin + if (hitb == 1'b1) + begin + temp_shadedatab = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedatab = bkcolour ; + temp_texmap = texmap; + end + temp_shadedataa = shadedataa; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol; + end + 5 : + begin + if (hitc == 1'b1) + begin + temp_shadedatac = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedatac = bkcolour ; + temp_texmap = texmap; + end + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_texinfol = texinfol; + end + 6 : + begin + temp_texinfol = texinfo ; + + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texmap = texmap; + end + 7 : + begin + temp_texinfol = texinfo ; + + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texmap = texmap; + end + 8 : + begin + temp_shadedataa[6:0] = blb ; + temp_shadedataa[13:7] = blg ; + temp_shadedataa[20:14] = blr ; + + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + 9 : + begin + temp_shadedatab[6:0] = blb ; + temp_shadedatab[13:7] = blg ; + temp_shadedatab[20:14] = blr ; + + temp_shadedataa = shadedataa; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + 10 : + begin + temp_shadedatac[6:0] = blb ; + temp_shadedatac[13:7] = blg ; + temp_shadedatac[20:14] = blr ; + + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + 11 : + begin + temp_shadedataa[6:0] = texelb ; + temp_shadedataa[13:7] = texelg ; + temp_shadedataa[20:14] = texelr ; + + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + 12 : + begin + temp_shadedatab[6:0] = texelb ; + temp_shadedatab[13:7] = texelg ; + temp_shadedatab[20:14] = texelr ; + + temp_shadedataa = shadedataa; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + 13 : + begin + temp_shadedatac[6:0] = texelb ; + temp_shadedatac[13:7] = texelg ; + temp_shadedatac[20:14] = texelr ; + + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_texinfol = texinfol ; + temp_texmap = texmap; + end + //create a default to avoid latch inference; use to hold + //previous state and thus preserve design intent + default: begin + temp_shadedataa = shadedataa; + temp_shadedatab = shadedatab; + temp_shadedatac = shadedatac; + temp_texinfol = texinfol; + temp_texmap = texmap; + end + endcase + end + + always @(*) + begin + case (state) + 0 : + begin + if (pending01 == 1'b1 | pending10 == 1'b1) + begin + next_state = 2 ; + end + else + begin + next_state = 0 ; + end + end + 1 : + begin + if (ack == 1'b1) + begin + next_state = 0 ; + end + else + begin + next_state = 1 ; + end + end + 2 : + begin + if (shadedataready == 1'b1) + begin + if (hita == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 3 ; + end + else + + begin + next_state = 4 ; + end + end + else + begin + next_state = 2 ; + end + end + 3 : + begin + next_state = 8 ; + end + 4 : + begin + if (shadedataready == 1'b1) + begin + if (hitb == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 6 ; + end + else + begin + next_state = 5 ; + end + + end + else + begin + next_state = 4 ; + end + end + 5 : + begin + if (shadedataready == 1'b1) + begin + if (hitc == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 7 ; + + end + else + begin + next_state = 1 ; + end + end + else + begin + next_state = 5 ; + end + end + 6 : + begin + next_state = 9 ; + end + 7 : + begin + next_state = 10 ; + end + 8 : + begin + if (texmap == 1'b1) + begin + next_state = 11 ; + end + else + begin + next_state = 4 ; + end + end + 9 : + begin + if (texmap == 1'b1) + begin + next_state = 12 ; + + end + else + begin + next_state = 5 ; + end + end + 10 : + begin + if (texmap == 1'b1) + begin + next_state = 13 ; + end + else + begin + next_state = 1 ; + end + end + 11 : + begin + if (texelready == 1'b1) + begin + next_state = 4 ; + end + else + begin + next_state = 11 ; + end + end + 12 : + begin + if (texelready == 1'b1) + begin + next_state = 5 ; + end + else + begin + next_state = 12 ; + end + end + 13 : + begin + if (texelready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 13 ; + end + end + // create a default to avoid latch inference; preserving intent by holding + // circuit in invalid states + default: begin + next_state = state; + end + endcase + end + endmodule + ////////////////////////////////////////////////////////////////////////////////////////////// + // + // Verilog file generated by X-HDL - Revision 3.2.38 Jan. 9, 2004 + // Sun Feb 8 14:14:35 2004 + // + // Input file : G:/jamieson/VERILOG_BENCHMARKS/RAYTRACE/col16to21.vhd + // Design name : col16to21 + // Author : + // Company : + // + // Description : + // + // + ////////////////////////////////////////////////////////////////////////////////////////////// + // + module col16to21 (dataline, texelselect, r, g, b); + + input[63:0] dataline; + input[1:0] texelselect; + output[6:0] r; + wire[6:0] r; + output[6:0] g; + wire[6:0] g; + output[6:0] b; + wire[6:0] b; + + reg[15:0] col16; + + always @(*) + begin + case (texelselect) + 2'b00 : + begin + col16 = dataline[15:0] ; + end + 2'b01 : + begin + col16 = dataline[31:16] ; + end + 2'b10 : + begin + col16 = dataline[47:32] ; + end + 2'b11 : + begin + col16 = dataline[63:48] ; + end + endcase + end + assign r = {col16[15:10], 1'b0} ; + assign g = {col16[9:5], 2'b00} ; + assign b = {col16[4:0], 2'b00} ; + endmodule + module linearmap (u, v, start, addr, texelselect, factor, enable, clk); + + input[6:0] u; + input[6:0] v; + input[17:0] start; + output[17:0] addr; + reg[17:0] addr; + output[1:0] texelselect; + wire[1:0] texelselect; + + input[2:0] factor; + input enable; + input clk; + + reg[6:0] ul; + reg[6:0] vl; + + assign texelselect = ul[1:0] ; + + always @(posedge clk) + begin + if (enable == 1'b1) + begin + ul <= u ; + vl <= v ; + end + else + begin + ul <= ul ; + vl <= vl ; + end + case (factor) + 3'b000 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({11'b00000000000, vl}) ; + end + 3'b001 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({10'b0000000000, vl, 1'b0}) ; + + end + 3'b010 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({9'b000000000, vl, 2'b00}) ; + end + 3'b011 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({8'b00000000, vl, 3'b000}) ; + end + 3'b100 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({7'b0000000, vl, 4'b0000}) ; + + end + 3'b101 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({6'b000000, vl, 5'b00000}) ; + end + 3'b110 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({5'b00000, vl, 6'b000000}) ; + end + 3'b111 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({4'b0000, vl, 7'b0000000}) ; + + end + endcase + end + endmodule + module bilinearintrp (u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, selectuv, ru, rv, rw, gu, gv, gw, bu, bv, bw, r, g, b, clk); + + input[7:0] u01a; + input[7:0] u01b; + input[7:0] u01c; + input[7:0] v01a; + input[7:0] v01b; + input[7:0] v01c; + input[7:0] u10a; + input[7:0] u10b; + input[7:0] u10c; + input[7:0] v10a; + input[7:0] v10b; + input[7:0] v10c; + input[2:0] selectuv; + input[6:0] ru; + input[6:0] rv; + input[6:0] rw; + input[6:0] gu; + input[6:0] gv; + input[6:0] gw; + input[6:0] bu; + input[6:0] bv; + input[6:0] bw; + output[6:0] r; + wire[6:0] r; + output[6:0] g; + wire[6:0] g; + output[6:0] b; + wire[6:0] b; + input clk; + + reg[7:0] u; + reg[7:0] v; + reg[7:0] ul; + reg[7:0] vl; + reg[7:0] wl; + reg[14:0] i1b; + reg[14:0] i2b; + reg[14:0] i3b; + reg[14:0] i1g; + reg[14:0] i2g; + reg[14:0] i3g; + reg[14:0] i1r; + reg[14:0] i2r; + reg[14:0] i3r; + reg[6:0] rul; + reg[6:0] rvl; + reg[6:0] rwl; + reg[6:0] gul; + reg[6:0] gvl; + reg[6:0] gwl; + reg[6:0] bul; + reg[6:0] bvl; + reg[6:0] bwl; + + always @(*) + begin + case (selectuv) + 3'b000 : + begin + u = u01a ; + v = v01a ; + end + 3'b001 : + begin + u = u01b ; + v = v01b ; + end + 3'b010 : + begin + u = u01c ; + v = v01c ; + end + 3'b100 : + begin + u = u10a ; + v = v10a ; + end + 3'b101 : + begin + u = u10b ; + v = v10b ; + end + 3'b110 : + begin + u = u10c ; + v = v10c ; + end + default : + begin + u = 0; + v = 0; + end + endcase + end + + always @(posedge clk) + begin + wl <= 8'b11111111 - u - v ; + ul <= u ; + vl <= v ; + rul <= ru ; + rvl <= rv ; + rwl <= rw ; + gul <= gu ; + gvl <= gv ; + gwl <= gw ; + bul <= bu ; + bvl <= bv ; + bwl <= bw ; + i1r <= ul * rul ; + i2r <= vl * rvl ; + i3r <= wl * rwl ; + i1g <= ul * gul ; + i2g <= vl * gvl ; + i3g <= wl * gwl ; + i1b <= ul * bul ; + i2b <= vl * bvl ; + i3b <= wl * bwl ; + end + assign r = (i1r + i2r + i3r) ; + assign g = (i1g + i2g + i3g) ; + assign b = (i1b + i2b + i3b) ; + endmodule + + + +module fifo3 (datain, writeen, dataout, shiften, globalreset, clk); + + input[18 - 1:0] datain; + input writeen; + output[18 - 1:0] dataout; + wire[18 - 1:0] dataout; + input shiften; + input globalreset; + input clk; + + reg[18 - 1:0] data0; + reg[18 - 1:0] data1; + reg[18 - 1:0] data2; + + reg[1:0] pos; + + assign dataout = data0 ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + pos <= 2'b00 ; + data0 <= 0 ; + data1 <= 0 ; + data2 <= 0 ; + end + else + begin + if (writeen == 1'b1 & shiften == 1'b1) + begin + case (pos) + 2'b00 : + begin + data0 <= 0 ; + data1 <= 0 ; + data2 <= 0 ; + end + + 2'b01 : + begin + data0 <= datain ; + data1 <= 0 ; + data2 <= 0 ; + end + 2'b10 : + begin + data0 <= data1 ; + data1 <= datain ; + data2 <= 0 ; + end + + 2'b11 : + begin + data0 <= data1 ; + data1 <= data2 ; + data2 <= datain ; + end + endcase + end + else if (shiften == 1'b1) + begin + data0 <= data1 ; + data1 <= data2 ; + pos <= pos - 1 ; + end + else if (writeen == 1'b1) + begin + case (pos) + 2'b00 : + begin + data0 <= datain ; + end + 2'b01 : + begin + data1 <= datain ; + end + 2'b10 : + begin + data2 <= datain ; + end + endcase + pos <= pos + 1 ; + end + end + end + endmodule + From cc465fbdf3bcc8b4f69fa790eecc8c0454bce275 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Thu, 25 Sep 2025 14:12:05 -0400 Subject: [PATCH 30/31] Add strong test for light slang testing --- .../strong_slang_parser/config/config.txt | 36 +++++++++++++++++++ .../config/golden_results.txt | 22 ++++++++++++ .../vtr_reg_strong/task_list.txt | 3 +- 3 files changed, 60 insertions(+), 1 deletion(-) create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/config.txt new file mode 100755 index 00000000000..90aa067671c --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/config.txt @@ -0,0 +1,36 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +# circuit_list_add=arm_core.v +circuit_list_add=boundtop_nolatches.v +circuit_list_add=ch_intrinsics_nolatches.v +circuit_list_add=diffeq1.v +circuit_list_add=diffeq2.v +# circuit_list_add=or1200.v +circuit_list_add=raygentop_nolatches.v +circuit_list_add=stereovision3.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_fixed_chan_width.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang --route_chan_width 128 + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/golden_results.txt new file mode 100644 index 00000000000..455757793d3 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/golden_results.txt @@ -0,0 +1,22 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 289.44 vpr 284.57 MiB -1 -1 20.67 129476 19 68.25 -1 -1 71904 -1 -1 882 133 25 0 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 291400 133 179 14475 14332 1 7206 1219 37 37 1369 clb auto 141.1 MiB 46.81 273069 122658 574011 185994 385626 2391 202.0 MiB 18.31 0.19 30.6258 21.4363 -205832 -21.4363 21.4363 2.01 0.0432399 0.0382393 4.49664 3.8499 -1 -1 -1 -1 114 179567 25 7.54166e+07 6.12355e+07 9.78865e+06 7150.22 111.44 21.2775 17.9203 204388 2081474 -1 167642 14 30864 119915 9459763 1697181 23.3276 23.3276 -209425 -23.3276 0 0 1.23736e+07 9038.42 0.72 4.75 2.40 -1 -1 0.72 2.30968 2.08056 + k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 519.87 vpr 711.41 MiB -1 -1 37.73 506144 14 98.66 -1 -1 122844 -1 -1 2721 257 0 11 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 728488 257 32 35846 33488 1 19333 3021 63 63 3969 clb auto 331.4 MiB 102.39 1.25468e+06 245660 2120531 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LU32PEEng.v common 3493.71 vpr 2.19 GiB -1 -1 144.79 1216388 97 1049.09 -1 -1 359028 -1 -1 7443 114 168 32 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2295496 114 102 119558 107421 1 56796 7859 102 102 10404 clb auto 994.5 MiB 286.46 5.89587e+06 944511 9536303 3917252 5594679 24372 1886.3 MiB 538.27 3.76 198.697 73.9797 -311968 -73.9797 73.9797 57.91 0.352129 0.312107 48.3166 40.9018 -1 -1 -1 -1 118 1287529 41 6.36957e+08 5.0583e+08 8.09815e+07 7783.69 1230.87 222.885 186.413 1626104 17616147 -1 1201819 23 208227 915566 48731540 8135695 74.7268 74.7268 -458789 -74.7268 0 0 1.02295e+08 9832.24 7.02 35.54 21.68 -1 -1 7.02 21.9604 19.1237 + k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 4832.47 vpr 2.28 GiB -1 -1 199.83 996260 26 3241.75 -1 -1 374916 -1 -1 6659 36 159 27 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2388320 36 356 184039 158693 1 62741 7237 97 97 9409 clb auto 1171.4 MiB 268.90 4.49439e+06 727507 9733206 3729310 5903583 100313 2057.0 MiB 495.51 2.95 141.286 46.7283 -316167 -46.7283 46.7283 48.36 0.287363 0.234663 44.7874 36.7354 -1 -1 -1 -1 128 942659 23 5.71422e+08 4.56673e+08 7.83350e+07 8325.54 418.27 165.672 138.252 1523367 17065601 -1 916087 20 211230 484468 27272992 4848753 47.2286 47.2286 -354961 -47.2286 0 0 9.89488e+07 10516.4 5.50 21.30 18.36 -1 -1 5.50 15.5586 13.8425 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index ba2f042d930..8e39c7b2f8f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -86,6 +86,7 @@ regression_tests/vtr_reg_strong/strong_routing_differing_modes regression_tests/vtr_reg_strong/strong_routing_modes regression_tests/vtr_reg_strong/strong_scale_delay_budgets regression_tests/vtr_reg_strong/strong_sdc +regression_tests/vtr_reg_strong/strong_slang_parser regression_tests/vtr_reg_strong/strong_soft_multipliers regression_tests/vtr_reg_strong/strong_sub_tiles regression_tests/vtr_reg_strong/strong_sub_tiles_directs @@ -120,4 +121,4 @@ regression_tests/vtr_reg_strong/strong_3d/3d_sb regression_tests/vtr_reg_strong/strong_xilinx_simple regression_tests/vtr_reg_strong/strong_xilinx_flagship regression_tests/vtr_reg_strong/strong_scatter_gather -regression_tests/vtr_reg_strong/strong_interposer \ No newline at end of file +regression_tests/vtr_reg_strong/strong_interposer From ab8399388728c224514f6dd7c81f2bd8562bd7c8 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 26 Sep 2025 10:27:56 -0400 Subject: [PATCH 31/31] Fix golden results file --- .../config/golden_results.txt | 29 +++++-------------- 1 file changed, 7 insertions(+), 22 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/golden_results.txt index 455757793d3..6c83c20362f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_slang_parser/config/golden_results.txt @@ -1,22 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 289.44 vpr 284.57 MiB -1 -1 20.67 129476 19 68.25 -1 -1 71904 -1 -1 882 133 25 0 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 291400 133 179 14475 14332 1 7206 1219 37 37 1369 clb auto 141.1 MiB 46.81 273069 122658 574011 185994 385626 2391 202.0 MiB 18.31 0.19 30.6258 21.4363 -205832 -21.4363 21.4363 2.01 0.0432399 0.0382393 4.49664 3.8499 -1 -1 -1 -1 114 179567 25 7.54166e+07 6.12355e+07 9.78865e+06 7150.22 111.44 21.2775 17.9203 204388 2081474 -1 167642 14 30864 119915 9459763 1697181 23.3276 23.3276 -209425 -23.3276 0 0 1.23736e+07 9038.42 0.72 4.75 2.40 -1 -1 0.72 2.30968 2.08056 - k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 519.87 vpr 711.41 MiB -1 -1 37.73 506144 14 98.66 -1 -1 122844 -1 -1 2721 257 0 11 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 728488 257 32 35846 33488 1 19333 3021 63 63 3969 clb auto 331.4 MiB 102.39 1.25468e+06 245660 2120531 748194 1370942 1395 711.4 MiB 99.60 0.82 59.3621 20.6572 -25384.1 -20.6572 20.6572 21.42 0.108435 0.097964 12.2761 10.5918 -1 -1 -1 -1 72 378217 39 2.36641e+08 1.51003e+08 1.98694e+07 5006.15 99.72 37.8934 32.4138 498330 4113940 -1 356248 20 90194 408064 16174907 2536181 21.0308 21.0308 -25825.1 -21.0308 0 0 2.48734e+07 6266.93 1.77 11.76 4.54 -1 -1 1.77 6.65629 5.95111 - k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 85.98 parmys 199.64 MiB -1 -1 10.28 204432 5 6.33 -1 -1 59012 -1 -1 493 36 0 0 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 145220 36 100 10156 7610 1 2714 629 28 28 784 clb auto 98.0 MiB 24.02 92054.9 41683 210761 62037 141517 7207 141.8 MiB 5.34 0.06 22.4681 14.7882 -2451.75 -14.7882 14.7882 1.11 0.0232622 0.0212188 1.97937 1.76596 -1 -1 -1 -1 68 70696 32 4.25198e+07 2.65697e+07 3.51491e+06 4483.30 26.53 8.01247 6.95619 92758 705249 -1 61667 14 13016 68231 2614170 388236 14.7933 14.7933 -2639.52 -14.7933 0 0 4.36276e+06 5564.75 0.25 1.93 0.71 -1 -1 0.25 1.18437 1.07194 - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 18.61 vpr 73.60 MiB -1 -1 12.32 50408 3 0.94 -1 -1 38580 -1 -1 48 196 1 0 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 75368 196 193 1201 1346 1 602 438 15 15 225 io auto 34.9 MiB 0.94 7163.84 3069 105144 27427 75259 2458 73.6 MiB 0.52 0.01 3.40453 2.35326 -1097.9 -2.35326 2.35326 0.28 0.00289602 0.00267647 0.203944 0.187459 -1 -1 -1 -1 38 5549 18 1.03862e+07 3.13491e+06 544116. 2418.30 1.62 0.89213 0.826138 21558 109668 -1 4866 12 1530 2342 124265 36142 2.6589 2.6589 -1196.4 -2.6589 0 0 690508. 3068.92 0.04 0.14 0.11 -1 -1 0.04 0.115725 0.110105 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 3.05 vpr 68.37 MiB -1 -1 0.30 28436 3 0.10 -1 -1 36976 -1 -1 68 99 1 0 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 70012 99 130 344 474 1 227 298 12 12 144 clb auto 29.4 MiB 0.26 1668.56 665 69948 18708 40810 10430 68.4 MiB 0.21 0.00 2.40104 1.86413 -122.75 -1.86413 1.86413 0.16 0.000913552 0.000847746 0.0692845 0.0643818 -1 -1 -1 -1 44 1292 12 5.66058e+06 4.21279e+06 360780. 2505.42 0.99 0.306444 0.280203 13374 71755 -1 1113 9 385 601 24354 7746 1.97022 1.97022 -144.54 -1.97022 0 0 470760. 3269.17 0.02 0.04 0.07 -1 -1 0.02 0.0277573 0.0261925 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 8.93 vpr 72.51 MiB -1 -1 0.34 31584 5 0.17 -1 -1 37692 -1 -1 32 162 0 5 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 74248 162 96 1067 884 1 658 295 16 16 256 mult_36 auto 33.2 MiB 0.44 8719.88 5184 91528 30281 60433 814 72.5 MiB 0.65 0.01 16.9045 15.9899 -1284.08 -15.9899 15.9899 0.32 0.00264371 0.0024706 0.266952 0.24923 -1 -1 -1 -1 52 11213 35 1.21132e+07 3.70461e+06 805949. 3148.24 5.09 1.0747 1.00025 26552 162987 -1 8811 19 3425 5748 914683 271858 17.1638 17.1638 -1366.65 -17.1638 0 0 1.06067e+06 4143.25 0.06 0.34 0.16 -1 -1 0.06 0.130497 0.123293 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 9.10 vpr 70.41 MiB -1 -1 0.25 30196 4 0.14 -1 -1 37488 -1 -1 22 66 0 5 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 72100 66 96 778 595 1 469 189 16 16 256 mult_36 auto 31.3 MiB 0.33 7350.19 3858 48969 14887 33291 791 70.4 MiB 0.43 0.01 13.706 12.0607 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5224 1049656 274967 8.13992 8.13992 -2416.01 -8.13992 0 0 8.69102e+06 3476.41 0.58 0.97 1.49 -1 -1 0.58 0.782267 0.741944 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 15.00 vpr 76.51 MiB -1 -1 1.11 35580 2 0.13 -1 -1 38112 -1 -1 32 311 15 0 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 78344 311 156 1015 1158 1 965 514 28 28 784 memory auto 35.6 MiB 0.88 19533.8 8754 175444 58990 113754 2700 74.9 MiB 0.98 0.02 4.8046 3.95822 -4383.35 -3.95822 3.95822 1.12 0.00462296 0.00408388 0.413249 0.360916 -1 -1 -1 -1 46 13596 14 4.25198e+07 9.94461e+06 2.40571e+06 3068.51 7.18 1.93831 1.74469 81794 492802 -1 13166 14 2545 2895 615847 177173 4.13098 4.13098 -4806.29 -4.13098 -0.000474482 -0.000474482 3.09729e+06 3950.62 0.19 0.33 0.50 -1 -1 0.19 0.195233 0.18134 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 107152 385 362 4430 4319 1 2401 996 26 26 676 io auto 58.8 MiB 8.85 62858.1 30309 562832 209641 346618 6573 98.9 MiB 6.92 0.09 12.2658 9.49103 -9725.66 -9.49103 9.49103 0.98 0.0155589 0.0144795 1.88463 1.72987 -1 -1 -1 -1 84 45426 45 3.69863e+07 1.47499e+07 3.60271e+06 5329.45 20.00 7.63693 7.01685 88364 756610 -1 42009 25 10509 34758 1860085 329697 9.44575 9.44575 -10202.1 -9.44575 0 0 4.58365e+06 6780.54 0.28 1.58 0.82 -1 -1 0.28 0.99516 0.934972 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 20.66 vpr 86.04 MiB -1 -1 3.30 49740 4 0.88 -1 -1 41700 -1 -1 127 236 1 6 success 5160a12-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-17T12:01:36 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 88100 236 305 3177 2989 1 1517 675 19 19 361 io auto 47.1 MiB 3.22 23813.1 12412 207805 61887 142593 3325 86.0 MiB 1.74 0.03 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