diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 6753b6c73c9..05364cb8418 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -311,6 +311,10 @@ jobs: name: 'Strong', suite: 'vtr_reg_strong' }, + { + name: 'SystemVerilog', + suite: 'vtr_reg_system_verilog' + }, { name: 'Valgrind Memory', suite: 'vtr_reg_valgrind_small' diff --git a/.gitmodules b/.gitmodules index 48709ae2f42..b2b3b51feef 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,3 +13,6 @@ [submodule "libs/EXTERNAL/yosys"] path = libs/EXTERNAL/yosys url = https://github.com/YosysHQ/yosys.git +[submodule "libs/EXTERNAL/yosys-slang"] + path = libs/EXTERNAL/yosys-slang + url = https://github.com/povik/yosys-slang.git diff --git a/CMakeLists.txt b/CMakeLists.txt index 4fb30b2f9e1..47cdef240b4 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -56,7 +56,7 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF) # Allow the user to enable building Yosys option(WITH_PARMYS "Enable Yosys as elaborator and parmys-plugin as partial mapper" ON) -option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF) +option(SLANG_SYSTEMVERILOG "Enable building and installing Yosys-Slang plugin for parsing SystemVerilog" ON) set(VTR_VERSION_MAJOR 9) set(VTR_VERSION_MINOR 0) @@ -437,11 +437,12 @@ if(${WITH_ODIN}) endif() endif() -# handle cmake params to compile Yosys SystemVerilog/UHDM plugins -if(${SYNLIG_SYSTEMVERILOG}) - # avoid compiling plugins in case the Parmys frontend is not active +# handle cmake params to compile yosys-slang plugin for Yosys +if(${SLANG_SYSTEMVERILOG}) + # avoid compiling yosys-slang plugin in case the Parmys frontend is not active if(NOT ${WITH_PARMYS}) - message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Parmys frontend. Please set WITH_PARMYS.") + message(WARNING "Parmys is not enabled, disabling Yosys-Slang as well.") + set(SLANG_SYSTEMVERILOG OFF) endif() endif() diff --git a/dev/vtr_test_suite_verifier/test_suites_info.json b/dev/vtr_test_suite_verifier/test_suites_info.json index d5b712750f4..7f0c477cb95 100644 --- a/dev/vtr_test_suite_verifier/test_suites_info.json +++ b/dev/vtr_test_suite_verifier/test_suites_info.json @@ -11,6 +11,10 @@ "name": "parmys_reg_basic", "ignored_tasks": [] }, + { + "name": "vtr_reg_system_verilog", + "ignored_tasks": [] + }, { "name": "vtr_reg_valgrind_small", "ignored_tasks": [] diff --git a/doc/src/vtr/run_vtr_flow.rst b/doc/src/vtr/run_vtr_flow.rst index 98026e68965..7534be08a16 100644 --- a/doc/src/vtr/run_vtr_flow.rst +++ b/doc/src/vtr/run_vtr_flow.rst @@ -73,15 +73,12 @@ The parser for these runs is considered the Yosys conventional Verilog/SystemVer .. code-block:: bash - # Using the Synlig System_Verilog tool if installed, otherwise the Yosys conventional Verilog parser - ./run_vtr_flow -parser system-verilog - - # Using the Surelog plugin if installed, otherwise failure on the unsupported file type - ./run_vtr_flow -parser surelog + # Using the Yosys-Slang plugin for Yosys, otherwise the Yosys conventional Verilog parser + ./run_vtr_flow -parser slang -Running the default VTR flow using the Parmys standalone front-end. -The Synlig HDL parser supports the (i.e., ``read_systemverilog``) and (i.e., ``read_uhdm``) commands. It utilizes Surelog for SystemVerilog 2017 processing and Yosys for synthesis. -Enable Synlig tool with the ``-DSYNLIG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end. +Will run the VTR flow (default configuration) with Yosys-Slang plugin for Yosys frontend using Parmys plugin as partial mapper. +The Yosys-Slang SystemVerilog parser supports the (i.e., ``read_slang``) command. Yosys-Slang builds on top of the slang library to provide comprehensive SystemVerilog support. +Enable the Yosys-Slang plugin with the ``-DSLANG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end. .. code-block:: bash @@ -260,19 +257,24 @@ Detailed Command-line Options .. option:: -parser - Specify a parser for the Yosys synthesizer [default (Verilog-2005), surelog (UHDM), system-verilog]. + Specify a parser for the Yosys synthesizer [default (Verilog-2005), slang (SystemVerilog)]. The script uses the default conventional Verilog parser if this argument is not used. **Default:** default .. note:: - Universal Hardware Data Model (UHDM) is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. - UHDM is used as a compiled interchange format in between SystemVerilog tools. Typical inputs to the UHDM flow are files with ``.v`` or ``.sv`` extensions. - The ``system-verilog`` parser, which represents the ``read_systemverilog`` command, reads SystemVerilog files directly in Yosys. - It executes Surelog with provided filenames and converts them (in memory) into UHDM file. Then, this UHDM file is converted into Yosys AST. `[Yosys-SystemVerilog] `_ - On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys `_, `Surelog] `_ + Yosys-Slang is a Yosys plugin that is built on top of the slang library to provide comprehensive SystemVerilog support. + It supports the ``read_slang`` command, used with the ``-C`` command-line option to read include-files from a text file containing include-file names. + It is used to read SystemVerilog files directly in Yosys. + For more information on Yosys-Slang, see `[Yosys-Slang] `_ .. note:: Parmys is a Yosys plugin which provides intelligent partial mapping features (inference, binding, and hard/soft logic trade-offs) from Odin-II for Yosys. For more information on available paramters see the `Parmys `_ plugin page. + +.. Universal Hardware Data Model (UHDM) is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. +.. UHDM is used as a compiled interchange format in between SystemVerilog tools. Typical inputs to the UHDM flow are files with ``.v`` or ``.sv`` extensions. +.. The ``system-verilog`` parser, which represents the ``read_systemverilog`` command, reads SystemVerilog files directly in Yosys. +.. It executes Surelog with provided filenames and converts them (in memory) into UHDM file. Then, this UHDM file is converted into Yosys AST. `[Yosys-SystemVerilog] `_ +.. On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys `_, `Surelog] `_ diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index ff2256bc77c..4704e011d77 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -1,6 +1,8 @@ include(ExternalProject) include(ProcessorCount) +find_package(Git REQUIRED) + #Manually synchronized external libraries add_subdirectory(libpugixml) @@ -10,7 +12,6 @@ add_subdirectory(libsdcparse) add_subdirectory(libblifparse) add_subdirectory(libtatum) add_subdirectory(libcatch2) -#add_subdirectory(synlig) #add_subdirectory(parmys) #Proc numbers @@ -60,11 +61,11 @@ if (${WITH_PARMYS}) #Initialize yosys submodules execute_process( - COMMAND git submodule update --init + COMMAND ${GIT_EXECUTABLE} submodule update --init WORKING_DIRECTORY ${YOSYS_SRC_DIR} ) execute_process( - COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive git\ submodule\ update\ --init + COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive ${GIT_EXECUTABLE}\ submodule\ update\ --init WORKING_DIRECTORY ${YOSYS_SRC_DIR} ) @@ -73,104 +74,61 @@ if (${WITH_PARMYS}) COMMAND ${MAKE_PROGRAM} -C ${YOSYS_SRC_DIR} ENABLE_ABC=0 PREFIX=${CMAKE_BINARY_DIR} - + > /dev/null 2>&1 COMMAND ${MAKE_PROGRAM} -C ${YOSYS_SRC_DIR} install ENABLE_ABC=0 PREFIX=${CMAKE_BINARY_DIR} - + > /dev/null 2>&1 WORKING_DIRECTORY ${YOSYS_SRC_DIR}) add_custom_target(yosys ALL DEPENDS ${YOSYS_BUILD_DIR}) - if (${SYNLIG_SYSTEMVERILOG}) - - set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog) - set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build) - set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins) - - ExternalProject_Add(surelog - # root directory for Surelog project - PREFIX "surelog" - - GIT_REPOSITORY https://github.com/chipsalliance/Surelog.git - GIT_TAG v1.71 - GIT_PROGRESS TRUE - GIT_SHALLOW TRUE - - # setting source, build and install directories - SOURCE_DIR "${SURELOG_SOURCE_DIR}" - BUILD_IN_SOURCE FALSE - INSTALL_DIR "${SURELOG_BINARY_DIR}" - - # define Surelog cache values - CMAKE_CACHE_ARGS - "-DCMAKE_BUILD_TYPE:STRING=Release" - "-DCMAKE_INSTALL_PREFIX:PATH=${CMAKE_BINARY_DIR}" - "-DCMAKE_POSITION_INDEPENDENT_CODE:BOOL=ON" - "-DCMAKE_WARN_DEPRECATED:BOOL=OFF" - - # redirect logs to a logfile - LOG_BUILD ON - LOG_UPDATE ON - LOG_INSTALL ON - LOG_CONFIGURE OFF - LOG_OUTPUT_ON_FAILURE ON - - # dependency - DEPENDS yosys - ) - - # Synlig integration (manages Surelog and UHDM internally) - - # Synlig integration (manages Surelog and UHDM internally) - set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig) + if (${SLANG_SYSTEMVERILOG}) + set(SLANG_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-slang) + set(SLANG_BUILD_DIR ${CMAKE_BINARY_DIR}/yosys-slang) + #Initialize yosys-slang submodules + execute_process( + COMMAND ${GIT_EXECUTABLE} submodule update --init + WORKING_DIRECTORY ${SLANG_SRC_DIR} + ) + execute_process( + COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive ${GIT_EXECUTABLE}\ submodule\ update\ --init + WORKING_DIRECTORY ${SLANG_SRC_DIR} + ) + set(SLANG_FE "${SLANG_SRC_DIR}/src/slang_frontend.cc") + ExternalProject_Add( + yosys-slang + SOURCE_DIR ${SLANG_SRC_DIR} + BINARY_DIR ${SLANG_BUILD_DIR} + + #Disabling UndrivenPass in slang_frontend.cc + PATCH_COMMAND + ${CMAKE_COMMAND} -E echo "Patching slang_frontend.cc to disable UndrivenPass" && + ${CMAKE_COMMAND} -DIN=${SLANG_FE} -P ${CMAKE_CURRENT_SOURCE_DIR}/patch_slang.cmake + + CONFIGURE_COMMAND "" + + # Sets location of yosys-config required by slang and suppresses warnings + BUILD_COMMAND + ${CMAKE_COMMAND} -E env + YOSYS_PREFIX=${CMAKE_BINARY_DIR}/bin/ + ${MAKE_PROGRAM} -C ${SLANG_SRC_DIR} + CMAKE_FLAGS="-DCMAKE_BUILD_TYPE=Release -DCMAKE_CXX_FLAGS=-w" + install - # Clone Synlig repository and ensure submodules are synced before building - ExternalProject_Add(synlig - PREFIX "synlig" + INSTALL_COMMAND "" - # Clone the Synlig repository - GIT_REPOSITORY https://github.com/chipsalliance/synlig.git - GIT_TAG main - GIT_PROGRESS TRUE - GIT_SHALLOW TRUE + DEPENDS yosys - # Set source and build directories - SOURCE_DIR "${SYNLIG_SOURCE_DIR}" - BUILD_IN_SOURCE FALSE - INSTALL_DIR " " - - # Sync submodules after cloning - - - UPDATE_COMMAND git submodule update --init --recursive third_party/surelog - WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR} - - BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT} - INSTALL_COMMAND "" - CONFIGURE_COMMAND "" - - # Pass necessary paths and set environment variables - CMAKE_CACHE_ARGS - "-DCMAKE_BUILD_TYPE:STRING=Release" - "-DSURELOG_PATH=${CMAKE_BINARY_DIR}/surelog" - "-DYOSYS_PATH=${CMAKE_BINARY_DIR}/yosys" - "-DUHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}" - "-DBUILD_DIR=${CMAKE_BINARY_DIR}/synlig-build" - "-DEXPORT_PATH=${CMAKE_BINARY_DIR}/synlig_install/usr/local/bin:$ENV{PATH}" - - LOG_BUILD ON + LOG_BUILD OFF LOG_UPDATE ON LOG_INSTALL ON LOG_CONFIGURE OFF LOG_OUTPUT_ON_FAILURE ON - - # Ensure dependencies like Yosys are built first - DEPENDS yosys # Ensure submodule sync runs before synlig build + ) - endif () endif () diff --git a/libs/EXTERNAL/patch_slang.cmake b/libs/EXTERNAL/patch_slang.cmake new file mode 100644 index 00000000000..d3520b95411 --- /dev/null +++ b/libs/EXTERNAL/patch_slang.cmake @@ -0,0 +1,18 @@ +# Patch step for yosys-slang +# +# The variable 'IN' points to vtr_root/libs/EXTERNAL/yosys-slang/src/slang_frontend.cc +# This file contains the UndrivenPass that we want to disable +# +# This patch step finds the line where the UndrivenPass is called and comments out that line +# +# The UndrivenPass needs to be disabled due to unsupported synchronous rules in vtr_primitives.v + +if(NOT DEFINED IN) + message(FATAL_ERROR "patch_slang.cmake: IN (SLANG_FE) variable not set.") +endif() +file(READ "${IN}" SLANG_FRONTEND_CONTENTS) +string(REPLACE "call(design, \"undriven\");" "// call(design, \"undriven\");" SLANG_PATCHED "${SLANG_FRONTEND_CONTENTS}") + if(NOT SLANG_FRONTEND_CONTENTS STREQUAL SLANG_PATCHED) + message(STATUS "Patching slang_frontend.cc to disable UndrivenPass") + file(WRITE "${IN}" "${SLANG_PATCHED}") + endif() diff --git a/libs/EXTERNAL/yosys-slang b/libs/EXTERNAL/yosys-slang new file mode 160000 index 00000000000..76b83eb5b73 --- /dev/null +++ b/libs/EXTERNAL/yosys-slang @@ -0,0 +1 @@ +Subproject commit 76b83eb5b73ba871797e6db7bc5fed10af380be4 diff --git a/vtr_flow/misc/yosys/slang_filelist.tcl b/vtr_flow/misc/yosys/slang_filelist.tcl new file mode 100644 index 00000000000..2f5364ef21b --- /dev/null +++ b/vtr_flow/misc/yosys/slang_filelist.tcl @@ -0,0 +1,24 @@ +#Parameters: +# +# circuit_list - list of circuits passed into the flow +# file_list - text file being written to that will contain +# the names of circuits from circuit list. +# +#Function: +# +# Validates file extensions of input files and writes the names +# of input files to the file list to be read by yosys-slang. + +proc build_filelist { circuit_list file_list } { + set fh [open $file_list "w"] + foreach f $circuit_list { + set ext [string tolower [file extension $f]] + if {$ext == ".sv" || $ext == ".svh" || $ext == ".v" || $ext == ".vh"} { + puts $fh $f + } else { + close $fh + error "Unsupported file type. Yosys-Slang accepts .sv .svh .v .vh. File {$f}" + } + } + close $fh +} diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index 24bae6877cc..114c640b0ec 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -1,22 +1,30 @@ yosys -import - plugin -i parmys -yosys -import read_verilog -nomem2reg +/parmys/vtr_primitives.v setattr -mod -set keep_hierarchy 1 single_port_ram setattr -mod -set keep_hierarchy 1 dual_port_ram - -# synlig path error handling -if {[catch {set synlig $::env(synlig_exe_path)} err]} { - puts "Error: $err" - puts "synlig_exe_path is not set" +setattr -mod -set keep 1 dual_port_ram + +# yosys-slang plugin error handling +if {$env(PARSER) == "slang" } { + if {![info exists ::env(yosys_slang_path)]} { + puts "Error: $err" + puts "yosys_slang_path is not set" + } elseif {![file exists $::env(yosys_slang_path)]} { + error "Error: cannot find plugin at '$::env(yosys_slang_path)'. Run make with CMake param -DSLANG_SYSTEMVERILOG=ON to enable yosys-slang plugin." + } else { + plugin -i slang + yosys -import + puts "Using yosys-slang as yosys frontend" + } +} elseif {$env(PARSER) == "default" } { + yosys -import + puts "Using Yosys read_verilog as yosys frontend" } else { - set synlig $::env(synlig_exe_path) - puts "Using parmys as partial mapper" + error "Invalid PARSER" } - # arch file: QQQ # input files: [XXX] # other args: [YYY] @@ -25,15 +33,15 @@ if {[catch {set synlig $::env(synlig_exe_path)} err]} { parmys_arch -a QQQ -if {$env(PARSER) == "surelog" } { - puts "Using Synlig read_uhdm command" - - exec $synlig -p "read_uhdm XXX" - -} elseif {$env(PARSER) == "system-verilog" } { - puts "Using Synlig read_systemverilog " - exec $synlig -p "read_systemverilog XXX" - +if {$env(PARSER) == "slang" } { + # Create a file list containing the name(s) of file(s) \ + # to read together with read_slang + source [file join [pwd] "slang_filelist.tcl"] + set readfile [file join [pwd] "filelist.txt"] + #Writing names of circuit files to file list + build_filelist {XXX} $readfile + puts "Using Yosys read_slang command" + read_slang -C $readfile } elseif {$env(PARSER) == "default" } { puts "Using Yosys read_verilog command" read_verilog -sv -nolatches XXX @@ -74,13 +82,10 @@ techmap -map +/parmys/aldffe2dff.v opt -full # Separate options for Parmys execution (Verilog or SystemVerilog) -if {$env(PARSER) == "default"} { +if {$env(PARSER) == "default" || $env(PARSER) == "slang"} { # For Verilog, use -nopass for a simpler, faster flow parmys -a QQQ -nopass -c CCC YYY -} elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} { - # For Synlig SystemVerilog, run additional passes to handle complexity - parmys -a QQQ -c CCC YYY -} +} opt -full @@ -95,4 +100,4 @@ stat hierarchy -check -auto-top -purge_lib -write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ \ No newline at end of file +write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index ae0bd0a1c35..72415d6b83a 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -22,7 +22,7 @@ ".ys": "RTLIL", } -YOSYS_PARSERS = ["default", "surelog", "system-verilog"] +YOSYS_PARSERS = ["default", "slang"] def create_circuits_list(main_circuit, include_files): @@ -191,8 +191,10 @@ def run( if yosys_exec is None: yosys_exec = str(vtr.paths.yosys_exe_path) + yosys_helper_base_script = None if yosys_script is None: yosys_base_script = str(vtr.paths.yosys_script_path) + yosys_helper_base_script = str(vtr.paths.yosys_helper_script_path) else: yosys_base_script = str(Path(yosys_script).resolve()) @@ -201,6 +203,12 @@ def run( yosys_script_full_path = str(temp_dir / yosys_script) shutil.copyfile(yosys_base_script, yosys_script_full_path) + if yosys_helper_base_script is not None: + # Copy the yosys-slang helper script file + yosys_helper_script = "slang_filelist.tcl" + yosys_helper_script_full_path = str(temp_dir / yosys_helper_script) + shutil.copyfile(yosys_helper_base_script, yosys_helper_script_full_path) + # Copy the VTR memory blocks file architecture_file_path = str(vtr.paths.scripts_path / architecture_file) @@ -233,12 +241,12 @@ def run( odin_config_full_path, ) - # Set the synlig exe script path in the environment variable - # (handle if it is not set or system-verilog OFF) + # Set the slang exe script path in the environment variable + # (handle if it is not set or yosys-slang OFF) try: - os.environ["synlig_exe_path"] = str(vtr.paths.synlig_exe_path) + os.environ["yosys_slang_path"] = str(vtr.paths.yosys_slang_path) except KeyError: - os.environ["synlig_exe_path"] = "/dummy/path" + os.environ["yosys_slang_path"] = "/dummy/path" # set the parser if parmys_args["parser"] in YOSYS_PARSERS: @@ -246,7 +254,8 @@ def run( del parmys_args["parser"] else: raise vtr.VtrError( - "Invalid parser is specified for Yosys, available parsers are [{}]".format( + parmys_args["parser"] + + "Invalid parser is specified for Yosys. Parsers are [{}]".format( " ".join(str(x) for x in YOSYS_PARSERS) ) ) diff --git a/vtr_flow/scripts/python_libs/vtr/paths.py b/vtr_flow/scripts/python_libs/vtr/paths.py index 2ab1e4c31b5..ce65148ffef 100644 --- a/vtr_flow/scripts/python_libs/vtr/paths.py +++ b/vtr_flow/scripts/python_libs/vtr/paths.py @@ -21,6 +21,8 @@ yosys_exe_path = yosys_path / "yosys" yosys_tcl_path = vtr_flow_path / "misc" / "yosys" yosys_script_path = yosys_tcl_path / "synthesis.tcl" +yosys_helper_script_path = yosys_tcl_path / "slang_filelist.tcl" +yosys_slang_path = root_path / "build" / "share" / "yosys" / "plugins" / "slang.so" # Synlig paths synlig_path = root_path / "build" / "bin" / "synlig_install" diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt index 4c09466d341..2af1583c159 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt @@ -46,4 +46,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements_fixed_chan_width.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 \ No newline at end of file +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt index 5005a12aaca..f47770e46ec 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt @@ -12,14 +12,14 @@ archs_dir=arch/timing # Add circuits to list to sweep -#include_list_add=display_control.sv -#include_list_add=timer.sv -#include_list_add=debounce.sv +include_list_add=display_control.sv +include_list_add=timer.sv +include_list_add=debounce.sv # Add circuits to list to sweep -#circuit_list_add=button_controller.sv +#circuit_list_add=flattened_button_controller.sv -circuit_list_add=flattened_button_controller.sv +circuit_list_add=button_controller.sv # Add architectures to list to sweep @@ -35,4 +35,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog +script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt index 0ba1c65ca48..d93276a1a5a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml button_controller.sv common 1.80 vpr 66.81 MiB -1 -1 0.76 56284 3 0.06 -1 -1 36748 -1 -1 13 3 0 0 success 33883b0-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-21T17:24:52 gh-actions-runner-vtr-auto-spawned151 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 68412 3 12 252 216 1 125 28 7 7 49 clb auto 28.2 MiB 0.09 426 1582 344 1156 82 66.8 MiB 0.02 0.00 2.14586 -130.671 -2.14586 2.14586 0.05 0.000235558 0.000213568 0.0116245 0.0106724 40 699 17 1.07788e+06 700622 95414.1 1947.23 0.33 0.0977526 0.0831919 3948 17640 -1 608 14 464 649 15787 5088 2.43268 2.43268 -139.129 -2.43268 0 0 120731. 2463.90 0.02 0.02 0.01 -1 -1 0.02 0.0126647 0.0116072 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml button_controller.sv common 0.92 vpr 68.15 MiB -1 -1 0.16 34148 3 0.06 -1 -1 36600 -1 -1 15 3 0 0 success v8.0.0-13290-gb84275926-dirty release IPO VTR_ASSERT_LEVEL=2 debug_logging GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-07-10T15:38:09 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/scripts 69788 3 12 254 218 1 124 30 7 7 49 clb auto 28.6 MiB 0.07 675.868 408 1456 290 1097 69 68.2 MiB 0.02 0.00 2.29626 2.1231 -130.392 -2.1231 2.1231 0.02 0.000203394 0.000182992 0.00887761 0.00812764 -1 -1 -1 -1 34 748 19 1.07788e+06 808410 84249.8 1719.38 0.17 0.066483 0.0578088 3756 15224 -1 619 14 472 643 15432 5486 2.26692 2.26692 -137.479 -2.26692 0 0 103542. 2113.11 0.00 0.02 0.01 -1 -1 0.00 0.0111772 0.010392 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt index c59221ce1d4..70c60b720f8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt @@ -32,4 +32,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog +script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt index b98b60543a3..f6cba8ff913 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml pulse_led.v common 0.78 vpr 65.65 MiB -1 -1 0.33 48464 2 0.02 -1 -1 35352 -1 -1 3 9 0 0 success 33883b0-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-21T17:24:52 gh-actions-runner-vtr-auto-spawned151 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67224 9 3 145 109 1 14 15 5 5 25 clb auto 27.3 MiB 0.02 26 177 38 133 6 65.6 MiB 0.00 0.00 1.225 -51.7876 -1.225 1.225 0.01 0.000107722 9.7932e-05 0.00192273 0.00179338 18 44 3 323364 161682 19301.3 772.054 0.02 0.00557779 0.00521101 1386 3298 -1 52 2 13 13 323 175 1.225 1.225 -52.7217 -1.225 0 0 24611.1 984.442 0.00 0.00 0.00 -1 -1 0.00 0.00303037 0.00287872 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml flattened_pulse_width_led.sv common 0.56 vpr 67.34 MiB -1 -1 0.10 34020 2 0.02 -1 -1 35132 -1 -1 3 9 0 0 success v8.0.0-13290-gb84275926-dirty release IPO VTR_ASSERT_LEVEL=2 debug_logging GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-07-10T15:38:09 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/tasks 68956 9 3 145 109 1 14 15 5 5 25 clb auto 28.4 MiB 0.02 55 43 51 16 34 1 67.3 MiB 0.00 0.00 1.225 1.225 -51.8382 -1.225 1.225 0.01 0.000107511 9.5853e-05 0.00103186 0.00097788 -1 -1 -1 -1 18 38 1 323364 161682 19301.3 772.054 0.05 0.00741415 0.00671207 1386 3298 -1 36 1 11 11 135 79 1.225 1.225 -51.9895 -1.225 0 0 24611.1 984.442 0.00 0.00 0.00 -1 -1 0.00 0.00313839 0.00304238 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt index c2c180dab1d..ee62c8c894a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt @@ -12,13 +12,14 @@ archs_dir=arch/timing # Add circuits to list to sweep -#include_list_add=timer.sv -#include_list_add=display_control.sv -#include_list_add=time_counter.sv -#include_list_add=modify_count.sv +include_list_add=modify_count.sv +include_list_add=display_control.sv +include_list_add=time_counter.sv +include_list_add=timer.sv # Add circuits to list to sweep -circuit_list_add=flattened_timer.sv +#circuit_list_add=flattened_timer.sv +circuit_list_add=clock.sv # Add architectures to list to sweep @@ -34,4 +35,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog +script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt index 36401994979..5210285784d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml clock.sv common 1.54 vpr 65.80 MiB -1 -1 0.69 49624 4 0.07 -1 -1 35560 -1 -1 10 3 0 0 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:44 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67380 3 12 261 222 1 119 25 6 6 36 clb auto 27.3 MiB 0.13 425 65.8 MiB 0.01 0.00 2.39956 -129.682 -2.39956 2.39956 0.03 9.565e-05 7.3348e-05 0.00427643 0.00376691 30 695 17 646728 538940 51438.4 1428.85 0.08 0.0252184 0.021744 2512 8913 -1 547 11 355 516 15625 5833 0 0 15625 5833 516 418 0 0 882 752 0 0 986 882 0 0 552 459 0 0 6460 1703 0 0 6229 1619 0 0 516 0 0 161 222 192 1871 0 0 2.70547 2.70547 -144.28 -2.70547 0 0 63526.2 1764.62 0.01 0.01 0.01 -1 -1 0.01 0.00924855 0.0087123 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml clock.sv common 1.00 vpr 68.54 MiB -1 -1 0.14 33892 4 0.07 -1 -1 36424 -1 -1 12 3 0 0 success v8.0.0-13290-gb84275926-dirty release IPO VTR_ASSERT_LEVEL=2 debug_logging GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-07-10T15:38:09 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/scripts 70180 3 12 261 222 1 119 27 6 6 36 clb auto 29.0 MiB 0.16 535.691 470 107 18 81 8 68.5 MiB 0.01 0.00 2.40548 2.45562 -139.625 -2.45562 2.45562 0.01 0.000220295 0.000194259 0.00283635 0.00272878 -1 -1 -1 -1 26 702 45 646728 646728 45684.2 1269.00 0.19 0.0790139 0.0683134 2404 7935 -1 576 16 443 680 18334 7784 2.53617 2.53617 -149.735 -2.53617 0 0 56055.2 1557.09 0.00 0.02 0.00 -1 -1 0.00 0.0131357 0.0121975 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt new file mode 100644 index 00000000000..a7baf142692 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt @@ -0,0 +1,37 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/system_verilog/koios_sv +includes_dir=benchmarks/system_verilog/koios_sv + +# Path to directory of architectures to use +archs_dir=arch/timing + + +# Add circuits to list to sweep +#include_list_add=display_control.sv +#include_list_add=timer.sv +#include_list_add=debounce.sv + +# Add circuits to list to sweep +circuit_list_add=deepfreeze.style1.sv + + + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/golden_results.txt new file mode 100644 index 00000000000..20faa1c1855 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml deepfreeze.style1.sv common 436.14 parmys 1.86 GiB -1 -1 411.69 1951548 3 0.26 -1 -1 39048 -1 -1 569 3 0 0 success v8.0.0-13294-ga4090df7f-dirty release IPO VTR_ASSERT_LEVEL=2 debug_logging GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-07-11T13:46:55 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/scripts 84760 3 513 1838 2166 1 824 1085 30 30 900 clb auto 41.9 MiB 0.69 4207.31 1231 575104 399781 38987 136336 82.6 MiB 0.70 0.01 4.09934 2.34735 -601.556 -2.34735 2.34735 0.70 0.00153716 0.00141826 0.186598 0.172244 -1 -1 -1 -1 26 2161 10 4.8774e+07 3.06657e+07 1.76811e+06 1964.57 2.04 0.502771 0.465859 83012 347295 -1 1972 8 569 767 17591 4270 2.4085 2.4085 -599.698 -2.4085 0 0 2.17697e+06 2418.86 0.08 0.06 0.18 -1 -1 0.08 0.0661326 0.0635241 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt index 509f77a6434..ddfaa46795d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt @@ -1,3 +1,4 @@ regression_tests/vtr_reg_system_verilog/f4pga_button_controller/ +regression_tests/vtr_reg_system_verilog/koios_sv/ regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/ regression_tests/vtr_reg_system_verilog/f4pga_timer/