From 1788fe36ca420b1b5e41a7a381e7e554e9b3a901 Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Fri, 13 Jun 2025 14:09:28 -0600 Subject: [PATCH 1/9] added check that would have made debuging easier --- parmys/parmys-plugin/netlist/netlist_utils.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/parmys/parmys-plugin/netlist/netlist_utils.cc b/parmys/parmys-plugin/netlist/netlist_utils.cc index 9c3fb060b4f..60fc7025f04 100644 --- a/parmys/parmys-plugin/netlist/netlist_utils.cc +++ b/parmys/parmys-plugin/netlist/netlist_utils.cc @@ -485,6 +485,7 @@ void remap_pin_to_new_net(npin_t *pin, nnet_t *new_net) *-----------------------------------------------------------------------*/ void remap_pin_to_new_node(npin_t *pin, nnode_t *new_node, int pin_idx) { + oassert(pin != NULL); if (pin->type == INPUT) { /* clean out the entry in the old net */ pin->node->input_pins[pin->pin_node_idx] = NULL; From 19653eea1cbcd6999252098b7986c04771be35d0 Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Fri, 13 Jun 2025 14:43:22 -0600 Subject: [PATCH 2/9] fix multiplier --- parmys/parmys-plugin/core/multiplier.cc | 180 +++++++++++++++++------- 1 file changed, 130 insertions(+), 50 deletions(-) diff --git a/parmys/parmys-plugin/core/multiplier.cc b/parmys/parmys-plugin/core/multiplier.cc index befb0b337bd..eeb9d8195bb 100644 --- a/parmys/parmys-plugin/core/multiplier.cc +++ b/parmys/parmys-plugin/core/multiplier.cc @@ -935,7 +935,7 @@ void init_multiplier_adder(nnode_t *node, nnode_t *parent, int a, int b) *-----------------------------------------------------------------------*/ void split_multiplier(nnode_t *node, int a0, int b0, int a1, int b1, netlist_t *netlist) { - nnode_t *a0b0, *a0b1, *a1b0, *a1b1, *addsmall, *addbig; + nnode_t *a0b0, *a0b1, *a1b0, *a1b1, *addsmall, *addsmall2, *addbig; int size; /* Check for a legitimate split */ @@ -974,50 +974,127 @@ void split_multiplier(nnode_t *node, int a0, int b0, int a1, int b1, netlist_t * init_split_multiplier(node, a1b0, a0, a1, 0, b0, a1b1, a0b0); mult_list = insert_in_vptr_list(mult_list, a1b0); - /* New node for the initial add */ - addsmall = allocate_nnode(node->loc); - addsmall->name = (char *)vtr::malloc(strlen(node->name) + 6); - strcpy(addsmall->name, node->name); - strcat(addsmall->name, "-add0"); - // this addition will have a carry out in the worst case, add to input pins and connect then to gnd - init_multiplier_adder(addsmall, a1b0, a1b0->num_output_pins + 1, a0b1->num_output_pins + 1); - - /* New node for the BIG add */ - addbig = allocate_nnode(node->loc); - addbig->name = (char *)vtr::malloc(strlen(node->name) + 6); - strcpy(addbig->name, node->name); - strcat(addbig->name, "-add1"); - init_multiplier_adder(addbig, addsmall, addsmall->num_output_pins, a0b0->num_output_pins - b0 + a1b1->num_output_pins); - - // connect inputs to port a of addsmall - for (int i = 0; i < a1b0->num_output_pins; i++) - connect_nodes(a1b0, i, addsmall, i); - add_input_pin_to_node(addsmall, get_zero_pin(netlist), a1b0->num_output_pins); - // connect inputs to port b of addsmall - for (int i = 0; i < a0b1->num_output_pins; i++) - connect_nodes(a0b1, i, addsmall, i + addsmall->input_port_sizes[0]); - add_input_pin_to_node(addsmall, get_zero_pin(netlist), a0b1->num_output_pins + addsmall->input_port_sizes[0]); - - // connect inputs to port a of addbig - size = addsmall->num_output_pins; - for (int i = 0; i < size; i++) - connect_nodes(addsmall, i, addbig, i); - - // connect inputs to port b of addbig - for (int i = b0; i < a0b0->output_port_sizes[0]; i++) - connect_nodes(a0b0, i, addbig, i - b0 + size); - size = size + a0b0->output_port_sizes[0] - b0; - for (int i = 0; i < a1b1->output_port_sizes[0]; i++) - connect_nodes(a1b1, i, addbig, i + size); - - // remap the multiplier outputs coming directly from a0b0 - for (int i = 0; i < b0; i++) { - remap_pin_to_new_node(node->output_pins[i], a0b0, i); - } + // using the balenced addition method only works if a0 and b0 are the same size + // (i.e. if the input ports on the hardware multiplier are equal) + if (b0 == a0) { + /* New node for the initial add */ + addsmall = allocate_nnode(node->loc); + addsmall->name = (char *)vtr::malloc(strlen(node->name) + 6); + strcpy(addsmall->name, node->name); + strcat(addsmall->name, "-add0"); + // this addition will have a carry out in the worst case, add to input pins and connect then to gnd + init_multiplier_adder(addsmall, a1b0, a1b0->num_output_pins + 1, a0b1->num_output_pins + 1); + + // connect inputs to port a of addsmall + for (int i = 0; i < a1b0->num_output_pins; i++) + connect_nodes(a1b0, i, addsmall, i); + + add_input_pin_to_node(addsmall, get_zero_pin(netlist), a1b0->num_output_pins); + // connect inputs to port b of addsmall + for (int i = 0; i < a0b1->num_output_pins; i++) + connect_nodes(a0b1, i, addsmall, i + addsmall->input_port_sizes[0]); + add_input_pin_to_node(addsmall, get_zero_pin(netlist), a0b1->num_output_pins + addsmall->input_port_sizes[0]); + + /* New node for the BIG add */ + addbig = allocate_nnode(node->loc); + addbig->name = (char *)vtr::malloc(strlen(node->name) + 6); + strcpy(addbig->name, node->name); + strcat(addbig->name, "-add1"); + init_multiplier_adder(addbig, addsmall, addsmall->num_output_pins, a0b0->num_output_pins - b0 + a1b1->num_output_pins); + + // connect inputs to port a of addbig + size = addsmall->num_output_pins; + for (int i = 0; i < size; i++) + connect_nodes(addsmall, i, addbig, i); + + // connect inputs to port b of addbig + for (int i = b0; i < a0b0->output_port_sizes[0]; i++) + connect_nodes(a0b0, i, addbig, i - b0 + size); + size = size + a0b0->output_port_sizes[0] - b0; + for (int i = 0; i < a1b1->output_port_sizes[0]; i++) + connect_nodes(a1b1, i, addbig, i + size); + + // remap the multiplier outputs coming directly from a0b0 + for (int i = 0; i < b0; i++) { + remap_pin_to_new_node(node->output_pins[i], a0b0, i); + } - // remap the multiplier outputs coming from addbig - for (int i = 0; i < addbig->num_output_pins; i++) { - remap_pin_to_new_node(node->output_pins[i + b0], addbig, i); + // remap the multiplier outputs coming from addbig + for (int i = 0; i < addbig->num_output_pins; i++) { + remap_pin_to_new_node(node->output_pins[i + b0], addbig, i); + } + } else { + + /* New node for the initial add */ + addsmall = allocate_nnode(node->loc); + addsmall->name = (char *)vtr::malloc(strlen(node->name) + 6); + strcpy(addsmall->name, node->name); + strcat(addsmall->name, "-add0"); + // All additions in this version have the posibility of a carry out in the worst case + init_multiplier_adder(addsmall, a1b0, a1b0->num_output_pins + a0 + 1, a0b1->num_output_pins + b0 + 1); + // A0 and B0 are our hardware multiplier sizes + + int max = a0b1->num_output_pins; + if (a1b0->num_output_pins > max) { + max = a1b0->num_output_pins; + } + + // right shift + for (int i = 0; i < a0; i++) + add_input_pin_to_node(addsmall, get_zero_pin(netlist), i); + + // connect inputs to port a of addsmall + for (int i = 0; i < a1b0->num_output_pins; i++) + connect_nodes(a1b0, i, addsmall, i + a0); + + add_input_pin_to_node(addsmall, get_zero_pin(netlist), a1b0->num_output_pins); // for carry + // right shift + for (int i = 0; i < b0; i++) + add_input_pin_to_node(addsmall, get_zero_pin(netlist), i + addsmall->input_port_sizes[0]); + // connect inputs to port b of addsmall + for (int i = 0; i < max; i++) + connect_nodes(a0b1, i, addsmall, i + addsmall->input_port_sizes[0] + b0); + add_input_pin_to_node(addsmall, get_zero_pin(netlist), a0b1->num_output_pins + addsmall->input_port_sizes[0]); + + addsmall2 = allocate_nnode(node->loc); + addsmall2->name = (char *)vtr::malloc(strlen(node->name) + 6); + strcpy(addsmall2->name, node->name); + strcat(addsmall2->name, "-add1"); + // this addition can have a carry in the worst case. + init_multiplier_adder(addsmall2, a0b0, a0b0->num_output_pins + 1, addsmall->num_output_pins + 1); + + for (int i = 0; i < a0b0->num_output_pins; i++) + connect_nodes(a0b0, i, addsmall2, i); + + add_input_pin_to_node(addsmall2, get_zero_pin(netlist), a0b0->num_output_pins); + + for (int i = 0; i < addsmall->num_output_pins; i++) + connect_nodes(addsmall, i, addsmall2, i + addsmall2->input_port_sizes[0]); + add_input_pin_to_node(addsmall2, get_zero_pin(netlist), addsmall->num_output_pins + addsmall2->input_port_sizes[0]); + + addbig = allocate_nnode(node->loc); + addbig->name = (char *)vtr::malloc(strlen(node->name) + 6); + strcpy(addbig->name, node->name); + strcat(addbig->name, "-add2"); + init_multiplier_adder(addbig, addsmall2, addsmall2->num_output_pins + 1, a1b1->num_output_pins + a0b0->num_output_pins + 1); + + for (int i = 0; i < addsmall2->num_output_pins; i++) + connect_nodes(addsmall2, i, addbig, i); + add_input_pin_to_node(addbig, get_zero_pin(netlist), addsmall2->num_output_pins); + + for (int i = 0; i < a0b0->num_output_pins; i++) + add_input_pin_to_node(addbig, get_zero_pin(netlist), i + addsmall2->num_output_pins); + + for (int i = 0; i < a1b1->num_output_pins; i++) + connect_nodes(a1b1, i, addbig, i + addbig->input_port_sizes[0] + a0b0->num_output_pins); + add_input_pin_to_node(addbig, get_zero_pin(netlist), a1b1->num_output_pins + addbig->input_port_sizes[0]); + + max = a0; + if (b0 > a0) + max = b0; + for (int i = 0; i < addbig->num_output_pins; i++) { + remap_pin_to_new_node(node->output_pins[i], addbig, i); + } } // CLEAN UP @@ -1058,7 +1135,6 @@ void split_multiplier_a(nnode_t *node, int a0, int a1, int b) strcat(a0b->name, "-0"); init_split_multiplier(node, a0b, 0, a0, 0, b, nullptr, nullptr); mult_list = insert_in_vptr_list(mult_list, a0b); - /* New node for a1b multiply */ a1b = allocate_nnode(node->loc); a1b->name = (char *)vtr::malloc(strlen(node->name) + 3); @@ -1182,7 +1258,6 @@ void pad_multiplier(nnode_t *node, netlist_t *netlist) oassert(node->type == MULTIPLY); oassert(hard_multipliers != NULL); - sizea = node->input_port_sizes[0]; sizeb = node->input_port_sizes[1]; sizeout = node->output_port_sizes[0]; @@ -1197,6 +1272,13 @@ void pad_multiplier(nnode_t *node, netlist_t *netlist) } diffa = ina - sizea; diffb = inb - sizeb; + // input multiplier size on middle range of unequal Hard Block size(ex; mul_size>18 && mul_size<25) + if (diffb < 0) { + std::swap(ina, inb); + diffa = ina - sizea; + diffb = inb - sizeb; + } + diffout = hard_multipliers->outputs->size - sizeout; if (configuration.split_hard_multiplier == 1) { @@ -1279,11 +1361,10 @@ void iterate_multipliers(netlist_t *netlist) int mula, mulb; int a0, a1, b0, b1; nnode_t *node; - /* Can only perform the optimisation if hard multipliers exist! */ if (hard_multipliers == NULL) return; - + // std::cin.get(); sizea = hard_multipliers->inputs->size; sizeb = hard_multipliers->inputs->next->size; if (sizea < sizeb) { @@ -1311,7 +1392,6 @@ void iterate_multipliers(netlist_t *netlist) sizea = sizeb; sizeb = swap; } - /* Do I need to split the multiplier on both inputs? */ if ((mula > sizea) && (mulb > sizeb)) { a0 = sizea; @@ -1888,4 +1968,4 @@ void free_multipliers() hard_multipliers->instances = NULL; } -} +} \ No newline at end of file From c713f8551e5e3a38cee8ebbe751f3768b428f186 Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Sat, 14 Jun 2025 03:20:05 -0600 Subject: [PATCH 3/9] new method, passing parmys --- parmys/parmys-plugin/core/multiplier.cc | 100 +++++++++++++++--------- 1 file changed, 61 insertions(+), 39 deletions(-) diff --git a/parmys/parmys-plugin/core/multiplier.cc b/parmys/parmys-plugin/core/multiplier.cc index eeb9d8195bb..7b7f9b1f641 100644 --- a/parmys/parmys-plugin/core/multiplier.cc +++ b/parmys/parmys-plugin/core/multiplier.cc @@ -1024,74 +1024,96 @@ void split_multiplier(nnode_t *node, int a0, int b0, int a1, int b1, netlist_t * remap_pin_to_new_node(node->output_pins[i + b0], addbig, i); } } else { - - /* New node for the initial add */ + /* Expounding upon the description for the method in this function.a0 + if we have two numbers A and B and we have a hardware multiplier of size a0xb0, + we can split them into two parts: + A = A1 << a0 + A0 + B = B1 << b0 + B0 + where A1 and B1 are the high bits of A and B, and A0 and B0 are the low bits. + The multiplication of A and B can be expressed as: + A * B = (A1 << a0 + A0) * (B1 << b0 + B0) + = {A1 * B1 << (a0 + b0)} + {(A1 * B0) << a0 + (A0 * B1) << b0} + {A0 * B0} + we define split the editions up like so: + addsmall = (A1 * B0) << a0 + (A0 * B1) << b0 + addsmall2 = (A1 * B1 << (a0 + b0)) + (A0 * B0) // Will not have carry + addbig = addsmall + addsmall2 + + */ + /////////////// Addsmall ///////////////////// addsmall = allocate_nnode(node->loc); addsmall->name = (char *)vtr::malloc(strlen(node->name) + 6); strcpy(addsmall->name, node->name); strcat(addsmall->name, "-add0"); - // All additions in this version have the posibility of a carry out in the worst case - init_multiplier_adder(addsmall, a1b0, a1b0->num_output_pins + a0 + 1, a0b1->num_output_pins + b0 + 1); - // A0 and B0 are our hardware multiplier sizes - - int max = a0b1->num_output_pins; - if (a1b0->num_output_pins > max) { - max = a1b0->num_output_pins; - } + init_multiplier_adder(addsmall, a1b0, a1b0->num_output_pins + a0, a0b1->num_output_pins + b0); - // right shift - for (int i = 0; i < a0; i++) + // The first a0 pins of addsmall input connecting to a1b0 are connected to zero + for (int i = 0; i < a0; i++) { add_input_pin_to_node(addsmall, get_zero_pin(netlist), i); + } // connect inputs to port a of addsmall - for (int i = 0; i < a1b0->num_output_pins; i++) + for (int i = 0; i < a1b0->num_output_pins; i++) { connect_nodes(a1b0, i, addsmall, i + a0); + } + + // add zero pin for carry + // add_input_pin_to_node(addsmall, get_zero_pin(netlist), a1b0->num_output_pins + a0); - add_input_pin_to_node(addsmall, get_zero_pin(netlist), a1b0->num_output_pins); // for carry - // right shift - for (int i = 0; i < b0; i++) + // The first b0 pins of addsmall input connecting to a0b1 are connected to zero + for (int i = 0; i < b0; i++) { add_input_pin_to_node(addsmall, get_zero_pin(netlist), i + addsmall->input_port_sizes[0]); + } + // connect inputs to port b of addsmall - for (int i = 0; i < max; i++) + for (int i = 0; i < a0b1->num_output_pins; i++) { connect_nodes(a0b1, i, addsmall, i + addsmall->input_port_sizes[0] + b0); - add_input_pin_to_node(addsmall, get_zero_pin(netlist), a0b1->num_output_pins + addsmall->input_port_sizes[0]); + } + + // add zero pin for carry + // add_input_pin_to_node(addsmall, get_zero_pin(netlist), a0b1->num_output_pins + addsmall->input_port_sizes[0] + b0); + /////////////// Addsmall2 ///////////////////// addsmall2 = allocate_nnode(node->loc); addsmall2->name = (char *)vtr::malloc(strlen(node->name) + 6); strcpy(addsmall2->name, node->name); strcat(addsmall2->name, "-add1"); - // this addition can have a carry in the worst case. - init_multiplier_adder(addsmall2, a0b0, a0b0->num_output_pins + 1, addsmall->num_output_pins + 1); + init_multiplier_adder(addsmall2, a1b1, a1b1->num_output_pins + a0 + b0, a0b0->num_output_pins); - for (int i = 0; i < a0b0->num_output_pins; i++) - connect_nodes(a0b0, i, addsmall2, i); + // connect first a0+ b0 pins of addsmall2 to zero + for (int i = 0; i < a0 + b0; i++) { + add_input_pin_to_node(addsmall2, get_zero_pin(netlist), i); + } - add_input_pin_to_node(addsmall2, get_zero_pin(netlist), a0b0->num_output_pins); + // connect inputs to port a of addsmall2 + for (int i = 0; i < a1b1->num_output_pins; i++) { + connect_nodes(a1b1, i, addsmall2, i + a0 + b0); + } - for (int i = 0; i < addsmall->num_output_pins; i++) - connect_nodes(addsmall, i, addsmall2, i + addsmall2->input_port_sizes[0]); - add_input_pin_to_node(addsmall2, get_zero_pin(netlist), addsmall->num_output_pins + addsmall2->input_port_sizes[0]); + // connect inputs to port b of addsmall2 + for (int i = 0; i < a0b0->output_port_sizes[0]; i++) { + connect_nodes(a0b0, i, addsmall2, i + addsmall2->input_port_sizes[0]); + } + /////////////// Addbig ///////////////////// addbig = allocate_nnode(node->loc); addbig->name = (char *)vtr::malloc(strlen(node->name) + 6); strcpy(addbig->name, node->name); strcat(addbig->name, "-add2"); - init_multiplier_adder(addbig, addsmall2, addsmall2->num_output_pins + 1, a1b1->num_output_pins + a0b0->num_output_pins + 1); - - for (int i = 0; i < addsmall2->num_output_pins; i++) - connect_nodes(addsmall2, i, addbig, i); - add_input_pin_to_node(addbig, get_zero_pin(netlist), addsmall2->num_output_pins); + init_multiplier_adder(addbig, addsmall, addsmall->num_output_pins, addsmall2->num_output_pins); - for (int i = 0; i < a0b0->num_output_pins; i++) - add_input_pin_to_node(addbig, get_zero_pin(netlist), i + addsmall2->num_output_pins); + // connect inputs to port a of addbig + for (int i = 0; i < addsmall->num_output_pins; i++) { + connect_nodes(addsmall, i, addbig, i); + } + // add_input_pin_to_node(addbig, get_zero_pin(netlist), addsmall->num_output_pins); - for (int i = 0; i < a1b1->num_output_pins; i++) - connect_nodes(a1b1, i, addbig, i + addbig->input_port_sizes[0] + a0b0->num_output_pins); - add_input_pin_to_node(addbig, get_zero_pin(netlist), a1b1->num_output_pins + addbig->input_port_sizes[0]); + // connect inputs to port b of addbig + for (int i = 0; i < addsmall2->num_output_pins; i++) { + connect_nodes(addsmall2, i, addbig, i + addbig->input_port_sizes[0]); + } + // add_input_pin_to_node(addbig, get_zero_pin(netlist), addsmall2->num_output_pins + addbig->input_port_sizes[0]); - max = a0; - if (b0 > a0) - max = b0; + // remap the multiplier outputs coming directly from a0b0 for (int i = 0; i < addbig->num_output_pins; i++) { remap_pin_to_new_node(node->output_pins[i], addbig, i); } From b900ffdc99e0b11f1ceeae85899a51568b10bf0c Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Mon, 16 Jun 2025 13:00:25 -0600 Subject: [PATCH 4/9] cleanup and clarified comments --- parmys/parmys-plugin/core/multiplier.cc | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/parmys/parmys-plugin/core/multiplier.cc b/parmys/parmys-plugin/core/multiplier.cc index 7b7f9b1f641..e144d864249 100644 --- a/parmys/parmys-plugin/core/multiplier.cc +++ b/parmys/parmys-plugin/core/multiplier.cc @@ -1024,27 +1024,28 @@ void split_multiplier(nnode_t *node, int a0, int b0, int a1, int b1, netlist_t * remap_pin_to_new_node(node->output_pins[i + b0], addbig, i); } } else { - /* Expounding upon the description for the method in this function.a0 + /* Expounding upon the description for the method in this function. if we have two numbers A and B and we have a hardware multiplier of size a0xb0, we can split them into two parts: A = A1 << a0 + A0 B = B1 << b0 + B0 where A1 and B1 are the high bits of A and B, and A0 and B0 are the low bits. + Note that len(A0) = a0 and len(B0) = b0 by definition. The multiplication of A and B can be expressed as: A * B = (A1 << a0 + A0) * (B1 << b0 + B0) = {A1 * B1 << (a0 + b0)} + {(A1 * B0) << a0 + (A0 * B1) << b0} + {A0 * B0} we define split the editions up like so: - addsmall = (A1 * B0) << a0 + (A0 * B1) << b0 + addsmall = (A1 * B0) << a0 + (A0 * B1) << b0 // can have carry addsmall2 = (A1 * B1 << (a0 + b0)) + (A0 * B0) // Will not have carry addbig = addsmall + addsmall2 - + This is a slightly modified version of the Karatsuba algorithm. */ /////////////// Addsmall ///////////////////// addsmall = allocate_nnode(node->loc); addsmall->name = (char *)vtr::malloc(strlen(node->name) + 6); strcpy(addsmall->name, node->name); strcat(addsmall->name, "-add0"); - init_multiplier_adder(addsmall, a1b0, a1b0->num_output_pins + a0, a0b1->num_output_pins + b0); + init_multiplier_adder(addsmall, a1b0, a1b0->num_output_pins + a0 + 1, a0b1->num_output_pins + b0 + 1); // The first a0 pins of addsmall input connecting to a1b0 are connected to zero for (int i = 0; i < a0; i++) { @@ -1057,7 +1058,7 @@ void split_multiplier(nnode_t *node, int a0, int b0, int a1, int b1, netlist_t * } // add zero pin for carry - // add_input_pin_to_node(addsmall, get_zero_pin(netlist), a1b0->num_output_pins + a0); + add_input_pin_to_node(addsmall, get_zero_pin(netlist), a1b0->num_output_pins + a0); // The first b0 pins of addsmall input connecting to a0b1 are connected to zero for (int i = 0; i < b0; i++) { @@ -1070,7 +1071,7 @@ void split_multiplier(nnode_t *node, int a0, int b0, int a1, int b1, netlist_t * } // add zero pin for carry - // add_input_pin_to_node(addsmall, get_zero_pin(netlist), a0b1->num_output_pins + addsmall->input_port_sizes[0] + b0); + add_input_pin_to_node(addsmall, get_zero_pin(netlist), a0b1->num_output_pins + addsmall->input_port_sizes[0] + b0); /////////////// Addsmall2 ///////////////////// addsmall2 = allocate_nnode(node->loc); @@ -1100,6 +1101,9 @@ void split_multiplier(nnode_t *node, int a0, int b0, int a1, int b1, netlist_t * strcpy(addbig->name, node->name); strcat(addbig->name, "-add2"); init_multiplier_adder(addbig, addsmall, addsmall->num_output_pins, addsmall2->num_output_pins); + // Here the final addition can have a carry out in the worst case, however, + // our final product will always only be the length of the longest input port so regardless of the carry the + // final adds carry will always drop out. // connect inputs to port a of addbig for (int i = 0; i < addsmall->num_output_pins; i++) { @@ -1111,7 +1115,7 @@ void split_multiplier(nnode_t *node, int a0, int b0, int a1, int b1, netlist_t * for (int i = 0; i < addsmall2->num_output_pins; i++) { connect_nodes(addsmall2, i, addbig, i + addbig->input_port_sizes[0]); } - // add_input_pin_to_node(addbig, get_zero_pin(netlist), addsmall2->num_output_pins + addbig->input_port_sizes[0]); + // add_input_pin_to_node(addbig, get_zero_pin(netlist), addbig->input_port_sizes[0] + addsmall->num_output_pins); // remap the multiplier outputs coming directly from a0b0 for (int i = 0; i < addbig->num_output_pins; i++) { From d87e7e11fec4dc23855025b8f92b6418277eb813 Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Mon, 16 Jun 2025 13:35:50 -0600 Subject: [PATCH 5/9] add tests and golden for reg_strong --- .../vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt | 1 + .../vtr_reg_strong/strong_xilinx_flagship/config/config.txt | 1 + .../strong_xilinx_flagship/config/golden_results.txt | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt index 9fc4e235659..b8a39c21ee5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt @@ -12,6 +12,7 @@ circuits_dir=benchmarks/verilog arch_list_add=7series_BRAM_DSP_carry.xml # Add circuits to list to sweep +circuit_list_add=mcml.v circuit_list_add=LU32PEEng.v circuit_list_add=LU8PEEng.v circuit_list_add=bgm.v diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/config.txt index 67ebcf3f6cb..ccc1aea6050 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/config.txt @@ -6,6 +6,7 @@ arch_list_add=7series_BRAM_DSP_carry.xml # Add circuits to list to sweep circuit_list_add=stereovision3.v +circuit_list_add=diffeq2.v # Parse info and how to parse diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt index 157a340501b..f9a102d9372 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt @@ -1,2 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -7series_BRAM_DSP_carry.xml stereovision3.v common 2.87 vpr 72.69 MiB -1 -1 0.32 26404 4 0.08 -1 -1 35804 -1 -1 -1 11 0 -1 success v8.0.0-12999-gf153e4447-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-12T17:00:21 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 74436 11 2 303 283 2 114 35 7 7 49 CLB auto 33.4 MiB 1.15 577.007 408 947 108 584 255 72.7 MiB 0.01 0.00 3.1717 3.1717 -180.982 -3.1717 2.89952 0.12 0.000180919 0.000138049 0.00514751 0.00458797 -1 -1 -1 -1 40 911 27 1.34735e+06 1.18567e+06 152291. 3107.98 0.59 0.032835 0.0284564 6668 73471 -1 385 12 297 988 127228 60728 2.91111 2.8252 -221.503 -2.91111 -2.452 -0.04 215465. 4397.25 0.02 0.02 0.04 -1 -1 0.02 0.0099349 0.00925009 +7series_BRAM_DSP_carry.xml stereovision3.v common 2.53 vpr 72.59 MiB -1 -1 0.33 26408 4 0.08 -1 -1 36120 -1 -1 -1 11 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 74336 11 2 303 283 2 114 35 7 7 49 CLB auto 33.2 MiB 1.18 577.007 408 947 108 584 255 72.6 MiB 0.01 0.00 3.1717 3.1717 -180.982 -3.1717 2.89952 0.12 0.000171885 0.000143559 0.00458104 0.00401289 -1 -1 -1 -1 40 889 22 1.34735e+06 1.18567e+06 152291. 3107.98 0.22 0.0179847 0.0160687 6668 73471 -1 385 12 297 988 127228 60728 2.91111 2.8252 -221.503 -2.91111 -2.452 -0.04 215465. 4397.25 0.02 0.02 0.04 -1 -1 0.02 0.00962131 0.00895172 +7series_BRAM_DSP_carry.xml diffeq2.v common 48.98 vpr 129.37 MiB -1 -1 0.19 27844 5 0.09 -1 -1 38944 -1 -1 -1 66 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 132476 66 96 1819 1080 1 1150 336 26 26 676 DSP auto 40.6 MiB 2.77 20198.7 9188 64521 14520 45607 4394 119.7 MiB 0.65 0.01 22.6842 19.668 -1065.49 -19.668 19.668 3.45 0.000811128 0.000723384 0.0536543 0.0478746 -1 -1 -1 -1 74 12093 17 3.53732e+07 1.31407e+07 5.36197e+06 7931.91 33.65 0.395666 0.356239 133518 2720184 -1 10986 14 5828 10018 3165525 816384 19.4143 19.4143 -1210.49 -19.4143 -1.7 -0.034 6.54552e+06 9682.72 1.89 0.38 1.55 -1 -1 1.89 0.0458825 0.0428936 From 1391852f0493a1a1d1c1239c535441c639ff0460 Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Thu, 19 Jun 2025 10:29:19 -0600 Subject: [PATCH 6/9] Added mcml golden results to nightly --- .../vtr_xilinx_qor/config/golden_results.txt | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt index ce120048235..c16999abba4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt @@ -1,7 +1,8 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -7series_BRAM_DSP_carry.xml LU32PEEng.v common 19250.12 vpr 3.53 GiB -1 -1 85.05 1536380 97 401.39 -1 -1 380848 -1 -1 -1 114 153 -1 success v8.0.0-11597-g2b097dfa1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2024-10-17T11:29:23 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 3702192 114 102 123962 109723 1 78151 10542 114 114 12996 CLB auto 971.9 MiB 2051.84 1372550 15723982 6230234 8961888 531860 2716.0 MiB 850.65 4.89 108.226 -231571 -108.226 108.226 0.08 0.138193 0.121009 20.9801 17.9134 -1 -1 -1 -1 -1 1616189 23 7.77041e+08 6.19747e+08 2.51453e+08 19348.5 349.21 27.3637 23.0261 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -7series_BRAM_DSP_carry.xml LU8PEEng.v common 2038.38 vpr 1.02 GiB -1 -1 26.46 473708 98 36.58 -1 -1 117732 -1 -1 -1 114 45 -1 success v8.0.0-11597-g2b097dfa1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2024-10-17T11:29:23 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 1070284 114 102 36706 32285 1 22659 3186 62 62 3844 CLB auto 303.0 MiB 615.42 301086 2744964 924224 1608810 211930 812.6 MiB 90.07 0.81 110.594 -51236.9 -110.594 110.594 0.02 0.0348211 0.0304006 4.5861 3.9536 -1 -1 -1 -1 -1 354834 19 2.21078e+08 1.78196e+08 7.33801e+07 19089.5 28.08 5.92739 5.04309 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -7series_BRAM_DSP_carry.xml bgm.v common 2232.89 vpr 1.08 GiB -1 -1 22.10 654984 14 35.89 -1 -1 124492 -1 -1 -1 257 0 -1 success v8.0.0-11597-g2b097dfa1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2024-10-17T11:29:23 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 1137124 257 32 37283 34221 1 23794 3620 66 66 4356 CLB auto 335.7 MiB 466.45 295245 2920940 1018399 1814255 88286 910.4 MiB 92.90 0.91 21.8913 -27562.2 -21.8913 21.8913 0.02 0.0377186 0.033218 4.62567 3.92608 -1 -1 -1 -1 -1 413597 20 2.52497e+08 1.83282e+08 8.29171e+07 19035.1 39.64 6.17413 5.17828 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -7series_BRAM_DSP_carry.xml stereovision0.v common 493.23 vpr 468.43 MiB -1 -1 4.25 104408 5 2.86 -1 -1 69832 -1 -1 -1 169 0 -1 success v8.0.0-11597-g2b097dfa1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2024-10-17T11:29:23 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 479668 169 197 23225 21365 1 9579 1651 42 42 1764 CLB auto 167.1 MiB 246.51 70163 967297 274059 572737 120501 387.9 MiB 12.88 0.12 4.23437 -16244.7 -4.23437 4.23437 0.01 0.0103469 0.00882942 1.22561 1.03769 -1 -1 -1 -1 -1 66124 11 9.88618e+07 6.92551e+07 3.28179e+07 18604.2 6.32 1.4964 1.2619 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -7series_BRAM_DSP_carry.xml stereovision1.v common 1106.40 vpr 862.80 MiB -1 -1 3.56 116516 3 4.49 -1 -1 72468 -1 -1 -1 115 0 -1 success v8.0.0-11597-g2b097dfa1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2024-10-17T11:29:23 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 883512 115 145 22865 19302 1 10282 1530 66 66 4356 DSP auto 161.1 MiB 218.23 111593 988474 326800 631040 30634 771.3 MiB 11.98 0.10 4.92203 -20685.5 -4.92203 4.92203 0.02 0.0109393 0.00901865 1.3246 1.12536 -1 -1 -1 -1 -1 111099 12 2.52497e+08 9.58162e+07 8.29171e+07 19035.1 14.24 1.62381 1.37534 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -7series_BRAM_DSP_carry.xml stereovision2.v common 6254.18 vpr 2.04 GiB -1 -1 5.38 173084 3 2.17 -1 -1 140928 -1 -1 -1 149 0 -1 success v8.0.0-11597-g2b097dfa1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2024-10-17T11:29:23 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 2143796 149 182 55416 37075 1 33270 4005 106 106 11236 DSP auto 301.3 MiB 730.52 433336 3564709 1114274 2234226 216209 1922.3 MiB 83.75 0.70 14.9658 -47738.9 -14.9658 14.9658 0.07 0.0283938 0.0250043 3.56581 3.04154 -1 -1 -1 -1 -1 410536 17 6.67318e+08 2.78045e+08 2.17352e+08 19344.2 47.16 4.63423 3.93111 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +7series_BRAM_DSP_carry.xml mcml.v common 6028.93 vpr 4.29 GiB -1 -1 112.39 1324532 26 1575.37 -1 -1 397412 -1 -1 -1 36 159 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 4493412 36 356 199703 166091 1 96432 14448 132 132 17424 CLB auto 1373.1 MiB 1554.60 7.30767e+06 1510965 30795198 11005989 11799313 7989896 3575.2 MiB 2353.07 8.99 114.688 75.4926 -385876 -75.4926 75.4926 0.11 0.144559 0.12413 27.5533 22.7998 -1 -1 -1 -1 -1 1044733 17 1.04106e+09 8.39563e+08 3.37280e+08 19357.2 132.18 32.8963 27.1671 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +7series_BRAM_DSP_carry.xml LU32PEEng.v common 4021.40 vpr 3.52 GiB -1 -1 89.23 1523944 97 420.80 -1 -1 364304 -1 -1 -1 114 153 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 3686084 114 102 123962 109723 1 78255 10604 114 114 12996 CLB auto 1078.7 MiB 2226.89 7.50175e+06 1274738 15614502 6135197 9031079 448226 2727.3 MiB 917.29 6.53 143.442 109.472 -246691 -109.472 109.472 0.08 0.141279 0.121064 21.4205 17.832 -1 -1 -1 -1 -1 1465950 19 7.77041e+08 6.23088e+08 2.51453e+08 19348.5 154.91 27.165 22.4874 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +7series_BRAM_DSP_carry.xml LU8PEEng.v common 866.13 vpr 1.03 GiB -1 -1 28.05 472768 98 39.42 -1 -1 117816 -1 -1 -1 114 45 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 1079760 114 102 36706 32285 1 22732 3211 62 62 3844 CLB auto 336.8 MiB 618.57 1.07733e+06 293198 2726296 910892 1594196 221208 816.6 MiB 93.59 0.82 135.375 111.358 -52204.1 -111.358 111.358 0.02 0.0342582 0.0290691 4.52154 3.74248 -1 -1 -1 -1 -1 349285 16 2.21078e+08 1.79543e+08 7.33801e+07 19089.5 31.47 5.71966 4.71057 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +7series_BRAM_DSP_carry.xml bgm.v common 738.51 vpr 1.09 GiB -1 -1 23.62 654168 14 38.57 -1 -1 124128 -1 -1 -1 257 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 1147576 257 32 37283 34221 1 23859 3594 66 66 4356 CLB auto 369.5 MiB 486.01 1.42717e+06 292842 2727876 904302 1772661 50913 914.3 MiB 89.88 0.92 36.395 23.2057 -27798.9 -23.2057 23.2057 0.03 0.0420198 0.0365039 4.49405 3.75685 -1 -1 -1 -1 -1 405172 17 2.52497e+08 1.81881e+08 8.29171e+07 19035.1 37.75 5.87139 4.87957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +7series_BRAM_DSP_carry.xml stereovision0.v common 305.97 vpr 477.68 MiB -1 -1 4.47 103400 5 2.93 -1 -1 70128 -1 -1 -1 169 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 489148 169 197 23225 21365 1 9660 1645 42 42 1764 CLB auto 182.7 MiB 257.68 191242 69741 865479 231951 560905 72623 401.9 MiB 11.92 0.12 6.0701 4.03928 -16398 -4.03928 4.03928 0.01 0.0109682 0.00913863 1.16208 0.959963 -1 -1 -1 -1 -1 65287 12 9.88618e+07 6.89317e+07 3.28179e+07 18604.2 7.69 1.47609 1.21957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +7series_BRAM_DSP_carry.xml stereovision1.v common 329.87 vpr 834.59 MiB -1 -1 3.84 114924 3 4.76 -1 -1 71964 -1 -1 -1 115 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 854616 115 145 22865 19302 1 10319 1528 66 66 4356 DSP auto 177.7 MiB 240.81 312166 102042 872431 274471 588095 9865 776.7 MiB 10.52 0.10 5.768 4.76067 -21233.7 -4.76067 4.76067 0.03 0.0112499 0.00937755 1.28065 1.06586 -1 -1 -1 -1 -1 102221 14 2.52497e+08 9.57084e+07 8.29171e+07 19035.1 15.90 1.64146 1.36816 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +7series_BRAM_DSP_carry.xml stereovision2.v common 1075.22 vpr 2.05 GiB -1 -1 5.50 172452 3 2.26 -1 -1 140992 -1 -1 -1 149 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 2146896 149 182 55416 37075 1 33280 4031 106 106 11236 DSP auto 331.5 MiB 770.59 1.74668e+06 450674 3595535 1133232 2334220 128083 1925.1 MiB 87.23 0.75 22.9595 15.3724 -48322.5 -15.3724 15.3724 0.07 0.0319348 0.027826 3.8538 3.21492 -1 -1 -1 -1 -1 436136 16 6.67318e+08 2.79446e+08 2.17352e+08 19344.2 53.10 4.97283 4.15748 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From 0e9d7ef7f6372b2ad3bee9aa36a338bc07ae80ad Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Tue, 7 Oct 2025 12:52:13 -0600 Subject: [PATCH 7/9] Removed comments --- parmys/parmys-plugin/core/multiplier.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/parmys/parmys-plugin/core/multiplier.cc b/parmys/parmys-plugin/core/multiplier.cc index 6291d6f01b4..2876a2ab93a 100644 --- a/parmys/parmys-plugin/core/multiplier.cc +++ b/parmys/parmys-plugin/core/multiplier.cc @@ -1111,13 +1111,11 @@ void split_multiplier(nnode_t *node, int a0, int b0, int a1, int b1, netlist_t * for (int i = 0; i < addsmall->num_output_pins; i++) { connect_nodes(addsmall, i, addbig, i); } - // add_input_pin_to_node(addbig, get_zero_pin(netlist), addsmall->num_output_pins); // connect inputs to port b of addbig for (int i = 0; i < addsmall2->num_output_pins; i++) { connect_nodes(addsmall2, i, addbig, i + addbig->input_port_sizes[0]); } - // add_input_pin_to_node(addbig, get_zero_pin(netlist), addbig->input_port_sizes[0] + addsmall->num_output_pins); // remap the multiplier outputs coming directly from a0b0 for (int i = 0; i < addbig->num_output_pins; i++) { @@ -1392,7 +1390,6 @@ void iterate_multipliers(netlist_t *netlist) /* Can only perform the optimisation if hard multipliers exist! */ if (hard_multipliers == NULL) return; - // std::cin.get(); sizea = hard_multipliers->inputs->size; sizeb = hard_multipliers->inputs->next->size; if (sizea < sizeb) { From 6eb788fc20ae85b264094d1d3cec51bb91a0b16b Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Fri, 24 Oct 2025 14:45:47 -0600 Subject: [PATCH 8/9] updated golden --- .../strong_xilinx_flagship/config/golden_results.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt index c5f006aa489..92484b263bc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -7series_BRAM_DSP_carry.xml stereovision3.v common 2.53 vpr 72.59 MiB -1 -1 0.33 26408 4 0.08 -1 -1 36120 -1 -1 -1 11 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 74336 11 2 303 283 2 114 35 7 7 49 CLB auto 33.2 MiB 1.18 577.007 408 947 108 584 255 72.6 MiB 0.01 0.00 3.1717 3.1717 -180.982 -3.1717 2.89952 0.12 0.000171885 0.000143559 0.00458104 0.00401289 -1 -1 -1 -1 40 889 22 1.34735e+06 1.18567e+06 152291. 3107.98 0.22 0.0179847 0.0160687 6668 73471 -1 385 12 297 988 127228 60728 2.91111 2.8252 -221.503 -2.91111 -2.452 -0.04 215465. 4397.25 0.02 0.02 0.04 -1 -1 0.02 0.00962131 0.00895172 +7series_BRAM_DSP_carry.xml stereovision3.v common 2.53 vpr 72.59 MiB -1 -1 0.33 26408 4 0.08 -1 -1 36120 -1 -1 -1 11 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 74336 11 2 303 283 2 114 35 7 7 49 CLB auto 33.2 MiB 1.18 577.007 408 947 108 584 255 72.6 MiB 0.01 0.00 3.1717 3.1717 -180.982 -3.1717 2.89952 0.12 0.000171885 0.000143559 0.00458104 0.00401289 -1 -1 -1 -1 40 889 22 1.34735e+06 1.18567e+06 152291. 3107.98 15.02 0.0179847 0.0160687 6668 73471 -1 385 12 297 988 127228 60728 2.91111 2.8252 -221.503 -2.91111 -2.452 -0.04 215465. 4397.25 0.02 0.02 0.04 -1 -1 0.02 0.00962131 0.00895172 7series_BRAM_DSP_carry.xml diffeq2.v common 48.98 vpr 129.37 MiB -1 -1 0.19 27844 5 0.09 -1 -1 38944 -1 -1 -1 66 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 132476 66 96 1819 1080 1 1150 336 26 26 676 DSP auto 40.6 MiB 2.77 20198.7 9188 64521 14520 45607 4394 119.7 MiB 0.65 0.01 22.6842 19.668 -1065.49 -19.668 19.668 3.45 0.000811128 0.000723384 0.0536543 0.0478746 -1 -1 -1 -1 74 12093 17 3.53732e+07 1.31407e+07 5.36197e+06 7931.91 33.65 0.395666 0.356239 133518 2720184 -1 10986 14 5828 10018 3165525 816384 19.4143 19.4143 -1210.49 -19.4143 -1.7 -0.034 6.54552e+06 9682.72 1.89 0.38 1.55 -1 -1 1.89 0.0458825 0.0428936 \ No newline at end of file From e20ee6f062380d45760b296512171ceb4621124c Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Thu, 30 Oct 2025 22:02:27 -0600 Subject: [PATCH 9/9] updated tests parsing --- .../vtr_xilinx_qor/config/golden_results.txt | 16 ++++++++-------- .../config/golden_results.txt | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt index 788ced44c7a..b563c7587c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt @@ -1,8 +1,8 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -7series_BRAM_DSP_carry.xml mcml.v common 6028.93 vpr 4.29 GiB -1 -1 112.39 1324532 26 1575.37 -1 -1 397412 -1 -1 -1 36 159 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 4493412 36 356 199703 166091 1 96432 14448 132 132 17424 CLB auto 1373.1 MiB 1554.60 7.30767e+06 1510965 30795198 11005989 11799313 7989896 3575.2 MiB 2353.07 8.99 114.688 75.4926 -385876 -75.4926 75.4926 0.11 0.144559 0.12413 27.5533 22.7998 -1 -1 -1 -1 -1 1044733 17 1.04106e+09 8.39563e+08 3.37280e+08 19357.2 132.18 32.8963 27.1671 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -7series_BRAM_DSP_carry.xml LU32PEEng.v common 4021.40 vpr 3.52 GiB -1 -1 89.23 1523944 97 420.80 -1 -1 364304 -1 -1 -1 114 153 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 3686084 114 102 123962 109723 1 78255 10604 114 114 12996 CLB auto 1078.7 MiB 2226.89 7.50175e+06 1274738 15614502 6135197 9031079 448226 2727.3 MiB 917.29 6.53 143.442 109.472 -246691 -109.472 109.472 0.08 0.141279 0.121064 21.4205 17.832 -1 -1 -1 -1 -1 1465950 19 7.77041e+08 6.23088e+08 2.51453e+08 19348.5 154.91 27.165 22.4874 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -7series_BRAM_DSP_carry.xml LU8PEEng.v common 866.13 vpr 1.03 GiB -1 -1 28.05 472768 98 39.42 -1 -1 117816 -1 -1 -1 114 45 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 1079760 114 102 36706 32285 1 22732 3211 62 62 3844 CLB auto 336.8 MiB 618.57 1.07733e+06 293198 2726296 910892 1594196 221208 816.6 MiB 93.59 0.82 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goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 854616 115 145 22865 19302 1 10319 1528 66 66 4356 DSP auto 177.7 MiB 240.81 312166 102042 872431 274471 588095 9865 776.7 MiB 10.52 0.10 5.768 4.76067 -21233.7 -4.76067 4.76067 0.03 0.0112499 0.00937755 1.28065 1.06586 -1 -1 -1 -1 -1 102221 14 2.52497e+08 9.57084e+07 8.29171e+07 19035.1 15.90 1.64146 1.36816 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -7series_BRAM_DSP_carry.xml stereovision2.v common 1075.22 vpr 2.05 GiB -1 -1 5.50 172452 3 2.26 -1 -1 140992 -1 -1 -1 149 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 2146896 149 182 55416 37075 1 33280 4031 106 106 11236 DSP auto 331.5 MiB 770.59 1.74668e+06 450674 3595535 1133232 2334220 128083 1925.1 MiB 87.23 0.75 22.9595 15.3724 -48322.5 -15.3724 15.3724 0.07 0.0319348 0.027826 3.8538 3.21492 -1 -1 -1 -1 -1 436136 16 6.67318e+08 2.79446e+08 2.17352e+08 19344.2 53.10 4.97283 4.15748 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 \ No newline at end of file +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +7series_BRAM_DSP_carry.xml mcml.v common 6313.11 vpr 4.28 GiB -1 -1 87.19 1031944 26 1703.45 -1 -1 397084 -1 -1 -1 36 159 -1 success v8.0.0-14124-g5725a225d release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-10-09T09:04:20 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 4487004 36 356 198637 165032 1 95923 14364 132 132 17424 CLB auto 1363.3 MiB 1601.63 7.24933e+06 1524256 30905820 11032851 11396471 8476498 3423.6 MiB 2480.46 8.69 108.93 73.9809 -371259 -73.9809 73.9809 0.14 0.162937 0.141987 31.3309 26.6374 -1 -1 -1 -1 1035273 5.22707 458769 2.31631 480955 1548202 178093609 19783675 1.04106e+09 8.35036e+08 3.37280e+08 19357.2 16 7938917 120124248 2733689 60.9084 60.9084 -656666 -60.9084 0 0 78.01 40.16 10.79 4381.8 MiB 131.54 36.9474 31.2048 3423.6 MiB 0.08 161.67 +7series_BRAM_DSP_carry.xml LU32PEEng.v common 4141.71 vpr 3.47 GiB -1 -1 62.78 1217024 93 414.51 -1 -1 380360 -1 -1 -1 114 153 -1 success v8.0.0-14124-g5725a225d release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-10-09T09:04:20 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 3640452 114 102 123003 108818 1 77498 10464 113 113 12769 CLB auto 1067.7 MiB 2291.63 7.43631e+06 1262567 15340198 6033356 8730977 575865 2576.1 MiB 1003.63 6.20 135.884 109.205 -232244 -109.205 109.205 0.10 0.162848 0.141804 25.0696 21.5063 -1 -1 -1 -1 1398688 11.3770 626094 5.09268 439657 2220380 322294781 37162681 7.58182e+08 6.15544e+08 2.46355e+08 19293.2 18 5806063 87504646 2231668 85.8248 85.8248 -451588 -85.8248 0 0 57.91 29.77 8.16 3555.0 MiB 139.50 32.2133 27.3232 2576.1 MiB 0.08 125.61 +7series_BRAM_DSP_carry.xml LU8PEEng.v common 861.93 vpr 1.03 GiB -1 -1 20.03 380748 97 40.89 -1 -1 116508 -1 -1 -1 114 45 -1 success v8.0.0-14124-g5725a225d release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-10-09T09:04:20 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 1079496 114 102 36458 32091 1 22453 3197 62 62 3844 CLB auto 336.4 MiB 626.70 1.15759e+06 286430 2686985 897479 1605424 184082 785.5 MiB 91.37 0.82 127.808 111.347 -51526.1 -111.347 111.347 0.03 0.0403543 0.0350875 5.17473 4.40197 -1 -1 -1 -1 327752 8.99701 158009 4.33745 138790 590818 72646827 7812502 2.21078e+08 1.78788e+08 7.33801e+07 19089.5 19 1711674 25804385 642695 88.5126 88.5126 -79974.1 -88.5126 0 0 16.08 8.34 2.33 1054.0 MiB 27.92 6.71731 5.66531 785.5 MiB 0.08 27.47 +7series_BRAM_DSP_carry.xml bgm.v common 753.57 vpr 1.09 GiB -1 -1 14.84 508304 14 40.42 -1 -1 125028 -1 -1 -1 257 0 -1 success v8.0.0-14124-g5725a225d release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-10-09T09:04:20 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 1142528 257 32 37166 34104 1 23802 3586 66 66 4356 CLB auto 369.1 MiB 497.29 1.40047e+06 292740 2856930 988242 1818956 49732 879.1 MiB 98.21 0.99 36.7393 22.4885 -27648.5 -22.4885 22.4885 0.03 0.0421788 0.0370497 5.12815 4.34656 -1 -1 -1 -1 394981 10.6283 186576 5.02048 171693 731956 103907577 11160888 2.52497e+08 1.8145e+08 8.29171e+07 19035.1 20 1861896 29128908 739360 20.5236 20.5236 -28025.6 -20.5236 0 0 18.27 9.55 2.79 1115.8 MiB 38.76 6.88362 5.77265 879.1 MiB 0.08 32.15 +7series_BRAM_DSP_carry.xml stereovision0.v common 312.33 vpr 481.78 MiB -1 -1 3.37 103432 5 2.85 -1 -1 69068 -1 -1 -1 169 0 -1 success v8.0.0-14124-g5725a225d release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-10-09T09:04:20 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 493340 169 197 23132 21336 1 9472 1670 42 42 1764 CLB auto 186.5 MiB 264.83 192189 68164 853414 231424 553421 68569 397.7 MiB 11.46 0.12 5.42523 4.02318 -16155.7 -4.02318 4.02318 0.01 0.0123845 0.0104627 1.26103 1.04979 -1 -1 -1 -1 65033 2.81358 33016 1.42840 50854 111172 13334467 1642868 9.88618e+07 7.02791e+07 3.28179e+07 18604.2 13 823689 11449301 270023 3.61197 3.61197 -19327.2 -3.61197 0 0 6.88 3.67 1.11 481.8 MiB 8.06 1.62306 1.34782 397.7 MiB 0.08 10.78 +7series_BRAM_DSP_carry.xml stereovision1.v common 334.87 vpr 838.88 MiB -1 -1 2.89 117460 3 4.60 -1 -1 71612 -1 -1 -1 115 0 -1 success v8.0.0-14124-g5725a225d release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-10-09T09:04:20 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 859008 115 145 22828 19265 1 10325 1531 66 66 4356 DSP auto 179.2 MiB 244.04 311225 103708 909991 287175 612059 10757 742.8 MiB 11.66 0.12 5.73398 5.10375 -20985.5 -5.10375 5.10375 0.03 0.0133465 0.0113694 1.53107 1.2955 -1 -1 -1 -1 100160 4.38932 39961 1.75122 54266 112180 15375570 1836846 2.52497e+08 9.58701e+07 8.29171e+07 19035.1 10 1520183 28962658 248173 4.56731 4.56731 -24939.2 -4.56731 0 0 18.29 7.24 1.23 838.9 MiB 15.85 1.83682 1.55126 742.8 MiB 0.08 32.59 +7series_BRAM_DSP_carry.xml stereovision2.v common 1112.29 vpr 2.05 GiB -1 -1 4.46 179764 3 2.16 -1 -1 140184 -1 -1 -1 149 0 -1 success v8.0.0-14124-g5725a225d release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-10-09T09:04:20 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 2151592 149 182 55138 36887 1 33057 4001 106 106 11236 DSP auto 330.5 MiB 807.58 1.74045e+06 426423 3528140 1119893 2255709 152538 1831.9 MiB 86.41 0.74 24.8584 14.831 -47167.6 -14.831 14.831 0.09 0.0338907 0.0296075 4.25753 3.60632 -1 -1 -1 -1 407551 7.39362 135018 2.44944 129230 211734 56370804 6974901 6.67318e+08 2.77829e+08 2.17352e+08 19344.2 16 3832290 76670110 592393 14.5948 14.5948 -60596.1 -14.5948 0 0 50.05 19.78 3.06 2101.2 MiB 50.73 5.45946 4.61585 1831.9 MiB 0.08 99.78 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt index 92484b263bc..76842a94d9c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -7series_BRAM_DSP_carry.xml stereovision3.v common 2.53 vpr 72.59 MiB -1 -1 0.33 26408 4 0.08 -1 -1 36120 -1 -1 -1 11 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 74336 11 2 303 283 2 114 35 7 7 49 CLB auto 33.2 MiB 1.18 577.007 408 947 108 584 255 72.6 MiB 0.01 0.00 3.1717 3.1717 -180.982 -3.1717 2.89952 0.12 0.000171885 0.000143559 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