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@HazemAlindari
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@HazemAlindari HazemAlindari commented Oct 27, 2024

…nd delete SystemVerilog temp files

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  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

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  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@github-actions github-actions bot added the lang-python Python code label Oct 27, 2024
@vaughnbetz
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Thanks. Will merge when CI finishes.

@vaughnbetz
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if refactoring is the same functionality but easier to read, and the new code removes .sv files as well. Will merge after CI finishes.

@vaughnbetz vaughnbetz merged commit ca53359 into verilog-to-routing:master Jan 27, 2025
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2 participants