From 4a5c1c9bf9e7bf1b7cdd270a3f79a4ab21f6e216 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sun, 22 Sep 2024 17:16:02 -0400 Subject: [PATCH 01/16] add ChanPlaceCostFacContainer --- vpr/src/place/net_cost_handler.cpp | 66 ++++++++++++++++-------------- vpr/src/place/net_cost_handler.h | 17 ++++++-- 2 files changed, 50 insertions(+), 33 deletions(-) diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index 5abd9cb4f86..fd40829ed0a 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -179,16 +179,18 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_c /* Access arrays below as chan?_place_cost_fac[subhigh][sublow]. Since subhigh must be greater than or * equal to sublow, we will only access the lower half of a matrix, but we allocate the whole matrix anyway * for simplicity, so we can use the vtr utility matrix functions. */ - chanx_place_cost_fac_.resize({grid_height, grid_height + 1}); - chany_place_cost_fac_.resize({grid_width, grid_width + 1}); + chanx_place_cost_fac_.resize({grid_height + 1, grid_height + 1}); + chany_place_cost_fac_.resize({grid_width + 1, grid_width + 1}); // First compute the number of tracks between channel high and channel low, inclusive. - chanx_place_cost_fac_[0][0] = device_ctx.chan_width.x_list[0]; - - for (size_t high = 1; high < grid_height; high++) { - chanx_place_cost_fac_[high][high] = device_ctx.chan_width.x_list[high]; - for (size_t low = 0; low < high; low++) { - chanx_place_cost_fac_[high][low] = chanx_place_cost_fac_[high - 1][low] + device_ctx.chan_width.x_list[high]; + chanx_place_cost_fac_(-1, -1) = 0; + chanx_place_cost_fac_( 0, -1) = device_ctx.chan_width.x_list[0];; + chanx_place_cost_fac_( 0, 0) = device_ctx.chan_width.x_list[0]; + + for (int high = 1; high < (int)grid_height; high++) { + chanx_place_cost_fac_(high, high) = (float)device_ctx.chan_width.x_list[high]; + for (int low = 0; low < high; low++) { + chanx_place_cost_fac_(high, low) = chanx_place_cost_fac_(high - 1, low) + (float)device_ctx.chan_width.x_list[high]; } } @@ -199,50 +201,54 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_c * place_cost_exp power -- numbers other than one mean this is no * * longer a simple "average number of tracks"; it is some power of * * that, allowing greater penalization of narrow channels. */ - for (size_t high = 0; high < grid_height; high++) - for (size_t low = 0; low <= high; low++) { + for (int high = 0; high < (int)grid_height; high++) { + for (int low = 0; low <= high; low++) { /* Since we will divide the wiring cost by the average channel * * capacity between high and low, having only 0 width channels * * will result in infinite wiring capacity normalization * * factor, and extremely bad placer behaviour. Hence we change * * this to a small (1 track) channel capacity instead. */ - if (chanx_place_cost_fac_[high][low] == 0.0f) { + if (chanx_place_cost_fac_(high, low) == 0.0f) { VTR_LOG_WARN("CHANX place cost fac is 0 at %d %d\n", high, low); - chanx_place_cost_fac_[high][low] = 1.0f; + chanx_place_cost_fac_(high, low) = 1.0f; } - chanx_place_cost_fac_[high][low] = (high - low + 1.) / chanx_place_cost_fac_[high][low]; - chanx_place_cost_fac_[high][low] = pow((double)chanx_place_cost_fac_[high][low], (double)place_cost_exp); + chanx_place_cost_fac_(high, low) = (high - low + 1.) / chanx_place_cost_fac_(high, low); + chanx_place_cost_fac_(high, low) = pow((double)chanx_place_cost_fac_(high, low), (double)place_cost_exp); } + } /* Now do the same thing for the y-directed channels. First get the * number of tracks between channel high and channel low, inclusive. */ - chany_place_cost_fac_[0][0] = device_ctx.chan_width.y_list[0]; - - for (size_t high = 1; high < grid_width; high++) { - chany_place_cost_fac_[high][high] = device_ctx.chan_width.y_list[high]; - for (size_t low = 0; low < high; low++) { - chany_place_cost_fac_[high][low] = chany_place_cost_fac_[high - 1][low] + device_ctx.chan_width.y_list[high]; + chany_place_cost_fac_(-1, -1) = 0; + chany_place_cost_fac_( 0, -1) = device_ctx.chan_width.y_list[0]; + chany_place_cost_fac_( 0, 0) = device_ctx.chan_width.y_list[0]; + + for (int high = 1; high < (int)grid_width; high++) { + chany_place_cost_fac_(high, high) = device_ctx.chan_width.y_list[high]; + for (int low = 0; low < high; low++) { + chany_place_cost_fac_(high, low) = chany_place_cost_fac_(high - 1, low) + device_ctx.chan_width.y_list[high]; } } /* Now compute the inverse of the average number of tracks per channel * between high and low. Take to specified power. */ - for (size_t high = 0; high < grid_width; high++) - for (size_t low = 0; low <= high; low++) { + for (int high = 0; high < (int)grid_width; high++) { + for (int low = 0; low <= high; low++) { /* Since we will divide the wiring cost by the average channel * * capacity between high and low, having only 0 width channels * * will result in infinite wiring capacity normalization * * factor, and extremely bad placer behaviour. Hence we change * * this to a small (1 track) channel capacity instead. */ - if (chany_place_cost_fac_[high][low] == 0.0f) { + if (chany_place_cost_fac_(high, low) == 0.0f) { VTR_LOG_WARN("CHANY place cost fac is 0 at %d %d\n", high, low); - chany_place_cost_fac_[high][low] = 1.0f; + chany_place_cost_fac_(high, low) = 1.0f; } - chany_place_cost_fac_[high][low] = (high - low + 1.) / chany_place_cost_fac_[high][low]; - chany_place_cost_fac_[high][low] = pow((double)chany_place_cost_fac_[high][low], (double)place_cost_exp); + chany_place_cost_fac_(high, low) = (high - low + 1.) / chany_place_cost_fac_(high, low); + chany_place_cost_fac_(high, low) = pow((double)chany_place_cost_fac_(high, low), (double)place_cost_exp); } + } } double NetCostHandler::comp_bb_cost(e_cost_methods method) { @@ -1476,8 +1482,8 @@ double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { * channel capacity. Do this for x, then y direction and add. */ double ncost; - ncost = (bb.xmax - bb.xmin + 1) * crossing * chanx_place_cost_fac_[bb.ymax][bb.ymin - 1]; - ncost += (bb.ymax - bb.ymin + 1) * crossing * chany_place_cost_fac_[bb.xmax][bb.xmin - 1]; + ncost = (bb.xmax - bb.xmin + 1) * crossing * chanx_place_cost_fac_(bb.ymax, bb.ymin - 1); + ncost += (bb.ymax - bb.ymin + 1) * crossing * chany_place_cost_fac_(bb.xmax, bb.xmin - 1); return ncost; } @@ -1513,10 +1519,10 @@ double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use * channel capacity. Do this for x, then y direction and add. */ ncost += (bb[layer_num].xmax - bb[layer_num].xmin + 1) * crossing - * chanx_place_cost_fac_[bb[layer_num].ymax][bb[layer_num].ymin - 1]; + * chanx_place_cost_fac_(bb[layer_num].ymax, bb[layer_num].ymin - 1); ncost += (bb[layer_num].ymax - bb[layer_num].ymin + 1) * crossing - * chany_place_cost_fac_[bb[layer_num].xmax][bb[layer_num].xmin - 1]; + * chany_place_cost_fac_(bb[layer_num].xmax, bb[layer_num].xmin - 1); } return ncost; diff --git a/vpr/src/place/net_cost_handler.h b/vpr/src/place/net_cost_handler.h index 3b35bf68ea3..41d3a28fa5f 100644 --- a/vpr/src/place/net_cost_handler.h +++ b/vpr/src/place/net_cost_handler.h @@ -190,6 +190,18 @@ class NetCostHandler { vtr::vector proposed_net_cost_; vtr::vector bb_update_status_; + class ChanPlaceCostFacContainer : public vtr::NdMatrix { + public: + float& operator()(int i, int j) { + size_t ipp = i + 1; + size_t jpp = j + 1; + return this->operator[](ipp).operator[](jpp); + } + + private: + using vtr::NdMatrix::operator[]; + }; + /** * @brief Matrices below are used to precompute the inverse of the average * number of tracks per channel between [subhigh] and [sublow]. Access @@ -199,8 +211,8 @@ class NetCostHandler { * number of tracks in that direction; for other cost functions they * will never be used. */ - vtr::NdMatrix chanx_place_cost_fac_; // [0...device_ctx.grid.width()-2] - vtr::NdMatrix chany_place_cost_fac_; // [0...device_ctx.grid.height()-2] + ChanPlaceCostFacContainer chanx_place_cost_fac_; // [0...device_ctx.grid.width()-2] + ChanPlaceCostFacContainer chany_place_cost_fac_; // [0...device_ctx.grid.height()-2] private: @@ -383,7 +395,6 @@ class NetCostHandler { * @param old_edge_coord The current known bounding box of the net * @param new_num_block_on_edge The new bb calculated by this function * @param new_edge_coord The new bb edge calculated by this function - * */ inline void update_bb_edge_(ClusterNetId net_id, std::vector& bb_edge_new, From e793e210e88d3e23639cdd9bea3712c1b690ca59 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sun, 22 Sep 2024 17:30:11 -0400 Subject: [PATCH 02/16] remove std::max calls --- vpr/src/place/net_cost_handler.cpp | 61 +++++++++++++++--------------- 1 file changed, 30 insertions(+), 31 deletions(-) diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index fd40829ed0a..f4c30e8d3fb 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -36,7 +36,6 @@ #include -using std::max; using std::min; @@ -572,12 +571,12 @@ void NetCostHandler::get_non_updatable_cube_bb_(ClusterNetId net_id, bool use_ts * clip to 1 in both directions as well (since minimum channel index * * is 0). See route_common.cpp for a channel diagram. */ - bb_coord_new.xmin = max(min(xmin, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - bb_coord_new.ymin = max(min(ymin, device_ctx.grid.height() - 2), 1); //-2 for no perim channels - bb_coord_new.layer_min = max(min(layer_min, device_ctx.grid.get_num_layers() - 1), 0); - bb_coord_new.xmax = max(min(xmax, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - bb_coord_new.ymax = max(min(ymax, device_ctx.grid.height() - 2), 1); //-2 for no perim channels - bb_coord_new.layer_max = max(min(layer_max, device_ctx.grid.get_num_layers() - 1), 0); + bb_coord_new.xmin = min(xmin, device_ctx.grid.width() - 2); //-2 for no perim channels + bb_coord_new.ymin = min(ymin, device_ctx.grid.height() - 2); //-2 for no perim channels + bb_coord_new.layer_min = layer_min; + bb_coord_new.xmax = min(xmax, device_ctx.grid.width() - 2); //-2 for no perim channels + bb_coord_new.ymax = min(ymax, device_ctx.grid.height() - 2); //-2 for no perim channels + bb_coord_new.layer_max = layer_max; } void NetCostHandler::get_non_updatable_per_layer_bb_(ClusterNetId net_id, bool use_ts) { @@ -637,10 +636,10 @@ void NetCostHandler::get_non_updatable_per_layer_bb_(ClusterNetId net_id, bool u * is 0). See route_common.cpp for a channel diagram. */ for (int layer_num = 0; layer_num < num_layers; layer_num++) { bb_coord_new[layer_num].layer_num = layer_num; - bb_coord_new[layer_num].xmin = max(min(bb_coord_new[layer_num].xmin, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - bb_coord_new[layer_num].ymin = max(min(bb_coord_new[layer_num].ymin, device_ctx.grid.height() - 2), 1); //-2 for no perim channels - bb_coord_new[layer_num].xmax = max(min(bb_coord_new[layer_num].xmax, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - bb_coord_new[layer_num].ymax = max(min(bb_coord_new[layer_num].ymax, device_ctx.grid.height() - 2), 1); //-2 for no perim channels + bb_coord_new[layer_num].xmin = min(bb_coord_new[layer_num].xmin, device_ctx.grid.width() - 2); //-2 for no perim channels + bb_coord_new[layer_num].ymin = min(bb_coord_new[layer_num].ymin, device_ctx.grid.height() - 2); //-2 for no perim channels + bb_coord_new[layer_num].xmax = min(bb_coord_new[layer_num].xmax, device_ctx.grid.width() - 2); //-2 for no perim channels + bb_coord_new[layer_num].ymax = min(bb_coord_new[layer_num].ymax, device_ctx.grid.height() - 2); //-2 for no perim channels } } @@ -663,12 +662,12 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, // Number of sinks of the given net on each layer vtr::NdMatrixProxy num_sink_pin_layer_new = ts_layer_sink_pin_count_[size_t(net_id)]; - pin_new_loc.x = max(min(pin_new_loc.x, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - pin_new_loc.y = max(min(pin_new_loc.y, device_ctx.grid.height() - 2), 1); //-2 for no perim channels - pin_new_loc.layer_num = max(min(pin_new_loc.layer_num, device_ctx.grid.get_num_layers() - 1), 0); - pin_old_loc.x = max(min(pin_old_loc.x, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - pin_old_loc.y = max(min(pin_old_loc.y, device_ctx.grid.height() - 2), 1); //-2 for no perim channels - pin_old_loc.layer_num = max(min(pin_old_loc.layer_num, device_ctx.grid.get_num_layers() - 1), 0); + pin_new_loc.x = min(pin_new_loc.x, device_ctx.grid.width() - 2); //-2 for no perim channels + pin_new_loc.y = min(pin_new_loc.y, device_ctx.grid.height() - 2); //-2 for no perim channels + pin_new_loc.layer_num = pin_new_loc.layer_num; + pin_old_loc.x = min(pin_old_loc.x, device_ctx.grid.width() - 2); //-2 for no perim channels + pin_old_loc.y = min(pin_old_loc.y, device_ctx.grid.height() - 2); //-2 for no perim channels + pin_old_loc.layer_num = pin_old_loc.layer_num; /* Check if the net had been updated before. */ if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { @@ -927,10 +926,10 @@ void NetCostHandler::update_layer_bb_(ClusterNetId net_id, auto& device_ctx = g_vpr_ctx.device(); auto& place_move_ctx = placer_state_.move(); - pin_new_loc.x = max(min(pin_new_loc.x, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - pin_new_loc.y = max(min(pin_new_loc.y, device_ctx.grid.height() - 2), 1); //-2 for no perim channels - pin_old_loc.x = max(min(pin_old_loc.x, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - pin_old_loc.y = max(min(pin_old_loc.y, device_ctx.grid.height() - 2), 1); //-2 for no perim channels + pin_new_loc.x = min(pin_new_loc.x, device_ctx.grid.width() - 2); //-2 for no perim channels + pin_new_loc.y = min(pin_new_loc.y, device_ctx.grid.height() - 2); //-2 for no perim channels + pin_old_loc.x = min(pin_old_loc.x, device_ctx.grid.width() - 2); //-2 for no perim channels + pin_old_loc.y = min(pin_old_loc.y, device_ctx.grid.height() - 2); //-2 for no perim channels std::vector& bb_edge_new = layer_ts_bb_edge_new_[net_id]; std::vector& bb_coord_new = layer_ts_bb_coord_new_[net_id]; @@ -1285,9 +1284,9 @@ void NetCostHandler::get_bb_from_scratch_(ClusterNetId net_id, int y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; int pin_layer = block_loc.layer; - x = max(min(x, grid.width() - 2), 1); - y = max(min(y, grid.height() - 2), 1); - pin_layer = max(min(pin_layer, grid.get_num_layers() - 1), 0); + x = min(x, grid.width() - 2); + y = min(y, grid.height() - 2); + pin_layer = min(pin_layer, grid.get_num_layers() - 1); int xmin = x; int ymin = y; @@ -1322,9 +1321,9 @@ void NetCostHandler::get_bb_from_scratch_(ClusterNetId net_id, * the which channels are included within the bounding box, and it * * simplifies the code a lot. */ - x = max(min(x, grid.width() - 2), 1); //-2 for no perim channels - y = max(min(y, grid.height() - 2), 1); //-2 for no perim channels - pin_layer = max(min(pin_layer, grid.get_num_layers() - 1), 0); + x = min(x, grid.width() - 2); //-2 for no perim channels + y = min(y, grid.height() - 2); //-2 for no perim channels + pin_layer = min(pin_layer, grid.get_num_layers() - 1); if (x == xmin) { xmin_edge++; @@ -1406,8 +1405,8 @@ void NetCostHandler::get_layer_bb_from_scratch_(ClusterNetId net_id, int x_src = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum_src]; int y_src = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum_src]; - x_src = max(min(x_src, grid.width() - 2), 1); - y_src = max(min(y_src, grid.height() - 2), 1); + x_src = min(x_src, grid.width() - 2); + y_src = min(y_src, grid.height() - 2); // TODO: Currently we are assuming that crossing can only happen from OPIN. Because of that, // when per-layer bounding box is used, we want the bounding box on each layer to also include @@ -1435,8 +1434,8 @@ void NetCostHandler::get_layer_bb_from_scratch_(ClusterNetId net_id, * the which channels are included within the bounding box, and it * * simplifies the code a lot. */ - x = max(min(x, grid.width() - 2), 1); //-2 for no perim channels - y = max(min(y, grid.height() - 2), 1); //-2 for no perim channels + x = min(x, grid.width() - 2); //-2 for no perim channels + y = min(y, grid.height() - 2); //-2 for no perim channels if (x == coords[layer].xmin) { num_on_edges[layer].xmin++; From 8ef4144b64ebb41dff04928e22c6d00681e549a6 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sun, 22 Sep 2024 18:37:35 -0400 Subject: [PATCH 03/16] remove std::min calls --- vpr/src/place/net_cost_handler.cpp | 62 ++++++++++-------------------- 1 file changed, 21 insertions(+), 41 deletions(-) diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index f4c30e8d3fb..7761abadb31 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -36,9 +36,6 @@ #include -using std::min; - - static constexpr int MAX_FANOUT_CROSSING_COUNT = 50; /** @@ -570,12 +567,11 @@ void NetCostHandler::get_non_updatable_cube_bb_(ClusterNetId net_id, bool use_ts * channel immediately to the left of the bounding box, I want to * * clip to 1 in both directions as well (since minimum channel index * * is 0). See route_common.cpp for a channel diagram. */ - - bb_coord_new.xmin = min(xmin, device_ctx.grid.width() - 2); //-2 for no perim channels - bb_coord_new.ymin = min(ymin, device_ctx.grid.height() - 2); //-2 for no perim channels + bb_coord_new.xmin = xmin; + bb_coord_new.ymin = ymin; bb_coord_new.layer_min = layer_min; - bb_coord_new.xmax = min(xmax, device_ctx.grid.width() - 2); //-2 for no perim channels - bb_coord_new.ymax = min(ymax, device_ctx.grid.height() - 2); //-2 for no perim channels + bb_coord_new.xmax = xmax; + bb_coord_new.ymax = ymax; bb_coord_new.layer_max = layer_max; } @@ -634,13 +630,13 @@ void NetCostHandler::get_non_updatable_per_layer_bb_(ClusterNetId net_id, bool u * channel immediately to the left of the bounding box, I want to * * clip to 1 in both directions as well (since minimum channel index * * is 0). See route_common.cpp for a channel diagram. */ - for (int layer_num = 0; layer_num < num_layers; layer_num++) { - bb_coord_new[layer_num].layer_num = layer_num; - bb_coord_new[layer_num].xmin = min(bb_coord_new[layer_num].xmin, device_ctx.grid.width() - 2); //-2 for no perim channels - bb_coord_new[layer_num].ymin = min(bb_coord_new[layer_num].ymin, device_ctx.grid.height() - 2); //-2 for no perim channels - bb_coord_new[layer_num].xmax = min(bb_coord_new[layer_num].xmax, device_ctx.grid.width() - 2); //-2 for no perim channels - bb_coord_new[layer_num].ymax = min(bb_coord_new[layer_num].ymax, device_ctx.grid.height() - 2); //-2 for no perim channels - } +// for (int layer_num = 0; layer_num < num_layers; layer_num++) { +// bb_coord_new[layer_num].layer_num = layer_num; +// bb_coord_new[layer_num].xmin = bb_coord_new[layer_num].xmin; +// bb_coord_new[layer_num].ymin = bb_coord_new[layer_num].ymin; +// bb_coord_new[layer_num].xmax = bb_coord_new[layer_num].xmax; +// bb_coord_new[layer_num].ymax = bb_coord_new[layer_num].ymax; +// } } void NetCostHandler::update_bb_(ClusterNetId net_id, @@ -662,12 +658,12 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, // Number of sinks of the given net on each layer vtr::NdMatrixProxy num_sink_pin_layer_new = ts_layer_sink_pin_count_[size_t(net_id)]; - pin_new_loc.x = min(pin_new_loc.x, device_ctx.grid.width() - 2); //-2 for no perim channels - pin_new_loc.y = min(pin_new_loc.y, device_ctx.grid.height() - 2); //-2 for no perim channels - pin_new_loc.layer_num = pin_new_loc.layer_num; - pin_old_loc.x = min(pin_old_loc.x, device_ctx.grid.width() - 2); //-2 for no perim channels - pin_old_loc.y = min(pin_old_loc.y, device_ctx.grid.height() - 2); //-2 for no perim channels - pin_old_loc.layer_num = pin_old_loc.layer_num; +// pin_new_loc.x = pin_new_loc.x; +// pin_new_loc.y = pin_new_loc.y; +// pin_new_loc.layer_num = pin_new_loc.layer_num; +// pin_old_loc.x = pin_old_loc.x; +// pin_old_loc.y = pin_old_loc.y; +// pin_old_loc.layer_num = pin_old_loc.layer_num; /* Check if the net had been updated before. */ if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { @@ -923,13 +919,12 @@ void NetCostHandler::update_layer_bb_(ClusterNetId net_id, t_physical_tile_loc pin_old_loc, t_physical_tile_loc pin_new_loc, bool is_output_pin) { - auto& device_ctx = g_vpr_ctx.device(); auto& place_move_ctx = placer_state_.move(); - pin_new_loc.x = min(pin_new_loc.x, device_ctx.grid.width() - 2); //-2 for no perim channels - pin_new_loc.y = min(pin_new_loc.y, device_ctx.grid.height() - 2); //-2 for no perim channels - pin_old_loc.x = min(pin_old_loc.x, device_ctx.grid.width() - 2); //-2 for no perim channels - pin_old_loc.y = min(pin_old_loc.y, device_ctx.grid.height() - 2); //-2 for no perim channels + pin_new_loc.x = pin_new_loc.x; + pin_new_loc.y = pin_new_loc.y; + pin_old_loc.x = pin_old_loc.x; + pin_old_loc.y = pin_old_loc.y; std::vector& bb_edge_new = layer_ts_bb_edge_new_[net_id]; std::vector& bb_coord_new = layer_ts_bb_coord_new_[net_id]; @@ -1284,10 +1279,6 @@ void NetCostHandler::get_bb_from_scratch_(ClusterNetId net_id, int y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; int pin_layer = block_loc.layer; - x = min(x, grid.width() - 2); - y = min(y, grid.height() - 2); - pin_layer = min(pin_layer, grid.get_num_layers() - 1); - int xmin = x; int ymin = y; int layer_min = pin_layer; @@ -1321,10 +1312,6 @@ void NetCostHandler::get_bb_from_scratch_(ClusterNetId net_id, * the which channels are included within the bounding box, and it * * simplifies the code a lot. */ - x = min(x, grid.width() - 2); //-2 for no perim channels - y = min(y, grid.height() - 2); //-2 for no perim channels - pin_layer = min(pin_layer, grid.get_num_layers() - 1); - if (x == xmin) { xmin_edge++; } @@ -1391,7 +1378,6 @@ void NetCostHandler::get_layer_bb_from_scratch_(ClusterNetId net_id, vtr::NdMatrixProxy layer_pin_sink_count) { auto& device_ctx = g_vpr_ctx.device(); auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& grid = device_ctx.grid; auto& block_locs = placer_state_.block_locs(); const int num_layers = device_ctx.grid.get_num_layers(); @@ -1405,9 +1391,6 @@ void NetCostHandler::get_layer_bb_from_scratch_(ClusterNetId net_id, int x_src = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum_src]; int y_src = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum_src]; - x_src = min(x_src, grid.width() - 2); - y_src = min(y_src, grid.height() - 2); - // TODO: Currently we are assuming that crossing can only happen from OPIN. Because of that, // when per-layer bounding box is used, we want the bounding box on each layer to also include // the location of source since the connection on each layer starts from that location. @@ -1434,9 +1417,6 @@ void NetCostHandler::get_layer_bb_from_scratch_(ClusterNetId net_id, * the which channels are included within the bounding box, and it * * simplifies the code a lot. */ - x = min(x, grid.width() - 2); //-2 for no perim channels - y = min(y, grid.height() - 2); //-2 for no perim channels - if (x == coords[layer].xmin) { num_on_edges[layer].xmin++; } From 6d870c48449e6b05d25a03070bf0ebdf0ab0ac7b Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sun, 22 Sep 2024 18:55:02 -0400 Subject: [PATCH 04/16] remove dead code --- vpr/src/place/net_cost_handler.cpp | 77 +++++++----------------------- 1 file changed, 18 insertions(+), 59 deletions(-) diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index 7761abadb31..50a7076d004 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -520,12 +520,12 @@ void NetCostHandler::get_non_updatable_cube_bb_(ClusterNetId net_id, bool use_ts int y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; int layer = block_loc.layer; - int xmin = x; - int ymin = y; - int layer_min = layer; - int xmax = x; - int ymax = y; - int layer_max = layer; + bb_coord_new.xmin = x; + bb_coord_new.ymin = y; + bb_coord_new.layer_min = layer; + bb_coord_new.xmax = x; + bb_coord_new.ymax = y; + bb_coord_new.layer_max = layer; for (int layer_num = 0; layer_num < device_ctx.grid.get_num_layers(); layer_num++) { num_sink_pin_layer[layer_num] = 0; @@ -539,40 +539,26 @@ void NetCostHandler::get_non_updatable_cube_bb_(ClusterNetId net_id, bool use_ts y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; layer = block_loc.layer; - if (x < xmin) { - xmin = x; - } else if (x > xmax) { - xmax = x; + if (x < bb_coord_new.xmin) { + bb_coord_new.xmin = x; + } else if (x > bb_coord_new.xmax) { + bb_coord_new.xmax = x; } - if (y < ymin) { - ymin = y; - } else if (y > ymax) { - ymax = y; + if (y < bb_coord_new.ymin) { + bb_coord_new.ymin = y; + } else if (y > bb_coord_new.ymax) { + bb_coord_new.ymax = y; } - if (layer < layer_min) { - layer_min = layer; - } else if (layer > layer_max) { - layer_max = layer; + if (layer < bb_coord_new.layer_min) { + bb_coord_new.layer_min = layer; + } else if (layer > bb_coord_new.layer_max) { + bb_coord_new.layer_max = layer; } num_sink_pin_layer[layer]++; } - - /* Now I've found the coordinates of the bounding box. There are no * - * channels beyond device_ctx.grid.width()-2 and * - * device_ctx.grid.height() - 2, so I want to clip to that. As well,* - * since I'll always include the channel immediately below and the * - * channel immediately to the left of the bounding box, I want to * - * clip to 1 in both directions as well (since minimum channel index * - * is 0). See route_common.cpp for a channel diagram. */ - bb_coord_new.xmin = xmin; - bb_coord_new.ymin = ymin; - bb_coord_new.layer_min = layer_min; - bb_coord_new.xmax = xmax; - bb_coord_new.ymax = ymax; - bb_coord_new.layer_max = layer_max; } void NetCostHandler::get_non_updatable_per_layer_bb_(ClusterNetId net_id, bool use_ts) { @@ -622,21 +608,6 @@ void NetCostHandler::get_non_updatable_per_layer_bb_(ClusterNetId net_id, bool u bb_coord_new[layer_num].ymax = y; } } - - /* Now I've found the coordinates of the bounding box. There are no * - * channels beyond device_ctx.grid.width()-2 and * - * device_ctx.grid.height() - 2, so I want to clip to that. As well,* - * since I'll always include the channel immediately below and the * - * channel immediately to the left of the bounding box, I want to * - * clip to 1 in both directions as well (since minimum channel index * - * is 0). See route_common.cpp for a channel diagram. */ -// for (int layer_num = 0; layer_num < num_layers; layer_num++) { -// bb_coord_new[layer_num].layer_num = layer_num; -// bb_coord_new[layer_num].xmin = bb_coord_new[layer_num].xmin; -// bb_coord_new[layer_num].ymin = bb_coord_new[layer_num].ymin; -// bb_coord_new[layer_num].xmax = bb_coord_new[layer_num].xmax; -// bb_coord_new[layer_num].ymax = bb_coord_new[layer_num].ymax; -// } } void NetCostHandler::update_bb_(ClusterNetId net_id, @@ -658,13 +629,6 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, // Number of sinks of the given net on each layer vtr::NdMatrixProxy num_sink_pin_layer_new = ts_layer_sink_pin_count_[size_t(net_id)]; -// pin_new_loc.x = pin_new_loc.x; -// pin_new_loc.y = pin_new_loc.y; -// pin_new_loc.layer_num = pin_new_loc.layer_num; -// pin_old_loc.x = pin_old_loc.x; -// pin_old_loc.y = pin_old_loc.y; -// pin_old_loc.layer_num = pin_old_loc.layer_num; - /* Check if the net had been updated before. */ if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { /* The net had been updated from scratch, DO NOT update again! */ @@ -921,11 +885,6 @@ void NetCostHandler::update_layer_bb_(ClusterNetId net_id, bool is_output_pin) { auto& place_move_ctx = placer_state_.move(); - pin_new_loc.x = pin_new_loc.x; - pin_new_loc.y = pin_new_loc.y; - pin_old_loc.x = pin_old_loc.x; - pin_old_loc.y = pin_old_loc.y; - std::vector& bb_edge_new = layer_ts_bb_edge_new_[net_id]; std::vector& bb_coord_new = layer_ts_bb_coord_new_[net_id]; vtr::NdMatrixProxy bb_pin_sink_count_new = ts_layer_sink_pin_count_[size_t(net_id)]; From 1106c75afa1f99727b105c14dfddb00ebcaf9dd6 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sun, 22 Sep 2024 18:58:16 -0400 Subject: [PATCH 05/16] move part of chanx_place_cost_fac_ initialization to the loop by changing index range --- vpr/src/place/net_cost_handler.cpp | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index 50a7076d004..b99c42e500b 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -180,12 +180,10 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_c // First compute the number of tracks between channel high and channel low, inclusive. chanx_place_cost_fac_(-1, -1) = 0; - chanx_place_cost_fac_( 0, -1) = device_ctx.chan_width.x_list[0];; - chanx_place_cost_fac_( 0, 0) = device_ctx.chan_width.x_list[0]; - for (int high = 1; high < (int)grid_height; high++) { + for (int high = 0; high < (int)grid_height; high++) { chanx_place_cost_fac_(high, high) = (float)device_ctx.chan_width.x_list[high]; - for (int low = 0; low < high; low++) { + for (int low = -1; low < high; low++) { chanx_place_cost_fac_(high, low) = chanx_place_cost_fac_(high - 1, low) + (float)device_ctx.chan_width.x_list[high]; } } @@ -217,12 +215,10 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_c /* Now do the same thing for the y-directed channels. First get the * number of tracks between channel high and channel low, inclusive. */ chany_place_cost_fac_(-1, -1) = 0; - chany_place_cost_fac_( 0, -1) = device_ctx.chan_width.y_list[0]; - chany_place_cost_fac_( 0, 0) = device_ctx.chan_width.y_list[0]; - for (int high = 1; high < (int)grid_width; high++) { + for (int high = 0; high < (int)grid_width; high++) { chany_place_cost_fac_(high, high) = device_ctx.chan_width.y_list[high]; - for (int low = 0; low < high; low++) { + for (int low = -1; low < high; low++) { chany_place_cost_fac_(high, low) = chany_place_cost_fac_(high - 1, low) + device_ctx.chan_width.y_list[high]; } } From c9af1fb653bdd2d7ac25bcc94fe2947475a99c65 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sun, 22 Sep 2024 19:00:49 -0400 Subject: [PATCH 06/16] compute inverse average channel for all valid indices --- vpr/src/place/net_cost_handler.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index b99c42e500b..689568f5b62 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -195,8 +195,8 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_c * place_cost_exp power -- numbers other than one mean this is no * * longer a simple "average number of tracks"; it is some power of * * that, allowing greater penalization of narrow channels. */ - for (int high = 0; high < (int)grid_height; high++) { - for (int low = 0; low <= high; low++) { + for (int high = -1; high < (int)grid_height; high++) { + for (int low = -1; low <= high; low++) { /* Since we will divide the wiring cost by the average channel * * capacity between high and low, having only 0 width channels * * will result in infinite wiring capacity normalization * @@ -225,8 +225,8 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_c /* Now compute the inverse of the average number of tracks per channel * between high and low. Take to specified power. */ - for (int high = 0; high < (int)grid_width; high++) { - for (int low = 0; low <= high; low++) { + for (int high = -1; high < (int)grid_width; high++) { + for (int low = -1; low <= high; low++) { /* Since we will divide the wiring cost by the average channel * * capacity between high and low, having only 0 width channels * * will result in infinite wiring capacity normalization * From 35a7e3e0aa9b0997df999aadc6e73d4175df6165 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 23 Sep 2024 11:57:44 -0400 Subject: [PATCH 07/16] inline operator() --- vpr/src/place/net_cost_handler.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/vpr/src/place/net_cost_handler.h b/vpr/src/place/net_cost_handler.h index 41d3a28fa5f..798ae32fe78 100644 --- a/vpr/src/place/net_cost_handler.h +++ b/vpr/src/place/net_cost_handler.h @@ -192,10 +192,8 @@ class NetCostHandler { class ChanPlaceCostFacContainer : public vtr::NdMatrix { public: - float& operator()(int i, int j) { - size_t ipp = i + 1; - size_t jpp = j + 1; - return this->operator[](ipp).operator[](jpp); + inline float& operator()(int i, int j) { + return this->operator[]((size_t)(i+1)).operator[]((size_t)(j+1)); } private: From 0693f1d0435e171ea315c8641d576298e9a29751 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 23 Sep 2024 17:09:38 -0400 Subject: [PATCH 08/16] add comments --- vpr/src/place/net_cost_handler.cpp | 29 +++++++++++++------------ vpr/src/place/net_cost_handler.h | 35 +++++++++++++++++++++++++----- 2 files changed, 45 insertions(+), 19 deletions(-) diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index 689568f5b62..c9c6d670da1 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -155,24 +155,12 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, } void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_cost_exp) { - /* Allocates and loads the chanx_place_cost_fac and chany_place_cost_fac * - * arrays with the inverse of the average number of tracks per channel * - * between [subhigh] and [sublow]. This is only useful for the cost * - * function that takes the length of the net bounding box in each * - * dimension divided by the average number of tracks in that direction. * - * For other cost functions, you don't have to bother calling this * - * routine; when using the cost function described above, however, you * - * must always call this routine after you call init_chan and before * - * you do any placement cost determination. The place_cost_exp factor * - * specifies to what power the width of the channel should be taken -- * - * larger numbers make narrower channels more expensive. */ - auto& device_ctx = g_vpr_ctx.device(); const size_t grid_height = device_ctx.grid.height(); const size_t grid_width = device_ctx.grid.width(); - /* Access arrays below as chan?_place_cost_fac[subhigh][sublow]. Since subhigh must be greater than or + /* Access arrays below as chan?_place_cost_fac_(subhigh, sublow). Since subhigh must be greater than or * equal to sublow, we will only access the lower half of a matrix, but we allocate the whole matrix anyway * for simplicity, so we can use the vtr utility matrix functions. */ chanx_place_cost_fac_.resize({grid_height + 1, grid_height + 1}); @@ -189,7 +177,7 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_c } /* Now compute the inverse of the average number of tracks per channel * - * between high and low. The cost function divides by the average * + * between high and low. The cost function divides by the average * * number of tracks per channel, so by storing the inverse I convert * * this to a faster multiplication. Take this final number to the * * place_cost_exp power -- numbers other than one mean this is no * @@ -1400,6 +1388,7 @@ void NetCostHandler::get_layer_bb_from_scratch_(ClusterNetId net_id, } } + double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { // Finds the cost due to one net by looking at its coordinate bounding box. auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -1415,6 +1404,12 @@ double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { /* Cost = wire length along channel * cross_count / average * * channel capacity. Do this for x, then y direction and add. */ + /* For average channel width factor, I'll always include the channel immediately + * below and the channel immediately to the left of the bounding box, so both bb.ymin + * and bb.xmin are subtracted by 1 before being used as indices of chan?_place_cost_fac_. + * chan?_place_cost_fac_ objects can handle -1 indices internally. + */ + double ncost; ncost = (bb.xmax - bb.xmin + 1) * crossing * chanx_place_cost_fac_(bb.ymax, bb.ymin - 1); ncost += (bb.ymax - bb.ymin + 1) * crossing * chany_place_cost_fac_(bb.xmax, bb.xmin - 1); @@ -1452,6 +1447,12 @@ double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use /* Cost = wire length along channel * cross_count / average * * channel capacity. Do this for x, then y direction and add. */ + /* For average channel width factor, I'll always include the channel immediately + * below and the channel immediately to the left of the bounding box, so both bb.ymin + * and bb.xmin are subtracted by 1 before being used as indices of chan?_place_cost_fac_. + * chan?_place_cost_fac_ objects can handle -1 indices internally. + */ + ncost += (bb[layer_num].xmax - bb[layer_num].xmin + 1) * crossing * chanx_place_cost_fac_(bb[layer_num].ymax, bb[layer_num].ymin - 1); diff --git a/vpr/src/place/net_cost_handler.h b/vpr/src/place/net_cost_handler.h index 798ae32fe78..9f22475765c 100644 --- a/vpr/src/place/net_cost_handler.h +++ b/vpr/src/place/net_cost_handler.h @@ -190,10 +190,28 @@ class NetCostHandler { vtr::vector proposed_net_cost_; vtr::vector bb_update_status_; + /** + * @brief This class is used to store the inverse of average channel + * width between two channels inclusive. The difference of this class + * with vtr::NdMatrix is that its index spaces starts from -1. + * When the inverse average channel width is factored in, the channel + * immediately below and the channel immediately to the left of the + * bounding box are also considered. This class makes sure that when + * the left and bottom edges of the bounding boxes are moved by one unit, + * the indices used to access inverse average channel width are still valid. + */ class ChanPlaceCostFacContainer : public vtr::NdMatrix { public: - inline float& operator()(int i, int j) { - return this->operator[]((size_t)(i+1)).operator[]((size_t)(j+1)); + /** + * @brief Returns the inverse average channel width between channels low + * and high inclusive. + * @param high The high channel number. + * @param low The low channel number. + * @return The inverse average channel width between the given channel + * numbers. + */ + inline float& operator()(int high, int low) { + return this->operator[]((size_t)(high + 1)).operator[]((size_t)(low + 1)); } private: @@ -203,14 +221,14 @@ class NetCostHandler { /** * @brief Matrices below are used to precompute the inverse of the average * number of tracks per channel between [subhigh] and [sublow]. Access - * them as chan?_place_cost_fac[subhigh][sublow]. They are used to + * them as chan?_place_cost_fac(subhigh, sublow). They are used to * speed up the computation of the cost function that takes the length * of the net bounding box in each dimension, divided by the average * number of tracks in that direction; for other cost functions they * will never be used. */ - ChanPlaceCostFacContainer chanx_place_cost_fac_; // [0...device_ctx.grid.width()-2] - ChanPlaceCostFacContainer chany_place_cost_fac_; // [0...device_ctx.grid.height()-2] + ChanPlaceCostFacContainer chanx_place_cost_fac_; // [-1...device_ctx.grid.width()-1] + ChanPlaceCostFacContainer chany_place_cost_fac_; // [-1...device_ctx.grid.height()-1] private: @@ -253,6 +271,13 @@ class NetCostHandler { /** * @brief Allocates and loads the chanx_place_cost_fac and chany_place_cost_fac arrays with the inverse of * the average number of tracks per channel between [subhigh] and [sublow]. + * + * @details This is only useful for the cost function that takes the length of the net bounding box in each + * dimension divided by the average number of tracks in that direction. For other cost functions, you don't + * have to bother calling this routine; when using the cost function described above, however, you must always + * call this routine before you do any placement cost determination. The place_cost_exp factor specifies to + * what power the width of the channel should be taken -- larger numbers make narrower channels more expensive. + * * @param place_cost_exp It is an exponent to which you take the average inverse channel capacity; * a higher value would favour wider channels more over narrower channels during placement (usually we use 1). */ From 625a61047fb28e79d195c88ebd230b91b31cabee Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 23 Sep 2024 17:23:00 -0400 Subject: [PATCH 09/16] update basic golder results --- .../basic_no_timing/config/golden_results.txt | 10 +++++----- .../basic_no_timing/config/golden_results.txt | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt index 7d583e4c3f4..0241f19b910 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 2.61 vpr 61.47 MiB -1 -1 0.41 18112 3 0.09 -1 -1 33112 -1 -1 69 99 1 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62948 99 130 353 483 1 220 299 13 13 169 clb auto 22.6 MiB 0.04 540 29270 3582 8022 17666 61.5 MiB 0.02 0.00 36 1178 8 3.33e+06 2.19e+06 481319. 2848.04 0.89 -k4_N10_memSize16384_memData64.xml diffeq1.v common 4.95 vpr 64.53 MiB -1 -1 0.72 23016 23 0.29 -1 -1 34312 -1 -1 71 162 0 5 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66076 162 96 1200 1141 1 688 334 13 13 169 clb auto 25.7 MiB 0.17 4622 86026 24278 56070 5678 64.5 MiB 0.16 0.00 50 10124 42 3.33e+06 2.58e+06 641417. 3795.37 1.79 -k4_N10_memSize16384_memData64.xml single_wire.v common 1.00 vpr 58.46 MiB -1 -1 0.15 16036 1 0.02 -1 -1 29872 -1 -1 0 1 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 59864 1 1 1 2 0 1 2 3 3 9 -1 auto 20.0 MiB 0.00 2 3 3 0 0 58.5 MiB 0.00 0.00 2 2 1 30000 0 1489.46 165.495 0.00 -k4_N10_memSize16384_memData64.xml single_ff.v common 1.02 vpr 58.49 MiB -1 -1 0.16 16284 1 0.02 -1 -1 29928 -1 -1 1 2 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 59892 2 1 3 4 1 3 4 3 3 9 -1 auto 19.7 MiB 0.00 4 9 6 0 3 58.5 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time + k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.91 vpr 65.59 MiB -1 -1 0.21 21296 3 0.05 -1 -1 39652 -1 -1 69 99 1 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67160 99 130 353 483 1 220 299 13 13 169 clb auto 26.9 MiB 0.03 692 29270 3600 8725 16945 65.6 MiB 0.03 0.00 30 1400 11 3.33e+06 2.19e+06 408126. 2414.95 1.08 + k4_N10_memSize16384_memData64.xml diffeq1.v common 4.43 vpr 69.27 MiB -1 -1 0.31 26352 23 0.22 -1 -1 41100 -1 -1 71 162 0 5 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 70936 162 96 1200 1141 1 688 334 13 13 169 clb auto 30.2 MiB 0.11 5199 75604 21039 49822 4743 69.3 MiB 0.10 0.00 54 10333 34 3.33e+06 2.58e+06 696024. 4118.48 2.85 + k4_N10_memSize16384_memData64.xml single_wire.v common 0.25 vpr 63.52 MiB -1 -1 0.05 19840 1 0.01 -1 -1 35512 -1 -1 0 1 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65048 1 1 1 2 0 1 2 3 3 9 -1 auto 25.1 MiB 0.00 2 3 1 2 0 63.5 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 + k4_N10_memSize16384_memData64.xml single_ff.v common 0.26 vpr 63.64 MiB -1 -1 0.06 19968 1 0.01 -1 -1 35756 -1 -1 1 2 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65172 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 6 9 4 1 4 63.6 MiB 0.00 0.00 18 13 1 30000 30000 3112.78 345.864 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt index a66baaecb4a..9c8e3fb5217 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.83 0.03 8960 4 0.21 -1 -1 36092 -1 -1 72 99 1 0 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 34468 99 130 378 508 1 260 302 13 13 169 clb auto 0.05 602 0.16 0.00 36 1421 8 3.33e+06 2.28e+06 481319. 2848.04 0.73 - k4_N10_memSize16384_memData64.xml diffeq1.v common 2.98 0.04 8784 23 0.24 -1 -1 34032 -1 -1 72 162 0 5 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 37256 162 96 1214 1147 1 676 335 13 13 169 clb auto 0.14 4543 0.24 0.00 50 10225 50 3.33e+06 2.61e+06 641417. 3795.37 1.46 - k4_N10_memSize16384_memData64.xml single_wire.v common 0.28 0.01 5576 1 0.01 -1 -1 29552 -1 -1 0 1 0 0 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 22644 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 - k4_N10_memSize16384_memData64.xml single_ff.v common 0.33 0.01 5472 1 0.01 -1 -1 29636 -1 -1 1 2 0 0 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 22508 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time + k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.31 vpr 65.73 MiB 0.02 9472 -1 -1 4 0.19 -1 -1 42360 -1 -1 72 99 1 0 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67304 99 130 378 508 1 260 302 13 13 169 clb auto 27.0 MiB 0.03 975 80250 22205 36468 21577 65.7 MiB 0.08 0.00 36 1771 10 3.33e+06 2.28e+06 481319. 2848.04 0.42 + k4_N10_memSize16384_memData64.xml diffeq1.v common 3.61 vpr 69.33 MiB 0.02 9472 -1 -1 23 0.20 -1 -1 41432 -1 -1 72 162 0 5 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 70992 162 96 1214 1147 1 676 335 13 13 169 clb auto 30.4 MiB 0.12 4968 89886 25356 58643 5887 69.3 MiB 0.12 0.00 52 9486 14 3.33e+06 2.61e+06 671819. 3975.26 2.33 + k4_N10_memSize16384_memData64.xml single_wire.v common 0.21 vpr 63.40 MiB 0.01 5888 -1 -1 1 0.01 -1 -1 35384 -1 -1 0 1 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64920 1 1 1 2 0 1 2 3 3 9 -1 auto 25.1 MiB 0.00 2 3 1 2 0 63.4 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 + k4_N10_memSize16384_memData64.xml single_ff.v common 0.20 vpr 63.39 MiB 0.01 5760 -1 -1 1 0.01 -1 -1 33768 -1 -1 1 2 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64916 2 1 3 4 1 3 4 3 3 9 -1 auto 25.1 MiB 0.00 6 9 4 1 4 63.4 MiB 0.00 0.00 18 13 1 30000 30000 3112.78 345.864 0.01 From 08d152c88154078d5232597eecb35ef026192c1a Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 23 Sep 2024 18:27:46 -0400 Subject: [PATCH 10/16] increase channel width for two run failures in vtr_strong amd vtr_strong_odin --- .../strong_router_lookahead/config/config.txt | 2 +- .../strong_router_lookahead/config/golden_results.txt | 10 +++++----- .../strong_router_lookahead/config/config.txt | 2 +- .../strong_router_lookahead/config/golden_results.txt | 10 +++++----- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/config.txt index a083912ff39..8907e4c73f5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/config.txt @@ -24,7 +24,7 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements_fixed_chan_width.txt # Script parameters -script_params_common = -starting_stage vpr --route_chan_width 60 --seed 3 +script_params_common = -starting_stage vpr --route_chan_width 62 --seed 3 script_params_list_add = --router_lookahead classic script_params_list_add = --router_lookahead map script_params_list_add = --router_lookahead extended_map diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index a0daaefafa3..8a39b0e4462 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.35 vpr 68.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 69888 8 63 748 811 0 474 151 13 13 169 clb auto 30.4 MiB 0.31 4777 68.2 MiB 0.23 0.01 3.84784 -163.483 -3.84784 nan 0.02 0.00149621 0.00123439 0.0680564 0.0585257 7011 4316 16294 1362887 232193 6.63067e+06 4.31152e+06 558096. 3302.35 27 4.15031 nan -189.888 -4.15031 0 0 68.2 MiB 0.39 0.209726 0.185599 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.50 vpr 68.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 70008 8 63 748 811 0 474 151 13 13 169 clb auto 30.5 MiB 0.32 4759 68.4 MiB 0.24 0.00 3.67264 -162.529 -3.67264 nan 0.01 0.00116165 0.000946418 0.0713954 0.0615431 7326 5473 20855 994356 157566 6.63067e+06 4.31152e+06 558096. 3302.35 34 4.16213 nan -189.536 -4.16213 0 0 68.4 MiB 0.44 0.213858 0.187505 68.4 MiB 0.15 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 2.41 vpr 68.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 69912 8 63 748 811 0 474 151 13 13 169 clb auto 30.4 MiB 0.30 4766 68.3 MiB 0.29 0.00 3.67734 -167.75 -3.67734 nan 0.02 0.00148412 0.00129547 0.0899822 0.0779226 7123 6415 26021 2027398 339751 6.63067e+06 4.31152e+06 558096. 3302.35 47 4.4134 nan -189.241 -4.4134 0 0 68.3 MiB 0.61 0.252432 0.222798 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.56 vpr 68.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 69836 8 63 748 811 0 474 151 13 13 169 clb auto 30.2 MiB 0.29 4766 68.2 MiB 0.32 0.00 3.67734 -167.75 -3.67734 nan 0.03 0.00110913 0.00093313 0.127833 0.101877 7123 6415 26021 2027398 339751 6.63067e+06 4.31152e+06 558096. 3302.35 47 4.4134 nan -189.241 -4.4134 0 0 68.2 MiB 0.67 0.295742 0.24731 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.46 vpr 67.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-11389-g625a61047 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-23T17:49:05 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/vtr-verilog-to-routing/vtr_flow 69056 8 63 748 811 0 474 151 13 13 169 clb auto 28.2 MiB 0.33 4925 14186 2812 10318 1056 67.4 MiB 0.22 0.01 3.93703 -166.673 -3.93703 nan 0.02 0.00225693 0.00200229 0.0979565 0.0884414 6903 14.5633 1898 4.00422 3929 14413 1232679 208639 6.63067e+06 4.31152e+06 577501. 3417.16 23 13292 85338 -1 4.36892 nan -190.868 -4.36892 0 0 0.09 -1 -1 67.4 MiB 0.33 0.226128 0.201736 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.53 vpr 67.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-11389-g625a61047 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-23T17:49:05 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/vtr-verilog-to-routing/vtr_flow 69144 8 63 748 811 0 474 151 13 13 169 clb auto 28.3 MiB 0.32 4860 15790 3063 11462 1265 67.5 MiB 0.24 0.01 4.29693 -193.727 -4.29693 nan 0.00 0.00226483 0.00201463 0.106166 0.0957802 6879 14.5127 1879 3.96413 4087 15882 659925 103848 6.63067e+06 4.31152e+06 577501. 3417.16 24 13292 85338 -1 4.41049 nan -200.759 -4.41049 0 0 0.09 -1 -1 67.5 MiB 0.30 0.250433 0.224299 67.5 MiB -1 0.13 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 2.42 vpr 67.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-11389-g625a61047 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-23T17:49:05 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/vtr-verilog-to-routing/vtr_flow 69116 8 63 748 811 0 474 151 13 13 169 clb auto 28.3 MiB 0.31 4839 12582 2336 9502 744 67.5 MiB 0.19 0.01 3.61483 -159.25 -3.61483 nan 0.03 0.00228626 0.0020217 0.0847617 0.0764979 7006 14.7806 1933 4.07806 4489 16137 1303855 215072 6.63067e+06 4.31152e+06 577501. 3417.16 27 13292 85338 -1 4.34694 nan -183.291 -4.34694 0 0 0.09 -1 -1 67.5 MiB 0.39 0.229114 0.203112 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.41 vpr 67.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-11389-g625a61047 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-23T17:49:05 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/vtr-verilog-to-routing/vtr_flow 69228 8 63 748 811 0 474 151 13 13 169 clb auto 28.3 MiB 0.31 4839 12582 2336 9502 744 67.6 MiB 0.19 0.01 3.61483 -159.25 -3.61483 nan 0.03 0.00229369 0.00203749 0.0853409 0.0771116 7006 14.7806 1933 4.07806 4489 16137 1303855 215072 6.63067e+06 4.31152e+06 577501. 3417.16 27 13292 85338 -1 4.34694 nan -183.291 -4.34694 0 0 0.09 -1 -1 67.6 MiB 0.39 0.232245 0.205938 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/config.txt index a083912ff39..8907e4c73f5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/config.txt @@ -24,7 +24,7 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements_fixed_chan_width.txt # Script parameters -script_params_common = -starting_stage vpr --route_chan_width 60 --seed 3 +script_params_common = -starting_stage vpr --route_chan_width 62 --seed 3 script_params_list_add = --router_lookahead classic script_params_list_add = --router_lookahead map script_params_list_add = --router_lookahead extended_map diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt index 969b38e82e3..a344f7d6fb5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.67 vpr 65.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 67520 8 63 748 811 0 474 151 13 13 169 clb auto 28.0 MiB 0.59 4777 65.9 MiB 0.38 0.01 3.84784 -163.483 -3.84784 nan 0.03 0.00252029 0.00221609 0.11533 0.102031 7011 4316 16294 1362887 232193 6.63067e+06 4.31152e+06 558096. 3302.35 27 4.15031 nan -189.888 -4.15031 0 0 65.9 MiB 0.77 0.303909 0.272618 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.78 vpr 66.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 67868 8 63 748 811 0 474 151 13 13 169 clb auto 28.4 MiB 0.51 4759 66.3 MiB 0.34 0.01 3.67264 -162.529 -3.67264 nan 0.02 0.00248842 0.00215226 0.109845 0.0972405 7326 5473 20855 994356 157566 6.63067e+06 4.31152e+06 558096. 3302.35 34 4.16213 nan -189.536 -4.16213 0 0 66.3 MiB 0.90 0.31527 0.281483 66.3 MiB 0.18 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 3.90 vpr 66.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 67892 8 63 748 811 0 474 151 13 13 169 clb auto 28.4 MiB 0.52 4766 66.3 MiB 0.49 0.00 3.67734 -167.75 -3.67734 nan 0.03 0.00171022 0.00153169 0.120106 0.105978 7123 6415 26021 2027398 339751 6.63067e+06 4.31152e+06 558096. 3302.35 47 4.4134 nan -189.241 -4.4134 0 0 66.3 MiB 1.16 0.413244 0.360012 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.81 vpr 66.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 67600 8 63 748 811 0 474 151 13 13 169 clb auto 28.1 MiB 0.49 4766 66.0 MiB 0.48 0.01 3.67734 -167.75 -3.67734 nan 0.03 0.00221978 0.00198473 0.130765 0.106866 7123 6415 26021 2027398 339751 6.63067e+06 4.31152e+06 558097. 3302.35 47 4.4134 nan -189.241 -4.4134 0 0 66.0 MiB 1.13 0.408674 0.355573 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.41 vpr 67.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-11389-g625a61047 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-23T17:49:05 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/vtr-verilog-to-routing/vtr_flow 69136 8 63 748 811 0 474 151 13 13 169 clb auto 28.3 MiB 0.31 4925 14186 2812 10318 1056 67.5 MiB 0.21 0.01 3.93703 -166.673 -3.93703 nan 0.02 0.002265 0.00201026 0.0957948 0.0863492 6903 14.5633 1898 4.00422 3929 14413 1232679 208639 6.63067e+06 4.31152e+06 577501. 3417.16 23 13292 85338 -1 4.36892 nan -190.868 -4.36892 0 0 0.09 -1 -1 67.5 MiB 0.33 0.22016 0.196204 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.51 vpr 67.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-11389-g625a61047 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-23T17:49:05 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/vtr-verilog-to-routing/vtr_flow 69228 8 63 748 811 0 474 151 13 13 169 clb auto 28.4 MiB 0.31 4860 15790 3063 11462 1265 67.6 MiB 0.24 0.01 4.29693 -193.727 -4.29693 nan 0.00 0.00229611 0.00204527 0.104137 0.0937984 6879 14.5127 1879 3.96413 4087 15882 659925 103848 6.63067e+06 4.31152e+06 577501. 3417.16 24 13292 85338 -1 4.41049 nan -200.759 -4.41049 0 0 0.09 -1 -1 67.6 MiB 0.31 0.240893 0.214452 67.6 MiB -1 0.12 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 2.35 vpr 67.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-11389-g625a61047 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-23T17:49:05 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/vtr-verilog-to-routing/vtr_flow 69224 8 63 748 811 0 474 151 13 13 169 clb auto 28.4 MiB 0.28 4839 12582 2336 9502 744 67.6 MiB 0.19 0.01 3.61483 -159.25 -3.61483 nan 0.03 0.00226371 0.00200769 0.0849314 0.0767223 7006 14.7806 1933 4.07806 4489 16137 1303855 215072 6.63067e+06 4.31152e+06 577501. 3417.16 27 13292 85338 -1 4.34694 nan -183.291 -4.34694 0 0 0.09 -1 -1 67.6 MiB 0.39 0.227297 0.201685 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.46 vpr 67.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-11389-g625a61047 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-23T17:49:05 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/vtr-verilog-to-routing/vtr_flow 69052 8 63 748 811 0 474 151 13 13 169 clb auto 28.2 MiB 0.31 4839 12582 2336 9502 744 67.4 MiB 0.19 0.01 3.61483 -159.25 -3.61483 nan 0.03 0.0022842 0.00202119 0.0859867 0.0776221 7006 14.7806 1933 4.07806 4489 16137 1303855 215072 6.63067e+06 4.31152e+06 577501. 3417.16 27 13292 85338 -1 4.34694 nan -183.291 -4.34694 0 0 0.09 -1 -1 67.4 MiB 0.38 0.231554 0.205592 -1 -1 -1 From afe22e28c8f0012844e602f63398fab07988f741 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Tue, 24 Sep 2024 14:27:08 -0400 Subject: [PATCH 11/16] update golden results in strong and strong_odin --- .../strong_bidir/config/golden_results.txt | 10 ++--- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 12 +++--- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 40 +++++++++---------- .../strong_sdc/config/golden_results.txt | 12 +++--- .../strong_bidir/config/golden_results.txt | 10 ++--- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 40 +++++++++---------- .../strong_power/config/golden_results.txt | 4 +- .../strong_sdc/config/golden_results.txt | 12 +++--- 15 files changed, 88 insertions(+), 88 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 5e1d0a58a70..3f2209a5524 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 1.48 vpr 57.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 58568 10 10 253 263 1 169 87 11 11 121 clb auto 19.0 MiB 0.04 1270 57.2 MiB 0.04 0.00 5.46016 -69.6089 -5.46016 5.46016 0.13 0.000215331 0.000171987 0.00792391 0.00665338 13 1998 44 2.43e+06 2.01e+06 -1 -1 0.67 0.0832184 0.0722661 2006 27 1483 4679 322103 41342 9.23088 9.23088 -107.619 -9.23088 0 0 -1 -1 0.03 0.08 0.0198743 0.0176388 - k4_n4_v7_longline_bidir.xml styr.blif common 2.03 vpr 57.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 58680 10 10 253 263 1 169 87 11 11 121 clb auto 19.1 MiB 0.04 1274 57.3 MiB 0.04 0.00 5.85046 -74.2233 -5.85046 5.85046 0.19 0.000232214 0.000188182 0.00878653 0.00745938 18 2532 43 2.43e+06 2.01e+06 -1 -1 0.88 0.0924504 0.0755557 2435 38 2098 6378 540887 56511 9.2499 9.2499 -108.539 -9.2499 0 0 -1 -1 0.07 0.11 0.0228221 0.0199636 - k4_n4_v7_l1_bidir.xml styr.blif common 2.31 vpr 57.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 58420 10 10 253 263 1 169 87 11 11 121 clb auto 18.8 MiB 0.04 1314 57.1 MiB 0.05 0.00 7.03989 -83.5605 -7.03989 7.03989 0.17 0.000198421 0.000157186 0.0109691 0.00909187 11 1696 38 2.43e+06 2.01e+06 -1 -1 1.33 0.0788319 0.0684137 1347 23 1338 4185 371579 77951 8.29094 8.29094 -101.157 -8.29094 0 0 -1 -1 0.04 0.10 0.0180735 0.0162332 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.59 vpr 57.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 58404 10 10 253 263 1 169 87 11 11 121 clb auto 18.8 MiB 0.04 1338 57.0 MiB 0.06 0.00 6.19376 -68.5604 -6.19376 6.19376 0.46 0.000203538 0.000160851 0.0127857 0.0106469 16 2173 41 2.43e+06 2.01e+06 -1 -1 1.21 0.0981799 0.0859522 2120 27 1736 5578 1452395 185427 17.5032 17.5032 -249.6 -17.5032 0 0 -1 -1 0.04 0.26 0.0209466 0.0188615 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k4_n4_v7_bidir.xml styr.blif common 1.48 vpr 60.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61704 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1321 5000 862 3861 277 60.3 MiB 0.03 0.00 5.9335 -73.3937 -5.9335 5.9335 0.11 0.000261327 0.000224398 0.00853268 0.00751629 16 2231 44 2.43e+06 1.98e+06 -1 -1 0.82 0.103535 0.088869 3522 30407 -1 1953 31 1359 4378 262510 29492 8.05167 8.05167 -93.2354 -8.05167 0 0 -1 -1 0.04 0.05 0.01 -1 -1 0.04 0.0186186 0.0166315 + k4_n4_v7_longline_bidir.xml styr.blif common 1.35 vpr 60.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61660 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1283 3299 376 2835 88 60.2 MiB 0.02 0.00 4.65232 -54.7485 -4.65232 4.65232 0.17 0.000261335 0.000226611 0.00623888 0.00553939 18 2324 34 2.43e+06 1.98e+06 -1 -1 0.50 0.0674339 0.0582272 3282 34431 -1 2358 20 1330 4111 330217 37900 9.15177 9.15177 -106.099 -9.15177 0 0 -1 -1 0.08 0.05 0.01 -1 -1 0.08 0.0141075 0.0127004 + k4_n4_v7_l1_bidir.xml styr.blif common 1.68 vpr 60.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61736 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1308 8591 1804 6310 477 60.3 MiB 0.05 0.00 7.13454 -91.9395 -7.13454 7.13454 0.16 0.00024201 0.00020955 0.0132111 0.0116469 11 1687 50 2.43e+06 1.98e+06 -1 -1 0.85 0.0715403 0.0620252 4842 26197 -1 1434 21 1413 4826 393565 72389 8.93712 8.93712 -111.541 -8.93712 0 0 -1 -1 0.04 0.07 0.01 -1 -1 0.04 0.0141585 0.0126514 + k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.75 vpr 60.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61708 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1271 3677 486 3031 160 60.3 MiB 0.03 0.00 3.40634 -44.4904 -3.40634 3.40634 0.12 0.000249094 0.000211604 0.00674832 0.00592154 16 2163 32 2.43e+06 1.98e+06 -1 -1 0.92 0.0676003 0.058382 3522 30407 -1 2237 32 1642 5759 1828879 289403 29.985 29.985 -297.537 -29.985 0 0 -1 -1 0.04 0.21 0.01 -1 -1 0.04 0.0186587 0.0165112 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index b3badd093b7..a40279b9f9c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.47 vpr 61.68 MiB -1 -1 0.14 17412 1 0.02 -1 -1 30092 -1 -1 3 9 0 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63160 9 8 75 70 1 34 20 5 5 25 clb auto 23.0 MiB 0.48 71 587 167 407 13 61.7 MiB 0.01 0.00 2.64007 -28.8002 -2.64007 2.64007 0.02 0.00018874 0.0001749 0.00515172 0.00481814 26 158 12 151211 75605.7 37105.9 1484.24 0.07 0.0263968 0.0224852 1908 5841 -1 154 11 104 116 4129 2171 2.87707 2.87707 -34.6861 -2.87707 0 0 45067.1 1802.68 0.00 0.01 0.01 -1 -1 0.00 0.00661492 0.00590698 13 18 -1 -1 -1 -1 -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 5.70 vpr 62.75 MiB -1 -1 0.19 17840 1 0.03 -1 -1 30428 -1 -1 7 19 0 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64260 19 18 308 249 1 142 44 6 6 36 clb auto 24.5 MiB 3.72 448 3740 1050 2663 27 62.8 MiB 0.06 0.00 4.88121 -99.2245 -4.88121 4.88121 0.05 0.00062533 0.000580812 0.0338073 0.0315436 52 1067 23 403230 176413 110337. 3064.92 0.72 0.238972 0.204378 4014 20275 -1 806 25 799 1471 58539 21843 5.26432 5.26432 -115.767 -5.26432 0 0 143382. 3982.83 0.01 0.06 0.02 -1 -1 0.01 0.0338988 0.0298411 55 83 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 0.93 vpr 65.66 MiB -1 -1 0.06 20352 1 0.01 -1 -1 35860 -1 -1 3 9 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67236 9 8 75 70 1 34 20 5 5 25 clb auto 27.3 MiB 0.38 91 452 103 339 10 65.7 MiB 0.00 0.00 2.64007 -28.7664 -2.64007 2.64007 0.02 7.4568e-05 6.6193e-05 0.00195079 0.00178739 38 154 16 151211 75605.7 48493.3 1939.73 0.11 0.0243483 0.0205304 2100 8065 -1 119 18 114 142 4814 2350 2.64007 2.64007 -31.8474 -2.64007 0 0 61632.8 2465.31 0.01 0.01 0.01 -1 -1 0.01 0.00485388 0.00446806 13 18 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 3.87 vpr 66.77 MiB -1 -1 0.08 20736 1 0.01 -1 -1 35944 -1 -1 7 19 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68372 19 18 308 249 1 142 44 6 6 36 clb auto 28.4 MiB 2.88 521 2662 840 1802 20 66.8 MiB 0.02 0.00 4.88121 -98.944 -4.88121 4.88121 0.04 0.000207626 0.000184303 0.0103914 0.00951356 54 1083 35 403230 176413 113905. 3164.04 0.39 0.0844877 0.0734258 4050 20995 -1 745 17 630 985 35752 13957 5.5504 5.5504 -118.789 -5.5504 0 0 146644. 4073.44 0.01 0.02 0.01 -1 -1 0.01 0.014306 0.0132257 55 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 600c95bab03..5d73f4813a6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.20 vpr 57.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 58412 3 1 5 6 1 4 5 3 3 9 -1 auto 17.9 MiB 0.00 6 57.0 MiB 0.00 0.00 0.544641 -0.918653 -0.544641 0.544641 0.00 8.569e-06 5.385e-06 6.4543e-05 4.6229e-05 20 7 1 53894 53894 4880.82 542.314 0.00 0.000195384 0.00014468 7 1 3 3 40 30 0.681349 0.681349 -1.22599 -0.681349 0 0 6579.40 731.044 0.00 0.00 0.000109941 8.7312e-05 - k6_frac_N10_40nm.xml conn_order.eblif common 0.20 vpr 56.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 58124 2 1 4 5 1 3 4 3 3 9 -1 auto 17.8 MiB 0.00 4 56.8 MiB 0.00 0.00 0.709011 -1.25365 -0.709011 0.709011 0.00 7.609e-06 4.5e-06 6.564e-05 4.6586e-05 20 10 1 53894 53894 4880.82 542.314 0.00 0.000186162 0.000138088 18 2 3 3 70 58 1.93748 1.93748 -2.483 -1.93748 0 0 6579.40 731.044 0.00 0.00 0.000127915 0.000100994 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml test_eblif.eblif common 0.12 vpr 60.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61552 3 1 5 6 1 4 5 3 3 9 -1 auto 21.6 MiB 0.00 9 12 1 9 2 60.1 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.0349e-05 7.103e-06 8.7732e-05 6.8547e-05 20 10 1 53894 53894 4880.82 542.314 0.00 0.00111687 0.00105846 379 725 -1 6 1 3 3 36 25 0.605178 0.605178 -1.1507 -0.605178 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00107362 0.00104552 + k6_frac_N10_40nm.xml conn_order.eblif common 0.12 vpr 59.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61420 2 1 4 5 1 3 4 3 3 9 -1 auto 21.6 MiB 0.00 6 9 2 3 4 60.0 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.4366e-05 1.0429e-05 0.000128779 0.000106057 20 9 1 53894 53894 4880.82 542.314 0.00 0.00110538 0.00104614 379 725 -1 5 1 2 2 25 19 0.940178 0.940178 -1.48482 -0.940178 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00106677 0.00104008 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index d8cabfc840f..6cc6316b230 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 1.73 vpr 64.92 MiB -1 -1 0.63 25276 5 0.16 -1 -1 37176 -1 -1 7 10 0 0 success b93114b release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-05-16T13:37:54 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 66480 10 2 181 183 1 37 19 6 6 36 clb auto 26.3 MiB 0.06 110 594 150 401 43 64.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000294971 0.000262303 0.00999083 0.0090646 8 79 3 646728 377258 -1 -1 0.08 0.0453834 0.0395279 1804 2280 -1 77 3 61 85 2669 843 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00974423 0.00923886 - x_uniform_y_gaussian.xml stereovision3.v common 1.77 vpr 64.76 MiB -1 -1 0.62 25316 5 0.16 -1 -1 36908 -1 -1 7 10 0 0 success b93114b release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-05-16T13:37:54 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 66312 10 2 181 183 1 37 19 6 6 36 clb auto 26.1 MiB 0.06 109 544 174 318 52 64.8 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000339962 0.000303899 0.0100167 0.00911542 6 109 21 646728 377258 -1 -1 0.12 0.0580255 0.0502964 1804 2280 -1 77 3 66 90 2561 887 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.010375 0.00976898 - x_gaussian_y_gaussian.xml stereovision3.v common 1.62 vpr 64.61 MiB -1 -1 0.57 25276 5 0.16 -1 -1 37220 -1 -1 7 10 0 0 success b93114b release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-05-16T13:37:54 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 66164 10 2 181 183 1 37 19 6 6 36 clb auto 26.1 MiB 0.06 110 694 176 468 50 64.6 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000302965 0.000269217 0.0115316 0.0104852 8 78 3 646728 377258 -1 -1 0.08 0.0481134 0.0420436 1804 2280 -1 80 3 56 77 2444 765 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00991256 0.00939908 - x_delta_y_uniform.xml stereovision3.v common 1.86 vpr 64.89 MiB -1 -1 0.61 25392 5 0.17 -1 -1 37056 -1 -1 7 10 0 0 success b93114b release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-05-16T13:37:54 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 66452 10 2 181 183 1 37 19 6 6 36 clb auto 26.4 MiB 0.06 122 194 64 115 15 64.9 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000358492 0.000315992 0.0053859 0.00499525 18 90 3 646728 377258 -1 -1 0.18 0.0804512 0.0683474 1804 2280 -1 90 3 58 74 2193 794 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00992565 0.00940704 - x_delta_y_delta.xml stereovision3.v common 1.72 vpr 64.73 MiB -1 -1 0.60 25256 5 0.16 -1 -1 37136 -1 -1 7 10 0 0 success b93114b release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-05-16T13:37:54 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 66280 10 2 181 183 1 37 19 6 6 36 clb auto 26.2 MiB 0.06 113 669 200 418 51 64.7 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000358653 0.000319961 0.0120938 0.0109347 28 78 3 646728 377258 -1 -1 0.08 0.0507173 0.0441205 1804 2280 -1 78 3 60 82 2619 842 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0127115 0.0122068 - x_uniform_y_delta.xml stereovision3.v common 1.66 vpr 64.96 MiB -1 -1 0.58 25516 5 0.16 -1 -1 37200 -1 -1 7 10 0 0 success b93114b release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-05-16T13:37:54 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 66516 10 2 181 183 1 37 19 6 6 36 clb auto 26.4 MiB 0.06 115 569 114 397 58 65.0 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000323685 0.000288401 0.00998254 0.00910662 16 93 5 646728 377258 -1 -1 0.10 0.0484561 0.0422523 1804 2280 -1 83 3 59 80 2528 826 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00999757 0.00947752 + x_gaussian_y_uniform.xml stereovision3.v common 1.04 vpr 66.41 MiB -1 -1 0.43 26112 5 0.10 -1 -1 38916 -1 -1 7 10 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68000 10 2 181 183 1 37 19 6 6 36 clb auto 28.2 MiB 0.04 116 469 132 309 28 66.4 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000138168 0.000118301 0.00425649 0.00383687 8 78 3 646728 377258 -1 -1 0.04 0.0245278 0.0216143 1804 2280 -1 78 3 56 79 2317 690 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00721679 0.00692586 + x_uniform_y_gaussian.xml stereovision3.v common 1.05 vpr 66.39 MiB -1 -1 0.44 26112 5 0.10 -1 -1 38924 -1 -1 7 10 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67988 10 2 181 183 1 37 19 6 6 36 clb auto 28.0 MiB 0.04 118 669 184 441 44 66.4 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000156902 0.000136544 0.00589556 0.00530989 6 95 8 646728 377258 -1 -1 0.06 0.0247254 0.0217529 1804 2280 -1 76 3 72 99 2815 863 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00580214 0.00556708 + x_gaussian_y_gaussian.xml stereovision3.v common 1.06 vpr 66.40 MiB -1 -1 0.44 25856 5 0.10 -1 -1 38788 -1 -1 7 10 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67992 10 2 181 183 1 37 19 6 6 36 clb auto 28.0 MiB 0.04 116 469 114 316 39 66.4 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000141624 0.000121717 0.00429422 0.00384614 6 106 10 646728 377258 -1 -1 0.06 0.025184 0.0220839 1804 2280 -1 81 5 79 110 3380 1015 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00633534 0.00604945 + x_delta_y_uniform.xml stereovision3.v common 1.09 vpr 66.52 MiB -1 -1 0.44 26240 5 0.10 -1 -1 40736 -1 -1 7 10 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68120 10 2 181 183 1 37 19 6 6 36 clb auto 28.1 MiB 0.04 117 444 113 301 30 66.5 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000137696 0.00011826 0.0040508 0.00366202 34 76 4 646728 377258 -1 -1 0.09 0.0463587 0.0396882 1804 2280 -1 77 3 57 79 2311 671 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00567849 0.00546511 + x_delta_y_delta.xml stereovision3.v common 1.02 vpr 66.41 MiB -1 -1 0.44 25984 5 0.09 -1 -1 36772 -1 -1 7 10 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68008 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.04 118 419 102 293 24 66.4 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000152925 0.000122608 0.00406731 0.00366018 28 78 3 646728 377258 -1 -1 0.03 0.0212815 0.0187297 1804 2280 -1 78 3 54 74 2257 667 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.0057754 0.0055611 + x_uniform_y_delta.xml stereovision3.v common 1.06 vpr 66.41 MiB -1 -1 0.43 25984 5 0.09 -1 -1 36772 -1 -1 7 10 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68000 10 2 181 183 1 37 19 6 6 36 clb auto 28.0 MiB 0.04 117 519 114 373 32 66.4 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000150229 0.000130633 0.00465966 0.00420735 24 75 3 646728 377258 -1 -1 0.09 0.0461378 0.0396879 1804 2280 -1 75 2 53 72 2144 616 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00569081 0.00550877 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 9a8644cba96..fe6c3262d6b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.38001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.86636 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.38001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.86636 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.75805 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.48832 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.75805 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.48832 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt index 5fdc8c7275d..db6090c3a6a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.47 vpr 60.60 MiB -1 -1 -1 -1 0 0.02 -1 -1 33412 -1 -1 1 0 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62052 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.9 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.01 1.0457e-05 6.911e-06 7.0843e-05 5.1549e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.00100341 0.000947247 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.000947427 0.000919868 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.46 vpr 60.61 MiB -1 -1 -1 -1 0 0.02 -1 -1 33544 -1 -1 1 0 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62068 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.9 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.01 9.807e-06 6.44e-06 6.4734e-05 4.6443e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.00103495 0.000981407 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.000999319 0.000973671 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.46 vpr 60.50 MiB -1 -1 -1 -1 0 0.02 -1 -1 33296 -1 -1 1 0 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 61952 6 1 1 8 0 1 8 3 3 9 -1 auto 21.9 MiB 0.00 0 21 0 11 10 60.5 MiB 0.00 0.00 nan 0 0 nan 0.01 8.586e-06 5.536e-06 6.9841e-05 4.993e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.00103677 0.000987105 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.000633491 0.000613318 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.46 vpr 60.57 MiB -1 -1 -1 -1 0 0.02 -1 -1 33420 -1 -1 1 0 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62028 6 1 1 8 0 1 8 3 3 9 -1 auto 21.9 MiB 0.00 0 21 0 11 10 60.6 MiB 0.00 0.00 nan 0 0 nan 0.01 8.794e-06 5.563e-06 7.1881e-05 5.2215e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.00101192 0.000956181 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.001024 0.000999917 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.50 vpr 60.40 MiB -1 -1 -1 -1 1 0.02 -1 -1 33516 -1 -1 1 2 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 61852 2 1 3 4 0 3 4 3 3 9 -1 auto 21.8 MiB 0.00 6 9 6 0 3 60.4 MiB 0.00 0.00 0.442454 -0.442454 -0.442454 nan 0.01 1.3033e-05 9.875e-06 9.6316e-05 7.6402e-05 16 16 1 3900 3900 3970.02 441.113 0.02 0.00151168 0.00132158 330 691 -1 5 1 3 3 44 29 0.584298 nan -0.584298 -0.584298 0 0 4445.42 493.935 0.00 0.00 0.00 -1 -1 0.00 0.0010412 0.00101047 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.61 vpr 60.59 MiB -1 -1 -1 -1 2 0.06 -1 -1 35092 -1 -1 1 5 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62048 5 1 7 8 0 7 7 3 3 9 -1 auto 21.9 MiB 0.00 14 18 14 0 4 60.6 MiB 0.00 0.00 0.701708 -0.701708 -0.701708 nan 0.01 1.8192e-05 1.4879e-05 0.0001413 0.000120674 18 17 4 3900 3900 4264.82 473.869 0.02 0.0027609 0.00231185 346 735 -1 23 7 18 18 649 515 1.38908 nan -1.38908 -1.38908 0 0 5011.22 556.802 0.00 0.00 0.00 -1 -1 0.00 0.00122295 0.00114619 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.65 vpr 60.24 MiB -1 -1 -1 -1 2 0.05 -1 -1 35084 -1 -1 1 5 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 61688 5 1 7 8 0 7 7 3 3 9 -1 auto 21.6 MiB 0.00 14 18 14 0 4 60.2 MiB 0.00 0.00 0.701708 -0.701708 -0.701708 nan 0.01 1.8845e-05 1.5391e-05 0.000128137 0.000107184 16 33 14 3900 3900 3970.02 441.113 0.04 0.00357802 0.00287144 330 691 -1 19 2 8 8 206 162 1.34631 nan -1.34631 -1.34631 0 0 4445.42 493.935 0.00 0.00 0.00 -1 -1 0.00 0.00114164 0.00109809 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.44 vpr 60.51 MiB -1 -1 -1 -1 1 0.02 -1 -1 34484 -1 -1 1 3 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 61960 3 1 5 6 1 4 5 3 3 9 -1 auto 21.9 MiB 0.00 6 12 9 0 3 60.5 MiB 0.00 0.00 0.274843 -0.535084 -0.274843 0.274843 0.01 1.6521e-05 1.3017e-05 0.000131239 0.000109368 16 9 1 3900 3900 3970.02 441.113 0.02 0.00148928 0.0013433 330 691 -1 13 1 3 3 95 80 0.776991 0.776991 -1.10653 -0.776991 0 0 4445.42 493.935 0.00 0.00 0.00 -1 -1 0.00 0.00107699 0.00104537 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.58 vpr 60.55 MiB -1 -1 -1 -1 1 0.05 -1 -1 35752 -1 -1 1 3 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62000 4 1 4 6 0 4 6 3 3 9 -1 auto 21.8 MiB 0.00 8 15 12 0 3 60.5 MiB 0.00 0.00 0.442454 -0.442454 -0.442454 nan 0.01 1.5735e-05 1.2317e-05 0.000107693 8.9067e-05 12 12 16 3900 3900 2582.62 286.957 0.02 0.00180867 0.00156361 314 651 -1 21 18 48 48 1942 1644 1.35187 nan -1.35187 -1.35187 0 0 3970.02 441.113 0.00 0.01 0.00 -1 -1 0.00 0.00136895 0.00124924 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.46 vpr 60.56 MiB -1 -1 -1 -1 1 0.05 -1 -1 35128 -1 -1 1 4 0 0 exited with return code 2 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62012 4 4 8 12 0 8 9 3 3 9 -1 auto 21.9 MiB 0.00 17 27 23 0 4 60.6 MiB 0.00 0.00 0.442454 -1.76982 -0.442454 nan 0.01 2.8863e-05 2.438e-05 0.00019849 0.000172709 20 47 35 3900 3900 4445.42 493.935 0.04 0.00499721 0.00406667 354 763 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00 0.00 0.00 -1 -1 0.00 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 1.00 vpr 60.64 MiB -1 -1 -1 -1 3 0.06 -1 -1 35776 -1 -1 3 6 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62096 6 6 28 34 0 28 15 5 5 25 clb auto 22.2 MiB 0.01 90 51 15 36 0 60.6 MiB 0.00 0.00 1.22109 -5.53991 -1.22109 nan 0.04 8.3003e-05 7.2279e-05 0.000591374 0.000546509 24 254 25 23400 11700 20975.0 838.999 0.30 0.0244631 0.0199264 1420 4462 -1 216 19 282 1073 50766 22499 1.69944 nan -7.59202 -1.69944 0 0 27052.1 1082.08 0.01 0.02 0.01 -1 -1 0.01 0.00450964 0.00391238 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.88 vpr 60.87 MiB -1 -1 -1 -1 4 0.06 -1 -1 35792 -1 -1 5 7 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62332 7 8 39 47 0 39 20 5 5 25 clb auto 22.4 MiB 0.01 154 74 17 50 7 60.9 MiB 0.00 0.00 1.54677 -7.86002 -1.54677 nan 0.04 0.000106779 9.4302e-05 0.000776871 0.000719242 28 373 19 23400 19500 25328.9 1013.15 0.15 0.0152072 0.0127462 1476 4870 -1 293 15 297 1224 65781 28435 1.87564 nan -9.87124 -1.87564 0 0 29680.9 1187.23 0.01 0.02 0.01 -1 -1 0.01 0.00491322 0.00432064 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 1.17 vpr 60.86 MiB -1 -1 -1 -1 8 0.07 -1 -1 35964 -1 -1 7 8 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62324 8 8 51 59 0 51 23 6 6 36 clb auto 22.3 MiB 0.01 199 503 80 409 14 60.9 MiB 0.01 0.00 2.62874 -12.7894 -2.62874 nan 0.08 0.000134616 0.000120953 0.00276503 0.00250897 30 528 21 165600 27300 47960.3 1332.23 0.28 0.0212986 0.0180697 2708 10880 -1 439 21 503 2032 141498 54777 3.15238 nan -15.6665 -3.15238 0 0 61410.5 1705.85 0.02 0.04 0.02 -1 -1 0.02 0.0071604 0.00622966 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 1.55 vpr 61.26 MiB -1 -1 -1 -1 7 0.10 -1 -1 35652 -1 -1 11 10 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62728 10 10 95 105 0 95 31 6 6 36 clb auto 22.8 MiB 0.02 422 703 104 550 49 61.3 MiB 0.02 0.00 2.54568 -18.0554 -2.54568 nan 0.08 0.000234272 0.000209938 0.00478389 0.00435292 40 1055 36 165600 42900 61410.5 1705.85 0.53 0.0538987 0.0457378 2992 13730 -1 838 22 986 4180 289055 101472 2.8437 nan -20.1254 -2.8437 0 0 78756.9 2187.69 0.03 0.08 0.02 -1 -1 0.03 0.0124158 0.0107886 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 1.65 vpr 61.41 MiB -1 -1 -1 -1 8 0.10 -1 -1 36720 -1 -1 11 11 0 0 success 81e1de1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-20T21:48:56 gh-actions-runner-vtr-auto-spawned196 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62880 11 11 94 105 0 94 33 6 6 36 clb auto 22.9 MiB 0.02 404 553 74 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-1 0.01 0.00326751 0.00290812 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 0.91 vpr 62.35 MiB -1 -1 -1 -1 8 0.04 -1 -1 37068 -1 -1 7 8 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63848 8 8 51 59 0 51 23 6 6 36 clb auto 23.9 MiB 0.01 218 87 23 62 2 62.4 MiB 0.00 0.00 2.65232 -12.8401 -2.65232 nan 0.05 7.0802e-05 6.0363e-05 0.000548551 0.000504069 28 635 50 165600 27300 45013.2 1250.37 0.44 0.0222686 0.0184931 2604 9324 -1 531 20 525 2156 148800 55475 3.2769 nan -17.2194 -3.2769 0 0 53593.6 1488.71 0.01 0.02 0.01 -1 -1 0.01 0.00406269 0.00363043 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.90 vpr 62.70 MiB -1 -1 -1 -1 7 0.05 -1 -1 37832 -1 -1 11 10 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64208 10 10 95 105 0 95 31 6 6 36 clb auto 24.3 MiB 0.01 458 607 80 489 38 62.7 MiB 0.01 0.00 2.54057 -18.2603 -2.54057 nan 0.05 0.000106788 9.1771e-05 0.00197953 0.00177718 38 1072 47 165600 42900 55946.4 1554.07 0.35 0.0265862 0.0226733 2940 12782 -1 863 20 990 4097 286923 104030 2.92618 nan -21.5852 -2.92618 0 0 73011.6 2028.10 0.02 0.04 0.01 -1 -1 0.02 0.0061451 0.00551558 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 1.00 vpr 62.84 MiB -1 -1 -1 -1 8 0.06 -1 -1 41536 -1 -1 11 11 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64344 11 11 94 105 0 94 33 6 6 36 clb auto 24.3 MiB 0.01 429 657 85 535 37 62.8 MiB 0.01 0.00 2.9648 -21.4457 -2.9648 nan 0.05 0.000103943 9.2442e-05 0.00200059 0.00180664 40 1112 36 165600 42900 61410.5 1705.85 0.42 0.0288468 0.0245839 2992 13730 -1 884 19 850 3542 252924 89086 3.47123 nan -25.0388 -3.47123 0 0 78756.9 2187.69 0.02 0.04 0.01 -1 -1 0.02 0.00611204 0.00547477 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_1bit.blif common 0.29 vpr 62.13 MiB -1 -1 -1 -1 1 0.02 -1 -1 36508 -1 -1 1 3 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63624 3 2 5 7 0 5 6 3 3 9 -1 auto 23.6 MiB 0.00 15 15 8 4 3 62.1 MiB 0.00 0.00 0.442454 -0.884909 -0.442454 nan 0.00 1.1283e-05 8.006e-06 0.000108173 8.8205e-05 16 26 17 3900 3900 3970.02 441.113 0.01 0.00136397 0.00122442 330 691 -1 24 12 34 59 1656 1302 0.897144 nan -1.78596 -0.897144 0 0 4445.42 493.935 0.00 0.00 0.00 -1 -1 0.00 0.00124053 0.00115984 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.32 vpr 62.17 MiB -1 -1 -1 -1 2 0.02 -1 -1 39020 -1 -1 1 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63664 5 3 9 12 0 9 9 3 3 9 -1 auto 23.6 MiB 0.00 26 27 10 10 7 62.2 MiB 0.00 0.00 0.701708 -1.84587 -0.701708 nan 0.00 1.5359e-05 1.1792e-05 0.000139458 0.00011847 20 41 14 3900 3900 4445.42 493.935 0.03 0.00466515 0.00358618 354 763 -1 62 23 83 142 5466 4364 2.28942 nan -4.87234 -2.28942 0 0 5185.22 576.135 0.00 0.00 0.00 -1 -1 0.00 0.00167798 0.00149442 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.31 vpr 62.21 MiB -1 -1 -1 -1 3 0.03 -1 -1 39840 -1 -1 1 7 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63700 7 4 13 17 0 13 12 3 3 9 -1 auto 23.6 MiB 0.00 37 38 21 15 2 62.2 MiB 0.00 0.00 0.960961 -3.06608 -0.960961 nan 0.00 1.9757e-05 1.5869e-05 0.000178803 0.000157222 24 55 20 3900 3900 5011.22 556.802 0.01 0.0032267 0.00267312 378 957 -1 47 16 74 136 4091 2875 1.45584 nan -4.58947 -1.45584 0 0 6337.42 704.157 0.00 0.00 0.00 -1 -1 0.00 0.0016168 0.00148125 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.31 vpr 62.23 MiB -1 -1 -1 -1 4 0.03 -1 -1 39604 -1 -1 1 9 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63724 9 5 17 22 0 17 15 3 3 9 -1 auto 23.8 MiB 0.00 48 51 31 11 9 62.2 MiB 0.00 0.00 1.22021 -4.54555 -1.22021 nan 0.00 2.3734e-05 1.9446e-05 0.000202166 0.000178773 28 55 17 3900 3900 5935.82 659.535 0.01 0.00365694 0.00306018 394 1003 -1 58 13 87 148 4928 3501 1.86558 nan -6.3789 -1.86558 0 0 6854.42 761.602 0.00 0.00 0.00 -1 -1 0.00 0.00176664 0.00163559 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.41 vpr 62.16 MiB -1 -1 -1 -1 4 0.03 -1 -1 39704 -1 -1 2 11 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63652 11 6 24 30 0 24 19 4 4 16 clb auto 23.9 MiB 0.00 85 69 11 46 12 62.2 MiB 0.00 0.00 1.38419 -6.92615 -1.38419 nan 0.01 5.7979e-05 4.9933e-05 0.000372786 0.000336688 28 127 18 7800 7800 12557.4 784.840 0.08 0.00886381 0.00722294 812 2356 -1 155 18 208 453 20911 11455 1.85994 nan -8.56093 -1.85994 0 0 14986.4 936.652 0.00 0.01 0.00 -1 -1 0.00 0.00235198 0.00209145 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index eaed6cfb6d1..3ff8dccb714 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.35 vpr 63.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 6bddfe3 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-19T14:05:22 gh-actions-runner-vtr-auto-spawned2 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64796 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 16 30 11 13 6 63.3 MiB 0.00 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 2.807e-05 2.3009e-05 0.000202971 0.000171147 8 18 2 107788 107788 4794.78 299.674 0.01 0.00151709 0.00139152 564 862 -1 26 4 13 13 402 230 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00130488 0.00121897 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.34 vpr 63.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 6bddfe3 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-19T14:05:22 gh-actions-runner-vtr-auto-spawned2 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64684 5 3 11 14 2 9 10 4 4 16 clb auto 24.8 MiB 0.00 19 30 6 15 9 63.2 MiB 0.00 0.00 0.571 0 0 0.571 0.01 2.8135e-05 2.3875e-05 0.00019189 0.000165801 8 27 4 107788 107788 4794.78 299.674 0.01 0.00156501 0.00144254 564 862 -1 25 3 11 11 379 229 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00126229 0.00119668 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.35 vpr 63.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 6bddfe3 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-19T14:05:22 gh-actions-runner-vtr-auto-spawned2 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64820 5 3 11 14 2 9 10 4 4 16 clb auto 25.0 MiB 0.01 16 30 10 18 2 63.3 MiB 0.00 0.00 0.645499 -2.18826 -0.645499 0.571 0.01 3.2858e-05 2.4691e-05 0.000221753 0.000177424 8 17 3 107788 107788 4794.78 299.674 0.01 0.00166009 0.00149082 564 862 -1 14 5 15 15 287 110 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00140591 0.00129508 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.35 vpr 63.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 6bddfe3 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-19T14:05:22 gh-actions-runner-vtr-auto-spawned2 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64744 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.01 16 30 12 17 1 63.2 MiB 0.00 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 4.0389e-05 2.9209e-05 0.000246213 0.000189498 8 19 8 107788 107788 4794.78 299.674 0.01 0.00198382 0.00171208 564 862 -1 15 4 11 11 211 91 1.57153 0.571 -4.92067 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00140652 0.00129569 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.34 vpr 63.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 6bddfe3 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-19T14:05:22 gh-actions-runner-vtr-auto-spawned2 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64660 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 18 30 12 15 3 63.1 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 3.8905e-05 2.9489e-05 0.000269542 0.000218723 8 17 8 107788 107788 4794.78 299.674 0.01 0.00176198 0.00153688 564 862 -1 14 3 13 13 241 105 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00138662 0.00127541 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.34 vpr 63.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 6bddfe3 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-19T14:05:22 gh-actions-runner-vtr-auto-spawned2 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64672 5 3 11 14 2 9 10 4 4 16 clb auto 24.8 MiB 0.00 18 30 13 7 10 63.2 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 4.0481e-05 3.3326e-05 0.000216067 0.000179499 8 23 3 107788 107788 4794.78 299.674 0.01 0.00159164 0.00145319 564 862 -1 23 4 11 11 256 120 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00133524 0.00124531 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.15 vpr 64.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66040 5 3 11 14 2 9 10 4 4 16 clb auto 26.1 MiB 0.00 22 30 9 14 7 64.5 MiB 0.00 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 3.4514e-05 2.6389e-05 0.000188251 0.000157435 8 18 2 107788 107788 4794.78 299.674 0.01 0.00136356 0.00126067 564 862 -1 18 4 10 10 213 96 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00132991 0.0012563 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.15 vpr 64.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66172 5 3 11 14 2 9 10 4 4 16 clb auto 26.2 MiB 0.00 23 30 5 16 9 64.6 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.1699e-05 2.5357e-05 0.000167513 0.000139209 8 29 4 107788 107788 4794.78 299.674 0.01 0.00129724 0.00119452 564 862 -1 25 4 15 15 546 342 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00123336 0.00115491 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.15 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66304 5 3 11 14 2 9 10 4 4 16 clb auto 26.5 MiB 0.00 20 30 10 18 2 64.8 MiB 0.00 0.00 0.645499 -2.18826 -0.645499 0.571 0.01 5.5523e-05 4.2379e-05 0.000203498 0.000159839 8 17 3 107788 107788 4794.78 299.674 0.01 0.0014548 0.0013129 564 862 -1 14 4 15 15 278 103 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00123664 0.00115953 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.15 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66308 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 20 30 11 18 1 64.8 MiB 0.00 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 2.4636e-05 1.5899e-05 0.000174577 0.000131877 8 17 8 107788 107788 4794.78 299.674 0.01 0.00153355 0.00133955 564 862 -1 15 8 21 21 322 143 1.57153 0.571 -4.91875 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00136833 0.00125557 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.16 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66300 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 21 30 10 15 5 64.7 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 2.8303e-05 1.9276e-05 0.000183072 0.000124494 8 21 8 107788 107788 4794.78 299.674 0.01 0.00162656 0.00142678 564 862 -1 25 3 11 11 428 274 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0012549 0.00118367 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.15 vpr 64.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66232 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 21 100 23 56 21 64.7 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.9153e-05 3.219e-05 0.000324196 0.000258224 8 22 3 107788 107788 4794.78 299.674 0.01 0.00152952 0.00138796 564 862 -1 20 2 9 9 230 115 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00122034 0.00116368 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt index 755324715cf..6755b01d420 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 3.35 vpr 55.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 56776 10 10 253 263 1 169 87 11 11 121 clb auto 17.3 MiB 0.13 1270 55.4 MiB 0.08 0.00 5.46016 -69.6089 -5.46016 5.46016 0.17 0.000441019 0.000369117 0.0162387 0.0140536 13 1998 44 2.43e+06 2.01e+06 -1 -1 2.02 0.207776 0.184477 2006 27 1483 4679 322103 41342 9.23088 9.23088 -107.619 -9.23088 0 0 -1 -1 0.04 0.10 0.0296234 0.0264785 - k4_n4_v7_longline_bidir.xml styr.blif common 5.13 vpr 55.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 56964 10 10 253 263 1 169 87 11 11 121 clb auto 17.5 MiB 0.05 1274 55.6 MiB 0.05 0.00 5.85046 -74.2233 -5.85046 5.85046 0.23 0.000349213 0.000282966 0.0126593 0.0106736 18 2532 43 2.43e+06 2.01e+06 -1 -1 3.42 0.314676 0.279732 2435 43.7 2098 6378 540887 56511 9.2499 9.2499 -108.539 -9.2499 0 0 -1 -1 0.10 0.16 0.0389244 0.0344476 - k4_n4_v7_l1_bidir.xml styr.blif common 5.09 vpr 55.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 56976 10 10 253 263 1 169 87 11 11 121 clb auto 17.5 MiB 0.04 1314 55.6 MiB 0.07 0.00 7.03989 -83.5605 -7.03989 7.03989 0.23 0.000327368 0.000264148 0.0182445 0.0152593 11 1696 38 2.43e+06 2.01e+06 -1 -1 2.95 0.205017 0.182264 1347 23 1338 4185 371579 77951 8.29094 8.29094 -101.157 -8.29094 0 0 -1 -1 0.05 0.38 0.0324361 0.0292616 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 6.59 vpr 55.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 56664 10 10 253 263 1 169 87 11 11 121 clb auto 17.1 MiB 0.08 1338 55.3 MiB 0.14 0.00 6.19376 -68.5604 -6.19376 6.19376 1.18 0.000425619 0.000362908 0.0221479 0.0188897 16 2173 41 2.43e+06 2.01e+06 -1 -1 3.77 0.284495 0.251032 2120 27 1736 5578 1452395 185427 17.5032 17.5032 -220.236 -17.5032 0 0 -1 -1 0.05 0.32 0.0327982 0.0292008 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k4_n4_v7_bidir.xml styr.blif common 1.46 vpr 60.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61832 10 10 253 263 1 168 86 11 11 121 clb auto 22.0 MiB 0.03 1321 5000 862 3861 277 60.4 MiB 0.03 0.00 5.9335 -73.3937 -5.9335 5.9335 0.11 0.000247272 0.000211104 0.00802341 0.00702182 16 2231 44 2.43e+06 1.98e+06 -1 -1 0.80 0.100183 0.0859706 3522 30407 -1 1953 31 1359 4378 262510 29492 8.05167 8.05167 -93.2354 -8.05167 0 0 -1 -1 0.04 0.05 0.01 -1 -1 0.04 0.0184167 0.0164077 + k4_n4_v7_longline_bidir.xml styr.blif common 1.34 vpr 60.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61740 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1283 3299 376 2835 88 60.3 MiB 0.02 0.00 4.65232 -54.7485 -4.65232 4.65232 0.17 0.000255437 0.000220893 0.00609942 0.00538587 18 2324 34 2.43e+06 1.98e+06 -1 -1 0.49 0.0663873 0.0571989 3282 34431 -1 2358 20 1330 4111 330217 37900 9.15177 9.15177 -106.099 -9.15177 0 0 -1 -1 0.08 0.05 0.01 -1 -1 0.08 0.0143078 0.0127944 + k4_n4_v7_l1_bidir.xml styr.blif common 1.66 vpr 60.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61704 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1308 8591 1804 6310 477 60.3 MiB 0.05 0.00 7.13454 -91.9395 -7.13454 7.13454 0.16 0.000242373 0.000209231 0.012888 0.0113219 11 1687 50 2.43e+06 1.98e+06 -1 -1 0.84 0.0704665 0.0610222 4842 26197 -1 1434 21 1413 4826 393565 72389 8.93712 8.93712 -111.541 -8.93712 0 0 -1 -1 0.04 0.07 0.01 -1 -1 0.04 0.014159 0.0126913 + k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.73 vpr 60.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61704 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1271 3677 486 3031 160 60.3 MiB 0.03 0.00 3.40634 -44.4904 -3.40634 3.40634 0.11 0.000245519 0.000209021 0.00658945 0.00577606 16 2163 32 2.43e+06 1.98e+06 -1 -1 0.92 0.0663956 0.0571149 3522 30407 -1 2237 32 1642 5759 1828879 289403 29.985 29.985 -297.537 -29.985 0 0 -1 -1 0.04 0.21 0.01 -1 -1 0.04 0.0183895 0.0162618 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt index 31cfe86aeed..e20a70078a0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.41 vpr 62.15 MiB 0.03 6196 -1 -1 1 0.04 -1 -1 30096 -1 -1 3 9 0 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63640 9 8 71 66 1 35 20 5 5 25 clb auto 23.6 MiB 0.40 92 155 54 99 2 62.1 MiB 0.01 0.00 2.68643 -28.5255 -2.68643 2.68643 0.03 0.000279598 0.000259267 0.00285293 0.00269635 20 257 23 151211 75605.7 29112.5 1164.50 0.18 0.0562252 0.0490659 1812 4729 -1 263 19 256 334 13283 7093 3.63443 3.63443 -46.8377 -3.63443 0 0 37105.9 1484.24 0.00 0.02 0.01 -1 -1 0.00 0.0121492 0.0108578 14 17 16 6 0 0 -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.25 vpr 63.22 MiB 0.03 6356 -1 -1 1 0.03 -1 -1 30516 -1 -1 8 19 0 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64740 19 18 299 240 1 150 45 6 6 36 clb auto 24.8 MiB 2.60 509 3965 1656 2255 54 63.2 MiB 0.08 0.00 4.80824 -97.652 -4.80824 4.80824 0.07 0.00104469 0.00097299 0.0551095 0.0514421 50 1082 29 403230 201615 107229. 2978.57 0.47 0.240404 0.217708 3946 19047 -1 991 21 951 1468 70705 27211 5.13556 5.13556 -122.452 -5.13556 0 0 134937. 3748.26 0.01 0.08 0.03 -1 -1 0.01 0.0468224 0.0427605 62 82 85 13 0 0 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 0.81 vpr 65.85 MiB 0.01 6016 -1 -1 1 0.01 -1 -1 35776 -1 -1 3 9 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67428 9 8 71 66 1 35 20 5 5 25 clb auto 27.4 MiB 0.36 107 182 46 135 1 65.8 MiB 0.00 0.00 2.68643 -28.4013 -2.68643 2.68643 0.02 6.5012e-05 5.6766e-05 0.00123208 0.00115463 36 185 13 151211 75605.7 46719.2 1868.77 0.10 0.0225451 0.0190652 2052 7582 -1 146 10 108 137 4740 2447 2.68643 2.68643 -31.0287 -2.68643 0 0 57775.2 2311.01 0.00 0.01 0.01 -1 -1 0.00 0.00385153 0.00361726 14 17 16 6 0 0 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 2.78 vpr 66.76 MiB 0.01 6272 -1 -1 1 0.01 -1 -1 33876 -1 -1 8 19 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68364 19 18 299 240 1 150 45 6 6 36 clb auto 28.4 MiB 2.04 535 3885 1278 2560 47 66.8 MiB 0.03 0.00 4.80824 -97.5504 -4.80824 4.80824 0.04 0.000220352 0.000197239 0.013825 0.0125729 50 962 24 403230 201615 107229. 2978.57 0.20 0.0646538 0.0570817 3946 19047 -1 817 19 675 1076 42248 16898 5.14316 5.14316 -107.229 -5.14316 0 0 134937. 3748.26 0.01 0.02 0.01 -1 -1 0.01 0.0147259 0.0137101 62 82 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt index 2a065a016ec..f922c82810e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.59 vpr 55.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 56320 3 1 5 6 1 4 5 3 3 9 -1 auto 16.6 MiB 0.00 6 55.0 MiB 0.04 0.00 0.544641 -0.918653 -0.544641 0.544641 0.01 3.9125e-05 2.8457e-05 0.000157792 0.000118921 20 7 1 53894 53894 4880.82 542.314 0.06 0.000413799 0.000319707 7 1 3 3 40 30 0.681349 0.681349 -1.22599 -0.681349 0 0 6579.40 731.044 0.00 0.00 0.00014142 0.000113429 - k6_frac_N10_40nm.xml conn_order.eblif common 0.59 vpr 55.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 56388 2 1 4 5 1 3 4 3 3 9 -1 auto 16.7 MiB 0.02 4 55.1 MiB 0.00 0.00 0.709011 -1.25365 -0.709011 0.709011 0.00 9.832e-06 5.802e-06 7.9521e-05 5.5913e-05 20 10 1 53894 53894 4880.82 542.314 0.06 0.000293122 0.000221721 18 2 3 3 70 58 1.93748 1.93748 -2.483 -1.93748 0 0 6579.40 731.044 0.00 0.00 0.000162407 0.000131918 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml test_eblif.eblif common 0.12 vpr 59.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61424 3 1 5 6 1 4 5 3 3 9 -1 auto 21.5 MiB 0.00 9 12 1 9 2 60.0 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.035e-05 7.094e-06 8.8915e-05 6.9209e-05 20 10 1 53894 53894 4880.82 542.314 0.00 0.0011057 0.00104635 379 725 -1 6 1 3 3 36 25 0.605178 0.605178 -1.1507 -0.605178 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00105006 0.00102258 + k6_frac_N10_40nm.xml conn_order.eblif common 0.12 vpr 59.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61424 2 1 4 5 1 3 4 3 3 9 -1 auto 21.5 MiB 0.00 6 9 2 3 4 60.0 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0129e-05 6.963e-06 0.000104936 8.568e-05 20 9 1 53894 53894 4880.82 542.314 0.00 0.00111784 0.00105927 379 725 -1 5 1 2 2 25 19 0.940178 0.940178 -1.48482 -0.940178 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00106769 0.00103834 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt index 53e1a99cf04..377804dd2e9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 4.02 vpr 61.07 MiB 0.13 10072 -1 -1 4 0.16 -1 -1 33252 -1 -1 19 11 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 62540 11 30 262 292 2 104 60 7 7 49 clb auto 22.4 MiB 0.17 491 61.1 MiB 0.14 0.00 2.22129 -174.848 -2.22129 2.12256 0.08 0.000609229 0.000514776 0.0130362 0.0113054 30 570 24 1.07788e+06 1.02399e+06 77018.1 1571.80 1.53 0.218794 0.187902 537 22 693 1872 55819 14529 2.35993 2.22897 -183.816 -2.35993 0 0 90369.8 1844.28 0.02 0.10 0.0321781 0.0283564 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_N10_mem32K_40nm.xml stereovision3.v common 1.27 vpr 66.64 MiB 0.03 9984 -1 -1 4 0.11 -1 -1 40356 -1 -1 19 11 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68240 11 30 262 292 2 104 60 7 7 49 clb auto 27.9 MiB 0.04 534 1698 67 1561 70 66.6 MiB 0.02 0.00 2.46229 -183.132 -2.46229 2.30786 0.05 0.000271357 0.000227515 0.00621294 0.00543836 20 762 38 1.07788e+06 1.02399e+06 49980.0 1020.00 0.44 0.121211 0.10048 2664 9102 -1 658 40 1163 2905 97572 29592 2.48064 2.28958 -187.312 -2.48064 0 0 65453.8 1335.79 0.01 0.05 0.01 -1 -1 0.01 0.0255642 0.0220947 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt index 47383439114..14c7bba32a0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack -k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.38001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.86636 -1 -1 -1 -1 + arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack + k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.75805 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.48832 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt index 41c7144623e..7dfb524615c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.25 vpr 60.06 MiB -1 -1 -1 -1 0 0.01 -1 -1 35524 -1 -1 1 0 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61504 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.7 MiB 0.00 0 3 0 0 3 60.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1792e-05 6.462e-06 6.4199e-05 4.1558e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.000986802 0.000936159 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.00107673 0.00105237 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.25 vpr 60.17 MiB -1 -1 -1 -1 0 0.01 -1 -1 33504 -1 -1 1 0 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61616 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.9 MiB 0.00 0 3 0 0 3 60.2 MiB 0.00 0.00 nan 0 0 nan 0.00 7.223e-06 3.386e-06 5.5544e-05 3.5597e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.00104462 0.000996112 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.00102398 0.00100141 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.26 vpr 60.27 MiB -1 -1 -1 -1 0 0.01 -1 -1 35216 -1 -1 1 0 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61712 6 1 1 8 0 1 8 3 3 9 -1 auto 21.9 MiB 0.00 0 21 0 11 10 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1832e-05 6.422e-06 6.8768e-05 4.5464e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.00111165 0.00105707 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.00103287 0.00100779 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.25 vpr 59.99 MiB -1 -1 -1 -1 0 0.01 -1 -1 33352 -1 -1 1 0 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61428 6 1 1 8 0 1 8 3 3 9 -1 auto 21.7 MiB 0.00 0 21 0 11 10 60.0 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2823e-05 7.594e-06 6.6002e-05 4.2891e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.0010424 0.000992474 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.00105499 0.00103003 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.26 vpr 60.32 MiB -1 -1 -1 -1 1 0.01 -1 -1 33504 -1 -1 1 2 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61768 2 1 3 4 0 3 4 3 3 9 -1 auto 22.0 MiB 0.00 6 9 6 0 3 60.3 MiB 0.00 0.00 0.442454 -0.442454 -0.442454 nan 0.00 1.4918e-05 1.035e-05 8.2565e-05 6.0664e-05 16 16 1 3900 3900 3970.02 441.113 0.00 0.00108317 0.00102338 330 691 -1 5 1 3 3 44 29 0.584298 nan -0.584298 -0.584298 0 0 4445.42 493.935 0.00 0.00 0.00 -1 -1 0.00 0.00105978 0.00103527 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.32 vpr 60.22 MiB -1 -1 -1 -1 2 0.02 -1 -1 36244 -1 -1 1 5 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61664 5 1 7 8 0 7 7 3 3 9 -1 auto 21.7 MiB 0.00 14 18 14 0 4 60.2 MiB 0.00 0.00 0.701708 -0.701708 -0.701708 nan 0.00 2.0078e-05 1.5019e-05 0.000109954 8.6812e-05 18 17 4 3900 3900 4264.82 473.869 0.01 0.00238524 0.0020074 346 735 -1 23 7 18 18 645 512 1.38908 nan -1.38908 -1.38908 0 0 5011.22 556.802 0.00 0.00 0.00 -1 -1 0.00 0.00126509 0.00119902 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.33 vpr 60.43 MiB -1 -1 -1 -1 2 0.03 -1 -1 35480 -1 -1 1 5 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61884 5 1 7 8 0 7 7 3 3 9 -1 auto 22.0 MiB 0.00 14 18 14 0 4 60.4 MiB 0.00 0.00 0.701708 -0.701708 -0.701708 nan 0.00 2.0539e-05 1.5179e-05 0.000110768 8.7184e-05 16 33 14 3900 3900 3970.02 441.113 0.01 0.00242647 0.00192982 330 691 -1 19 2 10 10 257 200 1.34631 nan -1.34631 -1.34631 0 0 4445.42 493.935 0.00 0.00 0.00 -1 -1 0.00 0.00114846 0.00111124 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.24 vpr 60.05 MiB -1 -1 -1 -1 1 0.01 -1 -1 35644 -1 -1 1 3 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61496 3 1 5 6 1 4 5 3 3 9 -1 auto 21.6 MiB 0.00 6 12 9 0 3 60.1 MiB 0.00 0.00 0.274843 -0.535084 -0.274843 0.274843 0.00 1.1191e-05 7.554e-06 8.3676e-05 6.3398e-05 16 9 1 3900 3900 3970.02 441.113 0.00 0.00132447 0.00126222 330 691 -1 13 1 3 3 102 86 0.776991 0.776991 -1.10653 -0.776991 0 0 4445.42 493.935 0.00 0.00 0.00 -1 -1 0.00 0.00109442 0.00106652 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.32 vpr 60.20 MiB -1 -1 -1 -1 1 0.02 -1 -1 37004 -1 -1 1 3 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61648 4 1 4 6 0 4 6 3 3 9 -1 auto 21.6 MiB 0.00 8 15 12 0 3 60.2 MiB 0.00 0.00 0.442454 -0.442454 -0.442454 nan 0.00 1.3374e-05 9.718e-06 8.5095e-05 6.547e-05 12 12 16 3900 3900 2582.62 286.957 0.00 0.00124048 0.00110968 314 651 -1 21 18 48 48 1944 1648 1.35187 nan -1.35187 -1.35187 0 0 3970.02 441.113 0.00 0.00 0.00 -1 -1 0.00 0.0013361 0.00122949 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.24 vpr 60.29 MiB -1 -1 -1 -1 1 0.02 -1 -1 36440 -1 -1 1 4 0 0 exited with return code 2 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61736 4 4 8 12 0 8 9 3 3 9 -1 auto 22.0 MiB 0.00 17 27 23 0 4 60.3 MiB 0.00 0.00 0.442454 -1.76982 -0.442454 nan 0.00 1.7762e-05 1.3585e-05 0.000130011 0.000108712 20 47 35 3900 3900 4445.42 493.935 0.02 0.00339966 0.00274979 354 763 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00 0.00 0.00 -1 -1 0.00 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 0.48 vpr 60.08 MiB -1 -1 -1 -1 3 0.03 -1 -1 37308 -1 -1 3 6 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61520 6 6 28 34 0 28 15 5 5 25 clb auto 21.9 MiB 0.01 90 51 15 36 0 60.1 MiB 0.00 0.00 1.22109 -5.53991 -1.22109 nan 0.03 6.3148e-05 5.4311e-05 0.000386322 0.000350895 24 254 25 23400 11700 20975.0 838.999 0.08 0.00696126 0.00582132 1420 4462 -1 216 19 282 1073 50844 22544 1.69944 nan -7.59202 -1.69944 0 0 27052.1 1082.08 0.01 0.01 0.01 -1 -1 0.01 0.00293744 0.00261428 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.48 vpr 60.29 MiB -1 -1 -1 -1 4 0.03 -1 -1 39272 -1 -1 5 7 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61736 7 8 39 47 0 39 20 5 5 25 clb auto 22.1 MiB 0.01 154 74 17 50 7 60.3 MiB 0.00 0.00 1.54677 -7.86002 -1.54677 nan 0.03 7.8106e-05 6.8328e-05 0.000479808 0.00043804 28 373 19 23400 19500 25328.9 1013.15 0.08 0.00821967 0.00689891 1476 4870 -1 293 15 297 1224 65830 28477 1.87564 nan -9.87124 -1.87564 0 0 29680.9 1187.23 0.01 0.01 0.00 -1 -1 0.01 0.00311026 0.00278813 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 0.67 vpr 60.58 MiB -1 -1 -1 -1 8 0.04 -1 -1 39760 -1 -1 7 8 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 62032 8 8 51 59 0 51 23 6 6 36 clb auto 22.4 MiB 0.01 199 503 80 409 14 60.6 MiB 0.00 0.00 2.62874 -12.7894 -2.62874 nan 0.05 6.1655e-05 5.368e-05 0.00137631 0.00121424 30 525 22 165600 27300 47960.3 1332.23 0.17 0.010967 0.00928284 2708 10880 -1 452 24 556 2354 174839 65799 2.99786 nan -15.0511 -2.99786 0 0 61410.5 1705.85 0.01 0.03 0.01 -1 -1 0.01 0.00447446 0.00394186 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.90 vpr 61.03 MiB -1 -1 -1 -1 7 0.05 -1 -1 39892 -1 -1 11 10 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 62496 10 10 95 105 0 95 31 6 6 36 clb auto 22.7 MiB 0.01 422 703 104 550 49 61.0 MiB 0.01 0.00 2.54568 -18.0554 -2.54568 nan 0.05 0.000120846 0.000105778 0.00257269 0.00230638 38 1016 43 165600 42900 55946.4 1554.07 0.34 0.0267713 0.0228448 2940 12782 -1 946 20 922 3803 273492 99044 3.06944 nan -22.1272 -3.06944 0 0 73011.6 2028.10 0.02 0.04 0.01 -1 -1 0.02 0.00607893 0.00542262 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 0.91 vpr 60.85 MiB -1 -1 -1 -1 8 0.05 -1 -1 37544 -1 -1 11 11 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 62308 11 11 94 105 0 94 33 6 6 36 clb auto 22.5 MiB 0.01 404 553 74 451 28 60.8 MiB 0.01 0.00 2.82749 -21.0904 -2.82749 nan 0.05 0.000104234 9.1761e-05 0.00178771 0.00161138 40 986 26 165600 42900 61410.5 1705.85 0.34 0.0258843 0.0220673 2992 13730 -1 815 20 778 3303 237045 85863 3.17197 nan -25.3563 -3.17197 0 0 78756.9 2187.69 0.02 0.04 0.01 -1 -1 0.02 0.00616558 0.00552361 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_1bit.blif common 0.32 vpr 60.05 MiB -1 -1 -1 -1 1 0.02 -1 -1 36636 -1 -1 1 3 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61492 3 2 5 7 0 5 6 3 3 9 -1 auto 21.6 MiB 0.00 10 15 13 0 2 60.1 MiB 0.00 0.00 0.442454 -0.884909 -0.442454 nan 0.00 2.0539e-05 1.4958e-05 0.000108302 8.3475e-05 16 34 14 3900 3900 3970.02 441.113 0.01 0.00224157 0.00177215 330 691 -1 20 11 27 52 1186 813 0.949678 nan -1.54241 -0.949678 0 0 4445.42 493.935 0.00 0.00 0.00 -1 -1 0.00 0.0012629 0.00116855 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.31 vpr 60.18 MiB -1 -1 -1 -1 2 0.02 -1 -1 38892 -1 -1 1 5 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61624 5 3 9 12 0 9 9 3 3 9 -1 auto 21.7 MiB 0.00 18 27 24 0 3 60.2 MiB 0.00 0.00 0.701708 -1.84587 -0.701708 nan 0.00 1.7322e-05 1.3325e-05 0.000129361 0.000107621 22 35 5 3900 3900 4723.42 524.824 0.01 0.0024112 0.00198258 362 917 -1 25 17 47 91 2429 1590 1.0399 nan -2.61167 -1.0399 0 0 5935.82 659.535 0.00 0.00 0.00 -1 -1 0.00 0.00151202 0.0013796 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.32 vpr 60.13 MiB -1 -1 -1 -1 3 0.02 -1 -1 38128 -1 -1 1 7 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61576 7 4 13 17 0 13 12 3 3 9 -1 auto 21.7 MiB 0.00 26 38 34 0 4 60.1 MiB 0.00 0.00 0.960961 -3.06608 -0.960961 nan 0.00 2.158e-05 1.7212e-05 0.000165469 0.000142686 24 51 12 3900 3900 5011.22 556.802 0.02 0.00299239 0.00246489 378 957 -1 37 12 67 122 3797 2662 1.24647 nan -4.03744 -1.24647 0 0 6337.42 704.157 0.00 0.00 0.00 -1 -1 0.00 0.00155838 0.00144321 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.32 vpr 60.37 MiB -1 -1 -1 -1 4 0.03 -1 -1 39548 -1 -1 1 9 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61820 9 5 17 22 0 17 15 3 3 9 -1 auto 22.1 MiB 0.00 34 51 43 0 8 60.4 MiB 0.00 0.00 1.22021 -4.54555 -1.22021 nan 0.00 2.5308e-05 2.0559e-05 0.000199995 0.00017644 28 61 16 3900 3900 5935.82 659.535 0.02 0.00359559 0.00298152 394 1003 -1 60 13 79 151 4295 2818 1.86531 nan -6.32901 -1.86531 0 0 6854.42 761.602 0.00 0.00 0.00 -1 -1 0.00 0.00171244 0.00158046 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.38 vpr 60.21 MiB -1 -1 -1 -1 4 0.03 -1 -1 39740 -1 -1 2 11 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61652 11 6 24 30 0 24 19 4 4 16 clb auto 21.7 MiB 0.00 68 69 19 41 9 60.2 MiB 0.00 0.00 1.41045 -6.83425 -1.41045 nan 0.01 3.3762e-05 2.7691e-05 0.00027376 0.000243675 26 204 43 7800 7800 10971.4 685.715 0.04 0.00648411 0.00535478 796 2220 -1 157 18 215 493 23096 12686 1.78697 nan -8.42412 -1.78697 0 0 14062.4 878.902 0.00 0.01 0.00 -1 -1 0.00 0.00229668 0.00204194 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.23 vpr 62.12 MiB -1 -1 -1 -1 0 0.01 -1 -1 33488 -1 -1 1 0 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 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52 0.411504 0.411504 -0.743397 -0.411504 0 0 4264.82 473.869 0.00 0.00 0.00 -1 -1 0.00 0.00101855 0.000992124 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.28 vpr 62.14 MiB -1 -1 -1 -1 1 0.02 -1 -1 35792 -1 -1 1 3 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63628 4 1 4 6 0 4 6 3 3 9 -1 auto 23.8 MiB 0.00 12 15 5 4 6 62.1 MiB 0.00 0.00 0.442454 -0.442454 -0.442454 nan 0.00 1.8294e-05 1.3074e-05 8.2594e-05 6.1684e-05 12 10 13 3900 3900 2582.62 286.957 0.00 0.00129752 0.00116274 314 651 -1 5 1 4 4 82 62 0.529227 nan -0.529227 -0.529227 0 0 3970.02 441.113 0.00 0.00 0.00 -1 -1 0.00 0.000989778 0.000966254 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.21 vpr 62.05 MiB -1 -1 -1 -1 1 0.02 -1 -1 36024 -1 -1 1 4 0 0 exited with return code 2 e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63540 4 4 8 12 0 8 9 3 3 9 -1 auto 23.8 MiB 0.00 25 27 10 13 4 62.1 MiB 0.00 0.00 0.442454 -1.76982 -0.442454 nan 0.00 1.5989e-05 1.2313e-05 0.000135973 0.000114855 20 42 18 3900 3900 4445.42 493.935 0.01 0.00271823 0.00218574 354 763 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00 0.00 0.00 -1 -1 0.00 -1 -1 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 0.45 vpr 62.33 MiB -1 -1 -1 -1 3 0.03 -1 -1 37348 -1 -1 3 6 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63824 6 6 28 34 0 28 15 5 5 25 clb auto 23.9 MiB 0.00 103 51 16 35 0 62.3 MiB 0.00 0.00 1.20682 -5.54363 -1.20682 nan 0.03 6.5532e-05 5.6345e-05 0.000362477 0.000328062 24 291 50 23400 11700 20975.0 838.999 0.09 0.00842523 0.00696631 1420 4462 -1 203 23 273 1147 57568 24503 1.79815 nan -7.13942 -1.79815 0 0 27052.1 1082.08 0.01 0.01 0.00 -1 -1 0.01 0.00303588 0.00269461 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.46 vpr 62.28 MiB -1 -1 -1 -1 4 0.03 -1 -1 38016 -1 -1 5 7 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63776 7 8 39 47 0 39 20 5 5 25 clb auto 23.8 MiB 0.01 166 236 55 168 13 62.3 MiB 0.00 0.00 1.53492 -7.68167 -1.53492 nan 0.03 6.2787e-05 5.5644e-05 0.000904391 0.000813461 28 390 19 23400 19500 25328.9 1013.15 0.09 0.00844921 0.00711013 1476 4870 -1 345 18 424 1625 97221 41104 2.1436 nan -10.1282 -2.1436 0 0 29680.9 1187.23 0.01 0.02 0.00 -1 -1 0.01 0.00324908 0.00290646 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 0.92 vpr 62.48 MiB -1 -1 -1 -1 8 0.04 -1 -1 38280 -1 -1 7 8 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63976 8 8 51 59 0 51 23 6 6 36 clb auto 24.1 MiB 0.01 218 87 23 62 2 62.5 MiB 0.00 0.00 2.65232 -12.8401 -2.65232 nan 0.05 0.00010712 9.623e-05 0.000592006 0.000547633 28 635 50 165600 27300 45013.2 1250.37 0.45 0.0231976 0.0192994 2604 9324 -1 531 20 525 2156 148800 55475 3.2769 nan -17.2194 -3.2769 0 0 53593.6 1488.71 0.01 0.02 0.01 -1 -1 0.01 0.00401954 0.00358337 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.96 vpr 62.47 MiB -1 -1 -1 -1 7 0.05 -1 -1 38160 -1 -1 11 10 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63972 10 10 95 105 0 95 31 6 6 36 clb auto 24.0 MiB 0.01 458 607 80 489 38 62.5 MiB 0.01 0.00 2.54057 -18.2603 -2.54057 nan 0.05 0.000103744 8.9057e-05 0.00195849 0.0017585 38 1072 47 165600 42900 55946.4 1554.07 0.41 0.0295403 0.0251736 2940 12782 -1 863 20 990 4097 286923 104030 2.92618 nan -21.5852 -2.92618 0 0 73011.6 2028.10 0.02 0.04 0.01 -1 -1 0.02 0.00612337 0.00548198 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 0.98 vpr 62.71 MiB -1 -1 -1 -1 8 0.05 -1 -1 40416 -1 -1 11 11 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64216 11 11 94 105 0 94 33 6 6 36 clb auto 24.2 MiB 0.01 429 657 85 535 37 62.7 MiB 0.01 0.00 2.9648 -21.4457 -2.9648 nan 0.05 0.000161302 0.000148878 0.00224002 0.00203969 40 1112 36 165600 42900 61410.5 1705.85 0.42 0.0287244 0.0244922 2992 13730 -1 884 19 850 3542 252924 89086 3.47123 nan -25.0388 -3.47123 0 0 78756.9 2187.69 0.02 0.04 0.01 -1 -1 0.02 0.0059244 0.00528593 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_1bit.blif common 0.28 vpr 62.14 MiB -1 -1 -1 -1 1 0.02 -1 -1 38728 -1 -1 1 3 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63628 3 2 5 7 0 5 6 3 3 9 -1 auto 23.8 MiB 0.00 15 15 8 4 3 62.1 MiB 0.00 0.00 0.442454 -0.884909 -0.442454 nan 0.00 1.9005e-05 1.4186e-05 0.000116908 9.2382e-05 16 26 17 3900 3900 3970.02 441.113 0.01 0.00138483 0.00123021 330 691 -1 24 12 34 59 1656 1302 0.897144 nan -1.78596 -0.897144 0 0 4445.42 493.935 0.00 0.00 0.00 -1 -1 0.00 0.00126285 0.0011792 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.31 vpr 62.17 MiB -1 -1 -1 -1 2 0.02 -1 -1 37736 -1 -1 1 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63660 5 3 9 12 0 9 9 3 3 9 -1 auto 23.6 MiB 0.00 26 27 10 10 7 62.2 MiB 0.00 0.00 0.701708 -1.84587 -0.701708 nan 0.00 2.9094e-05 2.3013e-05 0.000162313 0.000137477 20 41 14 3900 3900 4445.42 493.935 0.03 0.00470101 0.00358969 354 763 -1 62 23 83 142 5466 4364 2.28942 nan -4.87234 -2.28942 0 0 5185.22 576.135 0.00 0.00 0.00 -1 -1 0.00 0.00167993 0.00148994 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.30 vpr 62.08 MiB -1 -1 -1 -1 3 0.02 -1 -1 37368 -1 -1 1 7 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63572 7 4 13 17 0 13 12 3 3 9 -1 auto 23.6 MiB 0.00 37 38 21 15 2 62.1 MiB 0.00 0.00 0.960961 -3.06608 -0.960961 nan 0.00 3.4835e-05 2.8744e-05 0.00021968 0.000193231 24 55 20 3900 3900 5011.22 556.802 0.02 0.0034395 0.00281572 378 957 -1 47 16 74 136 4091 2875 1.45584 nan -4.58947 -1.45584 0 0 6337.42 704.157 0.00 0.00 0.00 -1 -1 0.00 0.00168199 0.00150036 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.30 vpr 62.23 MiB -1 -1 -1 -1 4 0.03 -1 -1 37876 -1 -1 1 9 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63728 9 5 17 22 0 17 15 3 3 9 -1 auto 23.8 MiB 0.00 48 51 31 11 9 62.2 MiB 0.00 0.00 1.22021 -4.54555 -1.22021 nan 0.00 2.4027e-05 1.9828e-05 0.000203142 0.000178704 28 55 17 3900 3900 5935.82 659.535 0.01 0.00360742 0.00299184 394 1003 -1 58 13 87 148 4928 3501 1.86558 nan -6.3789 -1.86558 0 0 6854.42 761.602 0.00 0.00 0.00 -1 -1 0.00 0.00173866 0.00159953 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.39 vpr 62.16 MiB -1 -1 -1 -1 4 0.03 -1 -1 39264 -1 -1 2 11 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63652 11 6 24 30 0 24 19 4 4 16 clb auto 23.8 MiB 0.00 85 69 11 46 12 62.2 MiB 0.00 0.00 1.38419 -6.92615 -1.38419 nan 0.01 3.5296e-05 2.8123e-05 0.000285254 0.000254216 28 127 18 7800 7800 12557.4 784.840 0.07 0.00805822 0.00657388 812 2356 -1 155 18 208 453 20911 11455 1.85994 nan -8.56093 -1.85994 0 0 14986.4 936.652 0.00 0.01 0.00 -1 -1 0.00 0.00224724 0.00199391 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt index 04bb7d6ed48..754f7bd66a7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.47 vpr 66.59 MiB 0.03 9472 -1 -1 3 0.19 -1 -1 41836 -1 -1 65 99 1 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68184 99 130 363 493 1 251 295 12 12 144 clb auto 28.2 MiB 0.06 692 72889 28414 34489 9986 66.6 MiB 0.14 0.00 2.09877 -218.426 -2.09877 2.09877 0.25 0.000413152 0.000375281 0.0341832 0.0311622 54 1564 14 5.66058e+06 4.05111e+06 434679. 3018.61 0.66 0.126834 0.116786 13954 85374 -1 1453 9 525 650 57104 18407 2.36354 2.36354 -230.826 -2.36354 0 0 565229. 3925.20 0.14 0.02 0.06 -1 -1 0.14 0.0147228 0.0139818 0.009881 0.2313 0.07478 0.694 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 9.39 vpr 70.25 MiB 0.02 9472 -1 -1 15 0.26 -1 -1 39552 -1 -1 36 162 0 5 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 71936 162 96 999 932 1 693 299 16 16 256 mult_36 auto 32.4 MiB 0.21 5381 78221 22147 49025 7049 70.2 MiB 0.37 0.01 21.4844 -2025.35 -21.4844 21.4844 0.50 0.00135972 0.00124471 0.11653 0.107638 46 11847 29 1.21132e+07 3.92018e+06 727248. 2840.81 5.46 0.623277 0.577661 24972 144857 -1 9693 15 3048 5938 1889606 467681 23.0556 23.0556 -2225.33 -23.0556 0 0 934704. 3651.19 0.25 0.30 0.09 -1 -1 0.25 0.0669453 0.0637089 0.007698 0.3453 0.01633 0.6384 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.50 vpr 68.70 MiB 0.02 9472 -1 -1 3 0.19 -1 -1 41960 -1 -1 65 99 1 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 70352 99 130 363 493 1 251 295 12 12 144 clb auto 29.6 MiB 0.06 898 69946 27423 33815 8708 68.7 MiB 0.13 0.00 2.13689 -217.073 -2.13689 2.13689 0.25 0.000441485 0.000392594 0.0339038 0.0310413 36 2034 32 5.66058e+06 4.05111e+06 305235. 2119.69 1.78 0.210292 0.192855 12238 58442 -1 1635 12 651 842 57285 18015 2.34804 2.34804 -239.539 -2.34804 0 0 378970. 2631.74 0.10 0.03 0.04 -1 -1 0.10 0.016856 0.0159728 0.009514 0.2103 0.06439 0.7253 + k6_frac_N10_mem32K_40nm.xml diffeq1.v common 9.47 vpr 71.95 MiB 0.02 9472 -1 -1 15 0.26 -1 -1 41080 -1 -1 36 162 0 5 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 73680 162 96 999 932 1 690 299 16 16 256 mult_36 auto 32.8 MiB 0.23 5760 83216 27007 49519 6690 72.0 MiB 0.41 0.01 21.4984 -1890.69 -21.4984 21.4984 0.50 0.00137404 0.00127093 0.126092 0.1166 50 12109 34 1.21132e+07 3.92018e+06 780512. 3048.87 5.57 0.718313 0.665768 25484 153448 -1 9957 18 3267 6461 977570 257843 22.4842 22.4842 -2053.42 -22.4842 0 0 1.00276e+06 3917.05 0.27 0.19 0.09 -1 -1 0.27 0.0733674 0.0696001 0.007924 0.3531 0.0162 0.6307 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt index 1c233e57be8..3ff8dccb714 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.16 vpr 62.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64436 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 16 30 11 13 6 62.9 MiB 0.00 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 3.2409e-05 2.4445e-05 0.000164415 0.000132236 8 18 2 107788 107788 4794.78 299.674 0.01 0.001307 0.00120255 564 862 -1 27 4 14 14 480 275 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00128885 0.00121127 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.16 vpr 62.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64216 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.00 19 30 6 15 9 62.7 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.0537e-05 2.4065e-05 0.000157033 0.000130242 8 27 4 107788 107788 4794.78 299.674 0.01 0.00133748 0.00121419 564 862 -1 25 5 14 14 513 315 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00127297 0.00120378 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.16 vpr 62.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64140 5 3 11 14 2 9 10 4 4 16 clb auto 24.4 MiB 0.00 16 30 10 18 2 62.6 MiB 0.00 0.00 0.645499 -2.18826 -0.645499 0.571 0.01 3.9203e-05 2.6359e-05 0.000188933 0.0001445 8 17 3 107788 107788 4794.78 299.674 0.01 0.00139901 0.00126265 564 862 -1 14 4 15 15 278 103 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00133269 0.00124763 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.16 vpr 62.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64168 5 3 11 14 2 9 10 4 4 16 clb auto 24.4 MiB 0.00 16 30 12 17 1 62.7 MiB 0.00 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 2.6309e-05 1.6771e-05 0.000166579 0.000121265 8 19 8 107788 107788 4794.78 299.674 0.01 0.00153747 0.00134782 564 862 -1 15 2 8 8 148 67 1.57153 0.571 -4.92067 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0012472 0.00118244 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.16 vpr 62.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64292 5 3 11 14 2 9 10 4 4 16 clb auto 24.4 MiB 0.00 18 30 12 15 3 62.8 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 2.6059e-05 1.7653e-05 0.000167302 0.000126966 8 17 8 107788 107788 4794.78 299.674 0.01 0.00155096 0.00137177 564 862 -1 14 2 10 10 171 80 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00123638 0.00117557 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.16 vpr 62.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 8f82416 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1022-azure x86_64 2024-07-02T00:42:56 fv-az891-246 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64228 5 3 11 14 2 9 10 4 4 16 clb auto 24.4 MiB 0.00 18 30 13 7 10 62.7 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.8091e-05 2.7331e-05 0.000183163 0.000144511 8 23 2 107788 107788 4794.78 299.674 0.01 0.00134658 0.00123722 564 862 -1 23 2 8 8 193 92 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00125079 0.00119331 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.15 vpr 64.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66040 5 3 11 14 2 9 10 4 4 16 clb auto 26.1 MiB 0.00 22 30 9 14 7 64.5 MiB 0.00 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 3.4514e-05 2.6389e-05 0.000188251 0.000157435 8 18 2 107788 107788 4794.78 299.674 0.01 0.00136356 0.00126067 564 862 -1 18 4 10 10 213 96 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00132991 0.0012563 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.15 vpr 64.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66172 5 3 11 14 2 9 10 4 4 16 clb auto 26.2 MiB 0.00 23 30 5 16 9 64.6 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.1699e-05 2.5357e-05 0.000167513 0.000139209 8 29 4 107788 107788 4794.78 299.674 0.01 0.00129724 0.00119452 564 862 -1 25 4 15 15 546 342 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00123336 0.00115491 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.15 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66304 5 3 11 14 2 9 10 4 4 16 clb auto 26.5 MiB 0.00 20 30 10 18 2 64.8 MiB 0.00 0.00 0.645499 -2.18826 -0.645499 0.571 0.01 5.5523e-05 4.2379e-05 0.000203498 0.000159839 8 17 3 107788 107788 4794.78 299.674 0.01 0.0014548 0.0013129 564 862 -1 14 4 15 15 278 103 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00123664 0.00115953 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.15 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66308 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 20 30 11 18 1 64.8 MiB 0.00 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 2.4636e-05 1.5899e-05 0.000174577 0.000131877 8 17 8 107788 107788 4794.78 299.674 0.01 0.00153355 0.00133955 564 862 -1 15 8 21 21 322 143 1.57153 0.571 -4.91875 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00136833 0.00125557 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.16 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66300 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 21 30 10 15 5 64.7 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 2.8303e-05 1.9276e-05 0.000183072 0.000124494 8 21 8 107788 107788 4794.78 299.674 0.01 0.00162656 0.00142678 564 862 -1 25 3 11 11 428 274 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0012549 0.00118367 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.15 vpr 64.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66232 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 21 100 23 56 21 64.7 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.9153e-05 3.219e-05 0.000324196 0.000258224 8 22 3 107788 107788 4794.78 299.674 0.01 0.00152952 0.00138796 564 862 -1 20 2 9 9 230 115 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00122034 0.00116368 From 451b92902569ef2cd871e14bd78a7532c95765fa Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Tue, 24 Sep 2024 18:23:25 -0400 Subject: [PATCH 12/16] use integer indices in vtr::NdOffsetMatrix to enable using negative indices --- libs/libvtrutil/src/vtr_ndoffsetmatrix.h | 64 ++++++++++++------------ 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/libs/libvtrutil/src/vtr_ndoffsetmatrix.h b/libs/libvtrutil/src/vtr_ndoffsetmatrix.h index c4255303866..f65da2908b9 100644 --- a/libs/libvtrutil/src/vtr_ndoffsetmatrix.h +++ b/libs/libvtrutil/src/vtr_ndoffsetmatrix.h @@ -10,7 +10,7 @@ namespace vtr { /** * @brief A half-open range specification for a matrix dimension [begin_index, last_index) * - * It comes with valid indicies from [begin_index() ... end_index()-1], provided size() > 0. + * It comes with valid indices from [begin_index() ... end_index()-1], provided size() > 0. */ class DimRange { public: @@ -18,22 +18,22 @@ class DimRange { DimRange() = default; ///@brief a constructor with begin_index, end_index - DimRange(size_t begin, size_t end) + DimRange(int begin, int end) : begin_index_(begin) , end_index_(end) {} ///@brief Return the begin index - size_t begin_index() const { return begin_index_; } + int begin_index() const { return begin_index_; } ///@brief Return the end index - size_t end_index() const { return end_index_; } + int end_index() const { return end_index_; } ///@brief Return the size size_t size() const { return end_index_ - begin_index_; } private: - size_t begin_index_ = 0; - size_t end_index_ = 0; + int begin_index_ = 0; + int end_index_ = 0; }; /** @@ -69,7 +69,7 @@ class NdOffsetMatrixProxy { , start_(start) {} ///@brief const [] operator - const NdOffsetMatrixProxy operator[](size_t index) const { + const NdOffsetMatrixProxy operator[](int index) const { VTR_ASSERT_SAFE_MSG(index >= dim_ranges_[idim_].begin_index(), "Index out of range (below dimension minimum)"); VTR_ASSERT_SAFE_MSG(index < dim_ranges_[idim_].end_index(), "Index out of range (above dimension maximum)"); @@ -79,10 +79,10 @@ class NdOffsetMatrixProxy { * The elements are stored in zero-indexed form, so we need to adjust * for any non-zero minimum index */ - size_t effective_index = index - dim_ranges_[idim_].begin_index(); + int effective_index = index - dim_ranges_[idim_].begin_index(); //Determine the stride of the next dimension - size_t next_dim_stride = dim_stride_ / dim_ranges_[idim_ + 1].size(); + int next_dim_stride = dim_stride_ / dim_ranges_[idim_ + 1].size(); //Strip off one dimension return NdOffsetMatrixProxy(dim_ranges_, //Pass the dimension information @@ -92,7 +92,7 @@ class NdOffsetMatrixProxy { } ///@brief [] operator - NdOffsetMatrixProxy operator[](size_t index) { + NdOffsetMatrixProxy operator[](int index) { //Call the const version and cast-away constness return const_cast*>(this)->operator[](index); } @@ -122,21 +122,21 @@ class NdOffsetMatrixProxy { , start_(start) {} ///@brief const [] operator - const T& operator[](size_t index) const { + const T& operator[](int index) const { VTR_ASSERT_SAFE_MSG(dim_stride_ == 1, "Final dimension must have stride 1"); VTR_ASSERT_SAFE_MSG(index >= dim_ranges_[idim_].begin_index(), "Index out of range (below dimension minimum)"); VTR_ASSERT_SAFE_MSG(index < dim_ranges_[idim_].end_index(), "Index out of range (above dimension maximum)"); //The elements are stored in zero-indexed form, so we need to adjust //for any non-zero minimum index - size_t effective_index = index - dim_ranges_[idim_].begin_index(); + int effective_index = index - dim_ranges_[idim_].begin_index(); //Base case return start_[effective_index]; } ///@brief [] operator - T& operator[](size_t index) { + T& operator[](int index) { //Call the const version and cast-away constness return const_cast(const_cast*>(this)->operator[](index)); } @@ -163,7 +163,7 @@ class NdOffsetMatrixProxy { * This should improve memory usage (no extra pointers to store for each dimension), * and cache locality (less indirection via pointers, predictable strides). * - * The indicies are calculated based on the dimensions to access the appropriate elements. + * The indices are calculated based on the dimensions to access the appropriate elements. * Since the indexing calculations are visible to the compiler at compile time they can be * optimized to be efficient. */ @@ -230,14 +230,14 @@ class NdOffsetMatrixBase { } ///@brief Returns the starting index of ith dimension - size_t begin_index(size_t i) const { + int begin_index(size_t i) const { VTR_ASSERT_SAFE(i < ndims()); return dim_ranges_[i].begin_index(); } ///@brief Returns the one-past-the-end index of the ith dimension - size_t end_index(size_t i) const { + int end_index(size_t i) const { VTR_ASSERT_SAFE(i < ndims()); return dim_ranges_[i].end_index(); @@ -333,7 +333,7 @@ class NdOffsetMatrixBase { * * Examples: * - * //A 2-dimensional matrix with indicies [0..4][0..9] + * //A 2-dimensional matrix with indices [0..4][0..9] * NdOffsetMatrix m1({5,10}); * * //Accessing an element @@ -342,28 +342,28 @@ class NdOffsetMatrixBase { * //Setting an element * m4[6][20] = 0; * - * //A 2-dimensional matrix with indicies [2..6][5..9] + * //A 2-dimensional matrix with indices [2..6][5..9] * // Note that C++ requires one more set of curly brace than you would expect * NdOffsetMatrix m2({{{2,7},{5,10}}}); * - * //A 3-dimensional matrix with indicies [0..4][0..9][0..19] + * //A 3-dimensional matrix with indices [0..4][0..9][0..19] * NdOffsetMatrix m3({5,10,20}); * - * //A 3-dimensional matrix with indicies [2..6][1..19][50..89] + * //A 3-dimensional matrix with indices [2..6][1..19][50..89] * NdOffsetMatrix m4({{{2,7}, {1,20}, {50,90}}}); * - * //A 2-dimensional matrix with indicies [2..6][1..20], with all entries - * //intialized to 42 + * //A 2-dimensional matrix with indices [2..6][1..20], with all entries + * //initialized to 42 * NdOffsetMatrix m4({{{2,7}, {1,21}}}, 42); * - * //A 2-dimensional matrix with indicies [0..4][0..9], with all entries + * //A 2-dimensional matrix with indices [0..4][0..9], with all entries * //initialized to 42 * NdOffsetMatrix m1({5,10}, 42); * * //Filling all entries with value 101 * m1.fill(101); * - * //Resizing an existing matrix (all values reset to default constucted value) + * //Resizing an existing matrix (all values reset to default constructed value) * m1.resize({5,5}) * * //Resizing an existing matrix (all elements set to value 88) @@ -385,25 +385,25 @@ class NdOffsetMatrix : public NdOffsetMatrixBase { * Returns a proxy-object to allow chained array-style indexing (N >= 2 case) * template= 2>::type, typename T1=T> */ - const NdOffsetMatrixProxy operator[](size_t index) const { + const NdOffsetMatrixProxy operator[](int index) const { VTR_ASSERT_SAFE_MSG(this->dim_size(0) > 0, "Can not index into size zero dimension"); VTR_ASSERT_SAFE_MSG(this->dim_size(1) > 0, "Can not index into size zero dimension"); VTR_ASSERT_SAFE_MSG(index >= this->dim_ranges_[0].begin_index(), "Index out of range (below dimension minimum)"); VTR_ASSERT_SAFE_MSG(index < this->dim_ranges_[0].end_index(), "Index out of range (above dimension maximum)"); /* - * Clacluate the effective index + * Calculate the effective index * * The elements are stored in zero-indexed form, so adjust for any * non-zero minimum index in this dimension */ - size_t effective_index = index - this->dim_ranges_[0].begin_index(); + int effective_index = index - this->dim_ranges_[0].begin_index(); //Calculate the stride for the current dimension - size_t dim_stride = this->size() / this->dim_size(0); + int dim_stride = this->size() / this->dim_size(0); //Calculate the stride for the next dimension - size_t next_dim_stride = dim_stride / this->dim_size(1); + int next_dim_stride = dim_stride / this->dim_size(1); //Peel off the first dimension return NdOffsetMatrixProxy(this->dim_ranges_.data(), //Pass the dimension information @@ -417,7 +417,7 @@ class NdOffsetMatrix : public NdOffsetMatrixBase { * * Returns a proxy-object to allow chained array-style indexing */ - NdOffsetMatrixProxy operator[](size_t index) { + NdOffsetMatrixProxy operator[](int index) { //Call the const version, since returned by value don't need to worry about const return const_cast*>(this)->operator[](index); } @@ -436,7 +436,7 @@ class NdOffsetMatrix : public NdOffsetMatrixBase { public: ///@brief Access an element (immutable) - const T& operator[](size_t index) const { + const T& operator[](int index) const { VTR_ASSERT_SAFE_MSG(this->dim_size(0) > 0, "Can not index into size zero dimension"); VTR_ASSERT_SAFE_MSG(index >= this->dim_ranges_[0].begin_index(), "Index out of range (below dimension minimum)"); VTR_ASSERT_SAFE_MSG(index < this->dim_ranges_[0].end_index(), "Index out of range (above dimension maximum)"); @@ -445,7 +445,7 @@ class NdOffsetMatrix : public NdOffsetMatrixBase { } ///@brief Access an element (mutable) - T& operator[](size_t index) { + T& operator[](int index) { //Call the const version, and cast away const-ness return const_cast(const_cast*>(this)->operator[](index)); } From 099d040654c56c5d31cf0b8615bedaed57790d19 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Tue, 24 Sep 2024 18:34:35 -0400 Subject: [PATCH 13/16] replace ChanPlaceCostFacContainer with vtr::NdOffsetMatrix --- vpr/src/place/net_cost_handler.cpp | 52 +++++++++++++++--------------- vpr/src/place/net_cost_handler.h | 33 ++----------------- 2 files changed, 29 insertions(+), 56 deletions(-) diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index c9c6d670da1..ccdfd0349c6 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -157,22 +157,22 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_cost_exp) { auto& device_ctx = g_vpr_ctx.device(); - const size_t grid_height = device_ctx.grid.height(); - const size_t grid_width = device_ctx.grid.width(); + const int grid_height = device_ctx.grid.height(); + const int grid_width = device_ctx.grid.width(); /* Access arrays below as chan?_place_cost_fac_(subhigh, sublow). Since subhigh must be greater than or * equal to sublow, we will only access the lower half of a matrix, but we allocate the whole matrix anyway * for simplicity, so we can use the vtr utility matrix functions. */ - chanx_place_cost_fac_.resize({grid_height + 1, grid_height + 1}); - chany_place_cost_fac_.resize({grid_width + 1, grid_width + 1}); + chanx_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_height - 1}, {-1, grid_height - 1}}}); + chanx_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_width - 1}, {-1, grid_width - 1}}}); // First compute the number of tracks between channel high and channel low, inclusive. - chanx_place_cost_fac_(-1, -1) = 0; + chanx_place_cost_fac_[-1][-1] = 0; - for (int high = 0; high < (int)grid_height; high++) { - chanx_place_cost_fac_(high, high) = (float)device_ctx.chan_width.x_list[high]; + for (int high = 0; high < grid_height; high++) { + chanx_place_cost_fac_[high][high] = (float)device_ctx.chan_width.x_list[high]; for (int low = -1; low < high; low++) { - chanx_place_cost_fac_(high, low) = chanx_place_cost_fac_(high - 1, low) + (float)device_ctx.chan_width.x_list[high]; + chanx_place_cost_fac_[high][low] = chanx_place_cost_fac_[high - 1][low] + (float)device_ctx.chan_width.x_list[high]; } } @@ -183,50 +183,50 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_c * place_cost_exp power -- numbers other than one mean this is no * * longer a simple "average number of tracks"; it is some power of * * that, allowing greater penalization of narrow channels. */ - for (int high = -1; high < (int)grid_height; high++) { + for (int high = -1; high < grid_height; high++) { for (int low = -1; low <= high; low++) { /* Since we will divide the wiring cost by the average channel * * capacity between high and low, having only 0 width channels * * will result in infinite wiring capacity normalization * * factor, and extremely bad placer behaviour. Hence we change * * this to a small (1 track) channel capacity instead. */ - if (chanx_place_cost_fac_(high, low) == 0.0f) { + if (chanx_place_cost_fac_[high][low] == 0.0f) { VTR_LOG_WARN("CHANX place cost fac is 0 at %d %d\n", high, low); - chanx_place_cost_fac_(high, low) = 1.0f; + chanx_place_cost_fac_[high][low] = 1.0f; } - chanx_place_cost_fac_(high, low) = (high - low + 1.) / chanx_place_cost_fac_(high, low); - chanx_place_cost_fac_(high, low) = pow((double)chanx_place_cost_fac_(high, low), (double)place_cost_exp); + chanx_place_cost_fac_[high][low] = (high - low + 1.) / chanx_place_cost_fac_[high][low]; + chanx_place_cost_fac_[high][low] = pow((double)chanx_place_cost_fac_[high][low], (double)place_cost_exp); } } /* Now do the same thing for the y-directed channels. First get the * number of tracks between channel high and channel low, inclusive. */ - chany_place_cost_fac_(-1, -1) = 0; + chany_place_cost_fac_[-1][-1] = 0; - for (int high = 0; high < (int)grid_width; high++) { - chany_place_cost_fac_(high, high) = device_ctx.chan_width.y_list[high]; + for (int high = 0; high < grid_width; high++) { + chany_place_cost_fac_[high][high] = device_ctx.chan_width.y_list[high]; for (int low = -1; low < high; low++) { - chany_place_cost_fac_(high, low) = chany_place_cost_fac_(high - 1, low) + device_ctx.chan_width.y_list[high]; + chany_place_cost_fac_[high][low] = chany_place_cost_fac_[high - 1][low] + device_ctx.chan_width.y_list[high]; } } /* Now compute the inverse of the average number of tracks per channel * between high and low. Take to specified power. */ - for (int high = -1; high < (int)grid_width; high++) { + for (int high = -1; high < grid_width; high++) { for (int low = -1; low <= high; low++) { /* Since we will divide the wiring cost by the average channel * * capacity between high and low, having only 0 width channels * * will result in infinite wiring capacity normalization * * factor, and extremely bad placer behaviour. Hence we change * * this to a small (1 track) channel capacity instead. */ - if (chany_place_cost_fac_(high, low) == 0.0f) { + if (chany_place_cost_fac_[high][low] == 0.0f) { VTR_LOG_WARN("CHANY place cost fac is 0 at %d %d\n", high, low); - chany_place_cost_fac_(high, low) = 1.0f; + chany_place_cost_fac_[high][low] = 1.0f; } - chany_place_cost_fac_(high, low) = (high - low + 1.) / chany_place_cost_fac_(high, low); - chany_place_cost_fac_(high, low) = pow((double)chany_place_cost_fac_(high, low), (double)place_cost_exp); + chany_place_cost_fac_[high][low] = (high - low + 1.) / chany_place_cost_fac_[high][low]; + chany_place_cost_fac_[high][low] = pow((double)chany_place_cost_fac_[high][low], (double)place_cost_exp); } } } @@ -1411,8 +1411,8 @@ double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { */ double ncost; - ncost = (bb.xmax - bb.xmin + 1) * crossing * chanx_place_cost_fac_(bb.ymax, bb.ymin - 1); - ncost += (bb.ymax - bb.ymin + 1) * crossing * chany_place_cost_fac_(bb.xmax, bb.xmin - 1); + ncost = (bb.xmax - bb.xmin + 1) * crossing * chanx_place_cost_fac_[bb.ymax][bb.ymin - 1]; + ncost += (bb.ymax - bb.ymin + 1) * crossing * chany_place_cost_fac_[bb.xmax][bb.xmin - 1]; return ncost; } @@ -1454,10 +1454,10 @@ double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use */ ncost += (bb[layer_num].xmax - bb[layer_num].xmin + 1) * crossing - * chanx_place_cost_fac_(bb[layer_num].ymax, bb[layer_num].ymin - 1); + * chanx_place_cost_fac_[bb[layer_num].ymax][bb[layer_num].ymin - 1]; ncost += (bb[layer_num].ymax - bb[layer_num].ymin + 1) * crossing - * chany_place_cost_fac_(bb[layer_num].xmax, bb[layer_num].xmin - 1); + * chany_place_cost_fac_[bb[layer_num].xmax][bb[layer_num].xmin - 1]; } return ncost; diff --git a/vpr/src/place/net_cost_handler.h b/vpr/src/place/net_cost_handler.h index 9f22475765c..f3527362d6e 100644 --- a/vpr/src/place/net_cost_handler.h +++ b/vpr/src/place/net_cost_handler.h @@ -10,6 +10,7 @@ #include "timing_place.h" #include "move_transactions.h" #include "place_util.h" +#include "vtr_ndoffsetmatrix.h" #include @@ -190,34 +191,6 @@ class NetCostHandler { vtr::vector proposed_net_cost_; vtr::vector bb_update_status_; - /** - * @brief This class is used to store the inverse of average channel - * width between two channels inclusive. The difference of this class - * with vtr::NdMatrix is that its index spaces starts from -1. - * When the inverse average channel width is factored in, the channel - * immediately below and the channel immediately to the left of the - * bounding box are also considered. This class makes sure that when - * the left and bottom edges of the bounding boxes are moved by one unit, - * the indices used to access inverse average channel width are still valid. - */ - class ChanPlaceCostFacContainer : public vtr::NdMatrix { - public: - /** - * @brief Returns the inverse average channel width between channels low - * and high inclusive. - * @param high The high channel number. - * @param low The low channel number. - * @return The inverse average channel width between the given channel - * numbers. - */ - inline float& operator()(int high, int low) { - return this->operator[]((size_t)(high + 1)).operator[]((size_t)(low + 1)); - } - - private: - using vtr::NdMatrix::operator[]; - }; - /** * @brief Matrices below are used to precompute the inverse of the average * number of tracks per channel between [subhigh] and [sublow]. Access @@ -227,8 +200,8 @@ class NetCostHandler { * number of tracks in that direction; for other cost functions they * will never be used. */ - ChanPlaceCostFacContainer chanx_place_cost_fac_; // [-1...device_ctx.grid.width()-1] - ChanPlaceCostFacContainer chany_place_cost_fac_; // [-1...device_ctx.grid.height()-1] + vtr::NdOffsetMatrix chanx_place_cost_fac_; // [-1...device_ctx.grid.width()-1] + vtr::NdOffsetMatrix chany_place_cost_fac_; // [-1...device_ctx.grid.height()-1] private: From 888ac89c81807900a42944032623977fa7f56ced Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Tue, 24 Sep 2024 18:35:48 -0400 Subject: [PATCH 14/16] vtr::NdOffsetMatrix range is not inclusive --- vpr/src/place/net_cost_handler.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index ccdfd0349c6..de140547712 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -163,8 +163,8 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_c /* Access arrays below as chan?_place_cost_fac_(subhigh, sublow). Since subhigh must be greater than or * equal to sublow, we will only access the lower half of a matrix, but we allocate the whole matrix anyway * for simplicity, so we can use the vtr utility matrix functions. */ - chanx_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_height - 1}, {-1, grid_height - 1}}}); - chanx_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_width - 1}, {-1, grid_width - 1}}}); + chanx_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_height}, {-1, grid_height}}}); + chanx_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_width}, {-1, grid_width}}}); // First compute the number of tracks between channel high and channel low, inclusive. chanx_place_cost_fac_[-1][-1] = 0; From 6f5a3aae2dd50690ba7aae48bd1d742b98dcdbc1 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Tue, 24 Sep 2024 19:09:20 -0400 Subject: [PATCH 15/16] fix compilation warnings --- vpr/src/draw/draw_basic.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index 82ad456f70f..8a9b488cf16 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -631,8 +631,8 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren static vtr::OffsetMatrix chany_track; /* [0..device_ctx.grid.width() - 2][1..device_ctx.grid.height() - 2] */ if (draw_state->draw_route_type == GLOBAL) { /* Allocate some temporary storage if it's not already available. */ - size_t width = device_ctx.grid.width(); - size_t height = device_ctx.grid.height(); + int width = (int)device_ctx.grid.width(); + int height = (int)device_ctx.grid.height(); if (chanx_track.empty()) { chanx_track = vtr::OffsetMatrix({{{1, width - 1}, {0, height - 1}}}); } @@ -641,12 +641,12 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren chany_track = vtr::OffsetMatrix({{{0, width - 1}, {1, height - 1}}}); } - for (size_t i = 1; i < width - 1; i++) - for (size_t j = 0; j < height - 1; j++) + for (int i = 1; i < width - 1; i++) + for (int j = 0; j < height - 1; j++) chanx_track[i][j] = (-1); - for (size_t i = 0; i < width - 1; i++) - for (size_t j = 1; j < height - 1; j++) + for (int i = 0; i < width - 1; i++) + for (int j = 1; j < height - 1; j++) chany_track[i][j] = (-1); } From 56b989ac669530d70ec2ad5321c2b233eaa5a293 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sat, 28 Sep 2024 13:10:27 -0400 Subject: [PATCH 16/16] initialize chany_place_cost_fac_ --- vpr/src/place/net_cost_handler.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index de140547712..1dbef60a546 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -164,7 +164,7 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_(float place_c * equal to sublow, we will only access the lower half of a matrix, but we allocate the whole matrix anyway * for simplicity, so we can use the vtr utility matrix functions. */ chanx_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_height}, {-1, grid_height}}}); - chanx_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_width}, {-1, grid_width}}}); + chany_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_width}, {-1, grid_width}}}); // First compute the number of tracks between channel high and channel low, inclusive. chanx_place_cost_fac_[-1][-1] = 0;