Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into add_crr

Author: amin1377

doc/src/Images/Overall_view.png

@@ -582,10 +582,12 @@ Grid Layout Example
     Example FPGA grid
 
 
-.. arch:tag:: <interposer_cut dim=x|y loc="int"/>
+.. arch:tag:: <interposer_cut x="int" y="int"/>
 
-    :req_param dim: Dimension or axis of the cut. 'X' or 'x' means a horizontal cut while 'Y' or 'y' means a vertical cut.
-    :req_param loc: Location of the cut. Cuts are done above or to the right of the tiles at coordinate 'loc'. For example a cut with dim=x and loc=0 would cut the vertical wires above tiles in the 0th row. Currently only integer values are supported.
+    :opt_param x: Specifies the x-coordinate of a vertical interposer cut.
+    :opt_param y: Specifies the y-coordinate of a horizontal interposer cut.
+
+    .. note:: Exactly one of the ``x`` or ``y`` attributes must be specified.
 
     .. note:: Interposers are experimental and are currently not supported by VPR and using the related tags will not actually result in any changes to the flow.
     Defines an interposer cut for modelling 2.5D interposer-based architectures. An interposer cut will cut all connections at location 'loc' along the axis 'dim' Leaving the two sides completely unconnected.
@@ -2363,6 +2365,8 @@ Direct Inter-block Connections
 The content within the ``<directlist>`` tag consists of a group of ``<direct>`` tags.
 The ``<direct>`` tag and its contents are described below.
 
+.. note:: ``from_pin`` and ``to_pin`` only support big endian! For example, ``clb.out[8:0]``
+
 .. arch:tag:: <direct name="string" from_pin="string" to_pin="string" x_offset="int" y_offset="int" z_offset="int" switch_name="string" from_side="{left|right|top|bottom}" to_side="{left|right|top|bottom}"/>
 
     :req_param name: is a unique alphanumeric string to name the connection.
@@ -2382,12 +2386,89 @@ The ``<direct>`` tag and its contents are described below.
     The ``from_side`` and ``to_side`` options can usually be left unspecified.
     However they can be used to explicitly control how direct connections to physically equivalent pins (which may appear on multiple sides) are handled.
 
-    **Example:**
-    Consider a carry chain where the ``cout`` of each CLB drives the ``cin`` of the CLB immediately below it, using the delay-less switch one would enter the following:
+**Example: Inter-tile connection**
+Consider a carry chain where the ``cout`` of each CLB drives the ``cin`` of the CLB immediately below it, using the delay-less switch one would enter the following:
 
-    .. code-block:: xml
+.. code-block:: xml
+
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+
+**Example: Inner-tile feedback**
+
+Consider a feedback connection where the ``out`` of each CLB drives the ``in`` of the CLB in the same location, using the connection block switch one would enter the following:
+
+.. code-block:: xml
+
+    <direct name="feedback" from_pin="clb.out" to_pin="clb.in" x_offset="0" y_offset="0" z_offset="0" switch_name="cb_mux"/>
+
+**Example: Cross-sub-tile connection**
+
+In this example, a tile ``cim8_1k`` is defined, under which there are two types of sub-tiles:
+
+- ``mult_8``: the first sub-tile
+- ``memory``: the second, and the third sub-tile
+
+.. code-block:: xml
+
+    <tile name="cim8_1k" height="2" area="396000">
+      <sub_tile name="mult_8" capacity="1">
+        <equivalent_sites>
+          <site pb_type="mult_8" pin_mapping="direct"/>
+        </equivalent_sites>
+        <input name="a" num_pins="8"/>
+        <input name="b" num_pins="8"/>
+        <output name="out" num_pins="16"/>
+        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+          <fc_override port_name="out" fc_type="frac" fc_val="0"/>
+        </fc>
+        <pinlocations pattern="custom">
+          <loc side="left"/>
+          <loc side="top"/>
+          <loc side="right" yoffset="0">mult_8.a[0:2] mult_8.b[0:2] mult_8.out[0:5]</loc>
+          <loc side="right" yoffset="1">mult_8.a[3:5] mult_8.b[3:5] mult_8.out[6:10]</loc>
+          <loc side="bottom">mult_8.a[6:7] mult_8.b[6:7] mult_8.out[11:15]</loc>
+        </pinlocations>
+      </sub_tile>
+      <sub_tile name="memory" capacity="2">
+        <equivalent_sites>
+          <site pb_type="memory"/>
+        </equivalent_sites>
+        <input name="waddr" num_pins="7"/>
+        <input name="raddr" num_pins="7"/>
+        <input name="data_in" num_pins="8"/>
+        <input name="wen" num_pins="1"/>
+        <input name="ren" num_pins="1"/>
+        <output name="data_out" num_pins="8"/>
+        <clock name="clk" num_pins="1"/>
+        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+          <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
+          <fc_override port_name="data_in" fc_type="frac" fc_val="0"/>
+        </fc>
+        <pinlocations pattern="custom">
+          <loc side="left" yoffset="0">memory.clk memory.waddr[0:0] memory.raddr[0:0] memory.data_in[0:0] memory.data_out[0:0]</loc>
+          <loc side="left" yoffset="1">memory.waddr[1:1] memory.raddr[1:1] memory.data_in[1:1] memory.data_out[1:1]</loc>
+          <loc side="top" yoffset="1">memory.waddr[2:2] memory.raddr[2:2] memory.data_in[2:2] memory.data_out[2:2] memory.waddr[3:3] memory.raddr[3:3] memory.data_in[3:3] memory.data_out[3:3]</loc>
+          <loc side="right" yoffset="0">memory.waddr[4:4] memory.raddr[4:4] memory.data_in[4:4] memory.data_out[4:4]</loc>
+          <loc side="right" yoffset="1">memory.waddr[5:5] memory.raddr[5:5] memory.data_in[5:5] memory.data_out[5:5]</loc>
+          <loc side="bottom" yoffset="0">memory.wen memory.waddr[6:6] memory.raddr[6:6] memory.data_in[6:6] memory.data_out[6:6] memory.ren memory.data_in[7:7] memory.data_out[7:7]</loc>
+        </pinlocations>
+      </sub_tile>
+    </tile>
+
+As shown in :numref:`fig_example_subtile_direct_connection`, consider a connection where the ``out`` of a sub tile ``mult_8`` of tile ``cim8_1k`` drives the ``data_in`` of the sub tile ``memory`` of tile ``cim8_1k`` with an offset, using the delayless switch one would enter the following:
+
+.. code-block:: xml
+
+    <direct name="cim_direct0" from_pin="cim8_1k.out[7:0]" to_pin="cim8_1k.data_in[7:0]" x_offset="0" y_offset="0" z_offset="1"/>
+    <direct name="cim_direct1" from_pin="cim8_1k.out[15:8]" to_pin="cim8_1k.data_in[7:0]" x_offset="0" y_offset="0" z_offset="2"/>
+
+.. _fig_example_subtile_direct_connection:
+
+.. figure:: ./example_subtile_direct_connection.png
+   :width: 60%
+   :alt: Example of direct connections across sub-tiles
 
-        <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+   Example of direct connections across sub-tiles
 
 .. _custom_switch_blocks:
 

doc/src/arch/example_subtile_direct_connection.png

@@ -308,6 +308,7 @@ Manual Moves
 
 The manual moves feature allows the user to specify the next move in placement. If the move is legal, blocks are swapped and the new move is shown on the architecture. 
 
+.. _fig-misc-tab:
 .. figure:: ../Images/manual_move.png
     :align: center
     :width: 25%
@@ -335,3 +336,15 @@ If the manual move is legal, the cost summary window will display the delta cost
 
 The user can Accept or Reject the manual move based on the values provided. If accepted the block's new location is shown. 
 
+Pause Button
+------------
+
+The pause button allows the user to temporarily stop the program during placement or routing.
+When clicked during the placement stage, the program will pause at the next temperature update.
+When clicked during the routing stage, it will pause at the next router iteration.
+
+The button can be pressed at any time while the program is running. To enable the feature, click the **Pause** button under the **Misc.** tab (see :ref:`fig-misc-tab`).
+Once the program reaches the next temperature update or router iteration after the button is pressed, it will automatically pause.
+
+After the program has paused, clicking **Next Step** allows the user to resume execution from the point where the program was paused.
+This can be continuing from the current temperature in placement or from the current router iteration in routing.

doc/src/arch/reference.rst

@@ -9,7 +9,7 @@ How to Cite
 Citations are important in academia, as they ensure contributors receive credit for their efforts.
 Therefore please use the following paper as a general citation whenever you use VTR:
 
-    M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Koşar, K. Talaei, J. Fife, D. Khadivi, K. E. Murray, A. Boutros, K.B. Kent, J. Goeders, V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration" ACM TRETS, 2025
+    M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Koşar, K. Talaei, J. Fife, D. Khadivi, K. E. Murray, A. Boutros, K.B. Kent, J. Goeders, V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration" ACM TRETS, Vol. 13, No. 3, Sept. 2025, pp. 1 - 53.
 
 Bibtex:
 
@@ -19,6 +19,10 @@ Bibtex:
       title={VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration},
       author={Elgammal, Mohamed A. and Mohaghegh, Amin and Shahrouz, Soheil G. and Mahmoudi, Fatemehsadat and Kosar, Fahrican and Talaei, Kimia and Fife, Joshua and Khadivi, Daniel and Murray, Kevin and Boutros, Andrew and Kent, Kenneth B. and Goeders, Jeff and Betz, Vaughn},
       journal={ACM Trans. Reconfigurable Technol. Syst.},
+      issue_date = {September 2025},
+      volume = {18},
+      number = {3},
+      numpages = {53},
       year={2025}
     }
 

doc/src/vpr/graphics.rst

@@ -2,16 +2,23 @@
 
 #include <utility>
 
-DeviceGrid::DeviceGrid(std::string grid_name, vtr::NdMatrix<t_grid_tile, 3> grid)
-    : name_(std::move(grid_name))
-    , grid_(std::move(grid)) {
+DeviceGrid::DeviceGrid(std::string_view grid_name,
+                       vtr::NdMatrix<t_grid_tile, 3> grid,
+                       std::vector<std::vector<int>>&& horizontal_interposer_cuts,
+                       std::vector<std::vector<int>>&& vertical_interposer_cuts)
+    : name_(grid_name)
+    , grid_(std::move(grid))
+    , horizontal_interposer_cuts_(std::move(horizontal_interposer_cuts))
+    , vertical_interposer_cuts_(std::move(vertical_interposer_cuts)) {
     count_instances();
 }
 
-DeviceGrid::DeviceGrid(std::string grid_name,
+DeviceGrid::DeviceGrid(std::string_view grid_name,
                        vtr::NdMatrix<t_grid_tile, 3> grid,
-                       std::vector<t_logical_block_type_ptr> limiting_res)
-    : DeviceGrid(std::move(grid_name), std::move(grid)) {
+                       std::vector<t_logical_block_type_ptr> limiting_res,
+                       std::vector<std::vector<int>>&& horizontal_interposer_cuts,
+                       std::vector<std::vector<int>>&& vertical_interposer_cuts)
+    : DeviceGrid(grid_name, std::move(grid), std::move(horizontal_interposer_cuts), std::move(vertical_interposer_cuts)) {
     limiting_resources_ = std::move(limiting_res);
 }
 

doc/src/vtr/get_vtr.rst

@@ -26,8 +26,16 @@ struct t_grid_tile {
 class DeviceGrid {
   public:
     DeviceGrid() = default;
-    DeviceGrid(std::string grid_name, vtr::NdMatrix<t_grid_tile, 3> grid);
-    DeviceGrid(std::string grid_name, vtr::NdMatrix<t_grid_tile, 3> grid, std::vector<t_logical_block_type_ptr> limiting_res);
+    DeviceGrid(std::string_view grid_name,
+               vtr::NdMatrix<t_grid_tile, 3> grid,
+               std::vector<std::vector<int>>&& horizontal_interposer_cuts,
+               std::vector<std::vector<int>>&& vertical_interposer_cuts);
+
+    DeviceGrid(std::string_view grid_name,
+               vtr::NdMatrix<t_grid_tile, 3> grid,
+               std::vector<t_logical_block_type_ptr> limiting_res,
+               std::vector<std::vector<int>>&& horizontal_interposer_cuts,
+               std::vector<std::vector<int>>&& vertical_interposer_cuts);
 
     const std::string& name() const { return name_; }
 
@@ -63,7 +71,7 @@ class DeviceGrid {
      * @brief Returns the block types which limits the device size (may be empty if
      *        resource limits were not considered when selecting the device).
      */
-    std::vector<t_logical_block_type_ptr> limiting_resources() const { return limiting_resources_; }
+    const std::vector<t_logical_block_type_ptr>& limiting_resources() const { return limiting_resources_; }
 
     ///@brief Return the t_physical_tile_type_ptr at the specified location
     inline t_physical_tile_type_ptr get_physical_type(const t_physical_tile_loc& tile_loc) const {
@@ -189,15 +197,31 @@ class DeviceGrid {
         return &grid_.get(n);
     }
 
+    /// Returns the list of horizontal interposer cut locations for each layer,
+    /// i.e. y value of the tile row just below each cut
+    /// Accessed as [layer][cut_idx]
+    inline const std::vector<std::vector<int>>& get_horizontal_interposer_cuts() const {
+        return horizontal_interposer_cuts_;
+    }
+
+    /// Returns the list of vertical interposer cut locations for each layer,
+    /// i.e. x value of the tile column just to the left each cut
+    /// Accessed as [layer][cut_idx]
+    inline const std::vector<std::vector<int>>& get_vertical_interposer_cuts() const {
+        return vertical_interposer_cuts_;
+    }
+
   private:
-    ///@brief count_instances() counts the number of each tile type on each layer and store it in instance_counts_. It is called in the constructor.
+    /// @brief Counts the number of each tile type on each layer and store it in instance_counts_.
+    /// It is called in the constructor.
     void count_instances();
 
     std::string name_;
 
     /**
      * @brief grid_ is a 3D matrix that represents the grid of the FPGA chip.
-     * @note The first dimension is the layer number (grid_[0] corresponds to the bottom layer), the second dimension is the x coordinate, and the third dimension is the y coordinate.
+     * @note The first dimension is the layer number (grid_[0] corresponds to the bottom layer),
+     *       the second dimension is the x coordinate, and the third dimension is the y coordinate.
      * @note Note that vtr::Matrix operator[] returns and intermediate type
      * @note which can be used for indexing in the second dimension, allowing
      * @note traditional 2-d indexing to be used
@@ -208,4 +232,13 @@ class DeviceGrid {
     std::vector<std::map<t_physical_tile_type_ptr, size_t>> instance_counts_; /* [layer_num][physical_tile_type_ptr] */
 
     std::vector<t_logical_block_type_ptr> limiting_resources_;
+
+    /// Horizontal interposer cut locations in each layer,
+    /// i.e. y value of the tile row just below each cut
+    /// Accessed as [layer][cut_idx]
+    std::vector<std::vector<int>> horizontal_interposer_cuts_;
+    /// Vertical interposer cut location in each layer,
+    /// i.e. x value of the tile column just to the left each cut
+    /// Accessed as [layer][cut_idx]
+    std::vector<std::vector<int>> vertical_interposer_cuts_;
 };

libs/libarchfpga/src/device_grid.cpp

@@ -4,33 +4,20 @@
  * @file interposer_types.h
  * @brief This file contains types used for parsing interposer-related tags such as <interposer_cut> and <interdie_wire>
  * and converting that information into the device architecture-related data structures.
- * 
  */
 
-#include <unordered_map>
 #include <vector>
 #include <string>
 #include "grid_types.h"
 
-/**
- * @brief Enum for direction of an interposer cut. X means horizontal cut and Y means vertical cut.
- * 
- */
-enum class e_interposer_cut_dim {
-    X,
-    Y
+/// @brief Enum for direction of an interposer cut.
+enum class e_interposer_cut_type {
+    HORZ,
+    VERT
 };
 
-// Lookup table for converting between a character and an e_interposer_cut_dim
-inline const std::unordered_map<char, e_interposer_cut_dim> CHAR_INTERPOSER_DIM_MAP = {
-    {'X', e_interposer_cut_dim::X},
-    {'x', e_interposer_cut_dim::X},
-    {'Y', e_interposer_cut_dim::Y},
-    {'y', e_interposer_cut_dim::Y}};
-
 /**
  * @brief Struct containing information of interdire wires i.e. connections between the dies on an interposer
- * 
  */
 struct t_interdie_wire_inf {
     std::string sg_name; ///< Name of the scatter-gather pattern to be used for the interdie connection
@@ -40,18 +27,18 @@ struct t_interdie_wire_inf {
      * Contains starting and ending point (both inclusive) of scatter-gather instantiations and the increment/distance between the instantiations.
      * offset_definition.repeat_expr is not relevant for interdie wires and is not set to anything or used.
      * 
-     * Locations defined by this offset definition define the starting point or the gathering point of the SG pattern. The end or scatter point of the SG pattern is defined by the sg_link.
+     * Locations defined by this offset definition define the starting point or the gathering point of the SG pattern.
+     * The end or scatter point of the SG pattern is defined by the sg_link.
      */
     t_grid_loc_spec offset_definition;
     int num; ///< Number of scatter-gather instantiations per switchblock location
 };
 
 /**
  * @brief Struct containing information of an interposer cut
- * 
  */
 struct t_interposer_cut_inf {
-    e_interposer_cut_dim dim;                        ///< Dimension or axis of interposer cut.
+    e_interposer_cut_type dim;                       ///< Axis of interposer cut location. The cut is perpendicular to this axis. This specifies the dimension of `loc`.
     int loc;                                         ///< Location of the cut on the grid. Locations start from zero and cuts will happen above or to the right of the tiles at location=loc.
     std::vector<t_interdie_wire_inf> interdie_wires; ///< Connectivity specification between the two sides of the cut.
 };

libs/libarchfpga/src/device_grid.h

@@ -241,7 +241,7 @@ enum e_power_estimation_method_ {
     POWER_METHOD_SPECIFY_SIZES,   /* Transistor-level, user-specified buffers/wires */
     POWER_METHOD_TOGGLE_PINS,     /* Dynamic: Energy per pin toggle, Static: Absolute */
     POWER_METHOD_C_INTERNAL,      /* Dynamic: Equiv. Internal capacitance, Static: Absolute */
-    POWER_METHOD_ABSOLUTE         /* Dynamic: Aboslute, Static: Absolute */
+    POWER_METHOD_ABSOLUTE         /* Dynamic: Absolute, Static: Absolute */
 };
 typedef enum e_power_estimation_method_ e_power_estimation_method;
 typedef enum e_power_estimation_method_ t_power_estimation_method;

libs/libarchfpga/src/interposer_types.h

@@ -2661,7 +2661,8 @@ static void process_block_type_locs(t_grid_def& grid_def,
 
             t_interposer_cut_inf interposer_cut = parse_interposer_cut_tag(loc_spec_tag, loc_data);
 
-            if ((interposer_cut.dim == e_interposer_cut_dim::X && interposer_cut.loc >= grid_def.height) || (interposer_cut.dim == e_interposer_cut_dim::Y && interposer_cut.loc >= grid_def.width)) {
+            if ((interposer_cut.dim == e_interposer_cut_type::VERT && interposer_cut.loc >= grid_def.width)
+                || (interposer_cut.dim == e_interposer_cut_type::HORZ && interposer_cut.loc >= grid_def.height)) {
                 archfpga_throw(loc_data.filename_c_str(), loc_data.line(loc_spec_tag), "Interposer cut dimensions are outside of device bounds");
             }