Update documentation to reflect migration from F4PGA to Synlig

Author: amirarjmand93

.github/workflows/nightly_test.yml

@@ -65,9 +65,9 @@ jobs:
           - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                         extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
-          - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)
+          - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DSYNLIG_SYSTEMVERILOG=ON",                                     extra_pkgs: ""} 
           - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
-          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""}
+          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DSYNLIG_SYSTEMVERILOG=ON",                                     extra_pkgs: ""}
 
     env:
       DEBIAN_FRONTEND: "noninteractive"

CMakeLists.txt

@@ -60,7 +60,7 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
 
 # Allow the user to enable building Yosys
 option(WITH_PARMYS "Enable Yosys as elaborator and parmys-plugin as partial mapper" ON)
-option(YOSYS_F4PGA_PLUGINS "Enable building and installing Yosys SystemVerilog and UHDM plugins" OFF)
+option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF)
 
 set(VTR_VERSION_MAJOR 8)
 set(VTR_VERSION_MINOR 1)
@@ -453,7 +453,7 @@ if(${WITH_ODIN})
 endif()
 
 # handle cmake params to compile Yosys SystemVerilog/UHDM plugins
-if(${YOSYS_F4PGA_PLUGINS})
+if(${SYNLIG_SYSTEMVERILOG})
     # avoid compiling plugins in case the Parmys frontend is not active
     if(NOT ${WITH_PARMYS})
         message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Parmys frontend. Please set WITH_PARMYS.")

doc/src/parmys/quickstart.rst

@@ -37,8 +37,8 @@ To build the VTR flow with the Parmys front-end you may use the VTR Makefile wra
 
 .. note::
 
-    Compiling the VTR flow with the ``-DYOSYS_F4PGA_PLUGINS=ON`` flag is required to build and install Yosys SystemVerilog and UHDM plugins.
-    Using this compile flag, the `Yosys-F4PGA-Plugins <https://github.com/chipsalliance/yosys-f4pga-plugins>`_ and `Surelog <https://github.com/chipsalliance/Surelog>`_ repositories are cloned in the ``$VTR_ROOT/libs/EXTERNAL`` directory and then will be compiled and added as external plugins to the Parmys front-end.
+    Compiling the VTR flow with the ``-DSynlig_SystemVerilog=ON`` flag is required to build and install Synlig SystemVerilog and UHDM plugins.
+    Using this compile flag, the `Synlig_SystemVerilog <https://github.com/chipsalliance/synlig>`_ repository is cloned and installed in the ``$VTR_ROOT/build/bin`` directory and then will be compiled and added as external tool to the Parmys front-end.
 
 Basic Usage
 -----------

doc/src/vtr/run_vtr_flow.rst

@@ -73,15 +73,15 @@ The parser for these runs is considered the Yosys conventional Verilog/SystemVer
 
 .. code-block:: bash
 
-    # Using the Yosys-SystemVerilog plugin if installed, otherwise the Yosys conventional Verilog parser
+    # Using the Synlig System_Verilog tool if installed, otherwise the Yosys conventional Verilog parser
     ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -parser system-verilog
 
     # Using the Surelog plugin if installed, otherwise failure on the unsupported file type
     ./run_vtr_flow <path/to/UHDM/File> <path/to/arch/file> -parser surelog
 
 Running the default VTR flow using the Parmys standalone front-end.
-The Yosys HDL parser is considered as Yosys-SystemVerilog plugin (i.e., ``read_systemverilog``) and Yosys UHDM plugin (i.e., ``read_uhdm``), respectively.
-Utilizing Yosys plugins requires passing the ``-DYOSYS_F4PGA_PLUGINS=ON`` compile flag to build and install the plugins for the Parmys front-end.
+The Synlig HDL parser supports the (i.e., ``read_systemverilog``) and (i.e., ``read_uhdm``) commands. It utilizes Surelog for SystemVerilog 2017 processing and Yosys for synthesis.
+Enable Synlig tool with the ``-DSYNLIG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end.
 
 .. code-block:: bash
 

libs/EXTERNAL/CMakeLists.txt

@@ -38,7 +38,7 @@ endif ()
 # The VTR root CMakeFile initializes the WITH_PARMYS
 if (${WITH_PARMYS})
 
-    if (${YOSYS_F4PGA_PLUGINS})
+    if (${SYNLIG_SYSTEMVERILOG})
 
         set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
         set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build)

vtr_flow/benchmarks/system_verilog/f4pga/button_controller/make_sv_flattened.py

@@ -73,22 +73,13 @@ techmap -map +/parmys/aldffe2dff.v
 
 opt -full
 
-#parmys -a QQQ -nopass -c CCC YYY
-#parmys -a QQQ -c CCC YYY
-#memory -nomap
-#flatten
-
-
-# Separate opt for Parmys execution(verilog or system-verilog)
+# Separate options for Parmys execution (Verilog or SystemVerilog)
 if {$env(PARSER) == "default"} {
-    puts "Running Parmys with disables additional passes "
+    # For Verilog, use -nopass for a simpler, faster flow
     parmys -a QQQ -nopass -c CCC YYY
-
 } elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} {
-    puts "Running Parmys with Additional Passes Resolve Conflicts"
+    # For Synlig SystemVerilog, run additional passes to handle complexity
     parmys -a QQQ -c CCC YYY
-    memory -nomap
-    flatten
 }
 
 opt -full
@@ -104,4 +95,4 @@ stat
 
 hierarchy -check -auto-top -purge_lib
 
-write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ
+write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ