Merge pull request #2661 from verilog-to-routing/pass_actual_fc_to_connect_to_pins

Pass actual fc instead of fc_max to connect to pins

Author: vaughnbetz

vpr/src/route/rr_graph.cpp

@@ -1,2 +1,2 @@
- arch	  circuit	  script_params	  crit_path_delay_mcw	  clk_to_clk_cpd	  clk_to_clk2_cpd	  clk_to_input_cpd	  clk_to_output_cpd	  clk2_to_clk2_cpd	  clk2_to_clk_cpd	  clk2_to_input_cpd	  clk2_to_output_cpd	  input_to_input_cpd	  input_to_clk_cpd	  input_to_clk2_cpd	  input_to_output_cpd	  output_to_output_cpd	  output_to_clk_cpd	  output_to_clk2_cpd	  output_to_input_cpd	  clk_to_clk_setup_slack	  clk_to_clk2_setup_slack	  clk_to_input_setup_slack	  clk_to_output_setup_slack	  clk2_to_clk2_setup_slack	  clk2_to_clk_setup_slack	  clk2_to_input_setup_slack	  clk2_to_output_setup_slack	  input_to_input_setup_slack	  input_to_clk_setup_slack	  input_to_clk2_setup_slack	  input_to_output_setup_slack	  output_to_output_setup_slack	  output_to_clk_setup_slack	  output_to_clk2_setup_slack	  output_to_input_setup_slack	  clk_to_clk_hold_slack	  clk_to_clk2_hold_slack	  clk_to_input_hold_slack	  clk_to_output_hold_slack	  clk2_to_clk2_hold_slack	  clk2_to_clk_hold_slack	  clk2_to_input_hold_slack	  clk2_to_output_hold_slack	  input_to_input_hold_slack	  input_to_clk_hold_slack	  input_to_clk2_hold_slack	  input_to_output_hold_slack	  output_to_output_hold_slack	  output_to_clk_hold_slack	  output_to_clk2_hold_slack	  output_to_input_hold_slack	 
- k6_frac_N10_mem32K_40nm_clk_buf.xml	  multiclock_buf.blif	  common	  1.6965	  0.545	  -1	  -1	  -1	  0.545	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  0.293	  -1	  -1	  -1	  0.293	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+arch	circuit	script_params	crit_path_delay_mcw	clk_to_clk_cpd	clk_to_clk2_cpd	clk_to_input_cpd	clk_to_output_cpd	clk2_to_clk2_cpd	clk2_to_clk_cpd	clk2_to_input_cpd	clk2_to_output_cpd	input_to_input_cpd	input_to_clk_cpd	input_to_clk2_cpd	input_to_output_cpd	output_to_output_cpd	output_to_clk_cpd	output_to_clk2_cpd	output_to_input_cpd	clk_to_clk_setup_slack	clk_to_clk2_setup_slack	clk_to_input_setup_slack	clk_to_output_setup_slack	clk2_to_clk2_setup_slack	clk2_to_clk_setup_slack	clk2_to_input_setup_slack	clk2_to_output_setup_slack	input_to_input_setup_slack	input_to_clk_setup_slack	input_to_clk2_setup_slack	input_to_output_setup_slack	output_to_output_setup_slack	output_to_clk_setup_slack	output_to_clk2_setup_slack	output_to_input_setup_slack	clk_to_clk_hold_slack	clk_to_clk2_hold_slack	clk_to_input_hold_slack	clk_to_output_hold_slack	clk2_to_clk2_hold_slack	clk2_to_clk_hold_slack	clk2_to_input_hold_slack	clk2_to_output_hold_slack	input_to_input_hold_slack	input_to_clk_hold_slack	input_to_clk2_hold_slack	input_to_output_hold_slack	output_to_output_hold_slack	output_to_clk_hold_slack	output_to_clk2_hold_slack	output_to_input_hold_slack	
+k6_frac_N10_mem32K_40nm_clk_buf.xml	multiclock_buf.blif	common	1.48876	0.545	-1	-1	-1	0.545	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0.293	-1	-1	-1	0.293	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt

@@ -1,2 +1,2 @@
- arch	  circuit	  script_params	  crit_path_delay_mcw	  clk_to_clk_cpd	  clk_to_clk2_cpd	  clk_to_input_cpd	  clk_to_output_cpd	  clk2_to_clk2_cpd	  clk2_to_clk_cpd	  clk2_to_input_cpd	  clk2_to_output_cpd	  input_to_input_cpd	  input_to_clk_cpd	  input_to_clk2_cpd	  input_to_output_cpd	  output_to_output_cpd	  output_to_clk_cpd	  output_to_clk2_cpd	  output_to_input_cpd	  clk_to_clk_setup_slack	  clk_to_clk2_setup_slack	  clk_to_input_setup_slack	  clk_to_output_setup_slack	  clk2_to_clk2_setup_slack	  clk2_to_clk_setup_slack	  clk2_to_input_setup_slack	  clk2_to_output_setup_slack	  input_to_input_setup_slack	  input_to_clk_setup_slack	  input_to_clk2_setup_slack	  input_to_output_setup_slack	  output_to_output_setup_slack	  output_to_clk_setup_slack	  output_to_clk2_setup_slack	  output_to_input_setup_slack	  clk_to_clk_hold_slack	  clk_to_clk2_hold_slack	  clk_to_input_hold_slack	  clk_to_output_hold_slack	  clk2_to_clk2_hold_slack	  clk2_to_clk_hold_slack	  clk2_to_input_hold_slack	  clk2_to_output_hold_slack	  input_to_input_hold_slack	  input_to_clk_hold_slack	  input_to_clk2_hold_slack	  input_to_output_hold_slack	  output_to_output_hold_slack	  output_to_clk_hold_slack	  output_to_clk2_hold_slack	  output_to_input_hold_slack	 
- k6_frac_N10_mem32K_40nm_clk_buf.xml	  multiclock_buf.blif	  common	  1.6965	  0.545	  -1	  -1	  -1	  0.545	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  0.293	  -1	  -1	  -1	  0.293	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+arch	circuit	script_params	crit_path_delay_mcw	clk_to_clk_cpd	clk_to_clk2_cpd	clk_to_input_cpd	clk_to_output_cpd	clk2_to_clk2_cpd	clk2_to_clk_cpd	clk2_to_input_cpd	clk2_to_output_cpd	input_to_input_cpd	input_to_clk_cpd	input_to_clk2_cpd	input_to_output_cpd	output_to_output_cpd	output_to_clk_cpd	output_to_clk2_cpd	output_to_input_cpd	clk_to_clk_setup_slack	clk_to_clk2_setup_slack	clk_to_input_setup_slack	clk_to_output_setup_slack	clk2_to_clk2_setup_slack	clk2_to_clk_setup_slack	clk2_to_input_setup_slack	clk2_to_output_setup_slack	input_to_input_setup_slack	input_to_clk_setup_slack	input_to_clk2_setup_slack	input_to_output_setup_slack	output_to_output_setup_slack	output_to_clk_setup_slack	output_to_clk2_setup_slack	output_to_input_setup_slack	clk_to_clk_hold_slack	clk_to_clk2_hold_slack	clk_to_input_hold_slack	clk_to_output_hold_slack	clk2_to_clk2_hold_slack	clk2_to_clk_hold_slack	clk2_to_input_hold_slack	clk2_to_output_hold_slack	input_to_input_hold_slack	input_to_clk_hold_slack	input_to_clk2_hold_slack	input_to_output_hold_slack	output_to_output_hold_slack	output_to_clk_hold_slack	output_to_clk2_hold_slack	output_to_input_hold_slack	
+k6_frac_N10_mem32K_40nm_clk_buf.xml	multiclock_buf.blif	common	1.48876	0.545	-1	-1	-1	0.545	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0.293	-1	-1	-1	0.293	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1