some cleanups

soheilshahrouz · soheilshahrouz · commit edbb9f4402d9 · 2025-11-04T15:05:48.000-05:00
diff --git a/libs/libarchfpga/src/physical_types_util.cpp b/libs/libarchfpga/src/physical_types_util.cpp
@@ -236,10 +236,9 @@ static int get_logical_block_physical_pin_num_offset(t_physical_tile_type_ptr ph
                                                      const t_sub_tile* curr_sub_tile,
                                                      t_logical_block_type_ptr curr_logical_block,
                                                      const int curr_relative_cap) {
-    int offset;
-    offset = get_sub_tile_inst_physical_pin_num_offset(physical_tile, curr_sub_tile, curr_relative_cap);
+    int offset = get_sub_tile_inst_physical_pin_num_offset(physical_tile, curr_sub_tile, curr_relative_cap);
 
-    for (auto eq_site : curr_sub_tile->equivalent_sites) {
+    for (t_logical_block_type_ptr eq_site : curr_sub_tile->equivalent_sites) {
         if (eq_site == curr_logical_block)
             break;
         offset += (int)eq_site->pin_logical_num_to_pb_pin_mapping.size();
@@ -255,13 +254,11 @@ static int get_pin_logical_num_from_pin_physical_num(t_physical_tile_type_ptr ph
     VTR_ASSERT(sub_tile_cap != -1);
     auto logical_block = get_logical_block_from_pin_physical_num(physical_tile, physical_num);
 
-    int pin_logical_num;
-
     int offset = get_logical_block_physical_pin_num_offset(physical_tile,
                                                            sub_tile,
                                                            logical_block,
                                                            sub_tile_cap);
-    pin_logical_num = physical_num - offset;
+    int pin_logical_num = physical_num - offset;
 
     return pin_logical_num;
 }
@@ -273,7 +270,6 @@ static std::vector<int> get_pb_pin_src_pins(t_physical_tile_type_ptr physical_ty
                                             const t_pb_graph_pin* pin) {
     std::vector<int> driving_pins;
     const auto& edges = pin->input_edges;
-    t_pb_graph_pin** connected_pins_ptr;
     int num_edges = pin->num_input_edges;
     int num_pins = 0;
 
@@ -285,7 +281,7 @@ static std::vector<int> get_pb_pin_src_pins(t_physical_tile_type_ptr physical_ty
 
     for (int edge_idx = 0; edge_idx < num_edges; edge_idx++) {
         const t_pb_graph_edge* pb_graph_edge = edges[edge_idx];
-        connected_pins_ptr = pb_graph_edge->input_pins;
+        t_pb_graph_pin** connected_pins_ptr = pb_graph_edge->input_pins;
         num_pins = pb_graph_edge->num_input_pins;
 
         for (int pin_idx = 0; pin_idx < num_pins; pin_idx++) {
@@ -315,7 +311,6 @@ static std::vector<int> get_pb_pin_sink_pins(t_physical_tile_type_ptr physical_t
                                              const t_pb_graph_pin* pin) {
     std::vector<int> sink_pins;
     const auto& edges = pin->output_edges;
-    t_pb_graph_pin** connected_pins_ptr;
     int num_edges = pin->num_output_edges;
     int num_pins = 0;
 
@@ -327,7 +322,7 @@ static std::vector<int> get_pb_pin_sink_pins(t_physical_tile_type_ptr physical_t
 
     for (int edge_idx = 0; edge_idx < num_edges; edge_idx++) {
         const t_pb_graph_edge* pb_graph_edge = edges[edge_idx];
-        connected_pins_ptr = pb_graph_edge->output_pins;
+        t_pb_graph_pin** connected_pins_ptr = pb_graph_edge->output_pins;
         num_pins = pb_graph_edge->num_output_pins;
 
         for (int pin_idx = 0; pin_idx < num_pins; pin_idx++) {
@@ -392,12 +387,12 @@ static int get_num_reachable_sinks(t_physical_tile_type_ptr physical_tile,
     const auto& connected_sinks = pb_pin->connected_sinks_ptc;
 
     // If ref_sink_num is not reachable by pin_physical_num return 0
-    if (connected_sinks.find(ref_sink_num) == connected_sinks.end()) {
+    if (!connected_sinks.contains(ref_sink_num)) {
         return 0;
     }
 
     for (auto sink_num : sink_grp) {
-        if (connected_sinks.find(sink_num) != connected_sinks.end()) {
+        if (connected_sinks.contains(sink_num)) {
             num_reachable_sinks++;
         }
     }
@@ -431,7 +426,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_
     int sub_tile_index = ARCH_FPGA_UNDEFINED_VAL;
     for (const auto& sub_tile : physical_tile->sub_tiles) {
         auto eq_sites = sub_tile.equivalent_sites;
-        auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block);
+        auto it = std::ranges::find(eq_sites, logical_block);
         if (it != eq_sites.end()) {
             sub_tile_index = sub_tile.index;
         }
@@ -467,7 +462,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_
     int sub_tile_index = ARCH_FPGA_UNDEFINED_VAL;
     for (const auto& sub_tile : physical_tile->sub_tiles) {
         auto eq_sites = sub_tile.equivalent_sites;
-        auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block);
+        auto it = std::ranges::find(eq_sites, logical_block);
         if (it != eq_sites.end()
             && (sub_tile.capacity.is_in_range(sub_tile_capacity))) {
             sub_tile_index = sub_tile.index;
@@ -497,13 +492,13 @@ t_logical_block_type_ptr pick_logical_type(t_physical_tile_type_ptr physical_til
 
 bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block) {
     const auto& equivalent_tiles = logical_block->equivalent_tiles;
-    return std::find(equivalent_tiles.begin(), equivalent_tiles.end(), physical_tile) != equivalent_tiles.end();
+    return std::ranges::find(equivalent_tiles, physical_tile) != equivalent_tiles.end();
 }
 
 bool is_sub_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int sub_tile_loc) {
     bool capacity_compatible = false;
-    for (auto& sub_tile : physical_tile->sub_tiles) {
-        auto result = std::find(sub_tile.equivalent_sites.begin(), sub_tile.equivalent_sites.end(), logical_block);
+    for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
+        auto result = std::ranges::find(sub_tile.equivalent_sites, logical_block);
 
         if (sub_tile.capacity.is_in_range(sub_tile_loc) && result != sub_tile.equivalent_sites.end()) {
             capacity_compatible = true;
@@ -691,14 +686,14 @@ std::vector<std::string> block_type_class_index_to_pin_names(t_physical_tile_typ
         return lhs.pin_physical_num < rhs.pin_physical_num;
     };
 
-    //Ensure all the pins are in order
-    std::sort(pin_info.begin(), pin_info.end(), cmp);
+    // Ensure all the pins are in order
+    std::ranges::sort(pin_info, cmp);
 
-    //Determine ranges for each capacity instance and port pair
+    // Determine ranges for each capacity instance and port pair
     std::map<std::tuple<int, int, int, int, int>, std::array<int, 4>> pin_ranges;
     for (const auto& pin_inf : pin_info) {
         auto key = std::make_tuple(pin_inf.sub_tile_index, pin_inf.capacity_instance, pin_inf.logical_block_index, pin_inf.pb_type_idx, pin_inf.port_index);
-        if (!pin_ranges.count(key)) {
+        if (!pin_ranges.contains(key)) {
             pin_ranges[key][0] = pin_inf.pin_index_in_port;
             pin_ranges[key][1] = pin_inf.pin_index_in_port;
             pin_ranges[key][2] = pin_inf.pin_physical_num;
@@ -1304,7 +1299,7 @@ float get_pin_primitive_comb_delay(t_physical_tile_type_ptr physical_type,
                                                                     pin_physical_num);
     VTR_ASSERT(pb_pin->is_primitive_pin());
 
-    auto it = std::max_element(pb_pin->pin_timing_del_max.begin(), pb_pin->pin_timing_del_max.end());
+    auto it = std::ranges::max_element(pb_pin->pin_timing_del_max);
 
     if (it == pb_pin->pin_timing_del_max.end()) {
         return 0.;
@@ -1323,9 +1318,9 @@ bool classes_in_same_block(t_physical_tile_type_ptr physical_tile,
     }
 
     // Two functions are considered to be in the same group if share at least two level of blocks
-    const int NUM_SIMILAR_PB_NODE_THRESHOLD = 2;
-    auto first_class_pin_list = get_pin_list_from_class_physical_num(physical_tile, first_class_ptc_num);
-    auto second_class_pin_list = get_pin_list_from_class_physical_num(physical_tile, second_class_ptc_num);
+    constexpr int NUM_SIMILAR_PB_NODE_THRESHOLD = 2;
+    std::vector<int> first_class_pin_list = get_pin_list_from_class_physical_num(physical_tile, first_class_ptc_num);
+    std::vector<int> second_class_pin_list = get_pin_list_from_class_physical_num(physical_tile, second_class_ptc_num);
 
     auto first_pb_graph_pin = get_pb_pin_from_pin_physical_num(physical_tile, first_class_pin_list[0]);
     auto second_pb_graph_pin = get_pb_pin_from_pin_physical_num(physical_tile, second_class_pin_list[0]);
@@ -1340,7 +1335,7 @@ bool classes_in_same_block(t_physical_tile_type_ptr physical_tile,
     int num_shared_pb_graph_node = 0;
     curr_pb_graph_node = second_pb_graph_pin->parent_node;
     while (curr_pb_graph_node != nullptr) {
-        auto find_res = std::find(first_pb_graph_node_chain.begin(), first_pb_graph_node_chain.end(), curr_pb_graph_node);
+        auto find_res = std::ranges::find(first_pb_graph_node_chain, curr_pb_graph_node);
         if (find_res != first_pb_graph_node_chain.end()) {
             num_shared_pb_graph_node++;
             if (num_shared_pb_graph_node >= NUM_SIMILAR_PB_NODE_THRESHOLD)
diff --git a/libs/librrgraph/src/base/rr_graph_utils.cpp b/libs/librrgraph/src/base/rr_graph_utils.cpp
@@ -180,7 +180,7 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil
 
         // See if we have encountered this tile type/ptc combo before, and used saved offset if so
         vtr::Point<int> new_loc(-1, -1);
-        if ((physical_type_offsets.find(tile_type) != physical_type_offsets.end()) && (physical_type_offsets[tile_type].find(node_ptc) != physical_type_offsets[tile_type].end())) {
+        if (physical_type_offsets.contains(tile_type) && physical_type_offsets[tile_type].contains(node_ptc)) {
             new_loc = tile_bb.bottom_left() + physical_type_offsets[tile_type].at(node_ptc);
         } else { /* We have not seen this tile type/ptc combo before */
             // The IPINs of the current SINK node
@@ -197,7 +197,7 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil
             std::vector<float> y_coords;
 
             // Add coordinates of each "cluster-edge" pin to vectors
-            for (const auto& pin : sink_ipins) {
+            for (const RRNodeId pin : sink_ipins) {
                 int pin_x = rr_graph.node_xlow(pin);
                 int pin_y = rr_graph.node_ylow(pin);
 
@@ -212,7 +212,7 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil
                        (int)round(std::accumulate(y_coords.begin(), y_coords.end(), 0.f) / (double)y_coords.size())};
 
             // Save offset for this tile/ptc combo
-            if (physical_type_offsets.find(tile_type) == physical_type_offsets.end())
+            if (!physical_type_offsets.contains(tile_type))
                 physical_type_offsets[tile_type] = {};
 
             physical_type_offsets[tile_type].insert({node_ptc, new_loc - tile_bb.bottom_left()});
diff --git a/vpr/src/route/rr_graph_generation/build_switchblocks.cpp b/vpr/src/route/rr_graph_generation/build_switchblocks.cpp
@@ -390,7 +390,7 @@ static void compute_wire_connections(const t_physical_tile_loc& sb_loc,
     }
 
     // Check that the permutation map has an entry for this side combination
-    if (sb.permutation_map.count(side_conn) == 0) {
+    if (!sb.permutation_map.contains(side_conn)) {
         // The specified switchblock does not have any permutation funcs for `from_side` to `to_side` connection
         return;
     }
diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp
@@ -2,6 +2,7 @@
 #include <regex>
 #include <algorithm>
 #include <sstream>
+#include <ranges>
 
 #include "pack_types.h"
 #include "vpr_types.h"
@@ -415,7 +416,7 @@ int get_sub_tile_index(ClusterBlockId blk,
 
     for (const auto& sub_tile : type->sub_tiles) {
         if (sub_tile.capacity.is_in_range(sub_tile_coordinate)) {
-            auto result = std::find(sub_tile.equivalent_sites.begin(), sub_tile.equivalent_sites.end(), logical_block);
+            auto result = std::ranges::find(sub_tile.equivalent_sites, logical_block);
             if (result == sub_tile.equivalent_sites.end()) {
                 VPR_THROW(VPR_ERROR_PLACE, "The Block Id %d has been placed in an incompatible sub tile location.\n", blk);
             }
@@ -596,7 +597,7 @@ t_logical_block_type_ptr infer_logic_block_type(const DeviceGrid& grid) {
             rhs_num_instances += grid.num_instances(type, -1);
         return lhs_num_instances > rhs_num_instances;
     };
-    std::stable_sort(logic_block_candidates.begin(), logic_block_candidates.end(), by_desc_grid_count);
+    std::ranges::stable_sort(logic_block_candidates, by_desc_grid_count);
 
     if (!logic_block_candidates.empty()) {
         return logic_block_candidates.front();
@@ -1061,7 +1062,7 @@ vtr::vector<ClusterBlockId, t_pb**> alloc_and_load_pin_id_to_pb_mapping() {
     auto& cluster_ctx = g_vpr_ctx.clustering();
 
     vtr::vector<ClusterBlockId, t_pb**> pin_id_to_pb_mapping(cluster_ctx.clb_nlist.blocks().size());
-    for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
+    for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) {
         pin_id_to_pb_mapping[blk_id] = new t_pb*[cluster_ctx.clb_nlist.block_type(blk_id)->pb_graph_head->total_pb_pins];
         for (int j = 0; j < cluster_ctx.clb_nlist.block_type(blk_id)->pb_graph_head->total_pb_pins; j++) {
             pin_id_to_pb_mapping[blk_id][j] = nullptr;
@@ -1248,7 +1249,7 @@ int num_ext_inputs_atom_block(AtomBlockId blk_id) {
     //Look through the output nets for any duplicates of the input nets
     for (auto pin_id : atom_ctx.netlist().block_output_pins(blk_id)) {
         auto net_id = atom_ctx.netlist().pin_net(pin_id);
-        if (input_nets.count(net_id)) {
+        if (input_nets.contains(net_id)) {
             --ext_inps;
         }
     }
@@ -1273,20 +1274,17 @@ void free_pb(t_pb* pb, AtomPBBimap& atom_pb_bimap) {
         return;
     }
 
-    const t_pb_type* pb_type;
-    int i, j, mode;
-
-    pb_type = pb->pb_graph_node->pb_type;
+    const t_pb_type* pb_type = pb->pb_graph_node->pb_type;
 
     if (pb->name) {
         free(pb->name);
         pb->name = nullptr;
     }
 
     if (pb_type->blif_model == nullptr) {
-        mode = pb->mode;
-        for (i = 0; i < pb_type->modes[mode].num_pb_type_children && pb->child_pbs != nullptr; i++) {
-            for (j = 0; j < pb_type->modes[mode].pb_type_children[i].num_pb && pb->child_pbs[i] != nullptr; j++) {
+        int mode = pb->mode;
+        for (int i = 0; i < pb_type->modes[mode].num_pb_type_children && pb->child_pbs != nullptr; i++) {
+            for (int j = 0; j < pb_type->modes[mode].pb_type_children[i].num_pb && pb->child_pbs[i] != nullptr; j++) {
                 if (pb->child_pbs[i][j].name != nullptr || pb->child_pbs[i][j].child_pbs != nullptr) {
                     free_pb(&pb->child_pbs[i][j], atom_pb_bimap);
                 }
@@ -1354,7 +1352,7 @@ std::tuple<int, int, std::string, std::string> parse_direct_pin_name(std::string
 
         std::string source_string{src_string};
         // replace '.' characters with space
-        std::replace(source_string.begin(), source_string.end(), '.', ' ');
+        std::ranges::replace(source_string, '.', ' ');
 
         std::istringstream source_iss(source_string);
         std::string pb_type_name, port_name;
@@ -1374,8 +1372,7 @@ std::tuple<int, int, std::string, std::string> parse_direct_pin_name(std::string
         std::string source_string{src_string};
 
         // Replace '.' and '[' characters with ' '
-        std::replace_if(
-            source_string.begin(), source_string.end(),
+        std::ranges::replace_if(source_string,
             [](char c) { return c == '.' || c == '[' || c == ':' || c == ']'; },
             ' ');
 
@@ -1479,18 +1476,18 @@ void print_switch_usage() {
             // Assumption: suppose for a L4 wire (bi-directional): ----+----+----+----, it can be driven from any point (0, 1, 2, 3).
             //             physically, the switch driving from point 1 & 3 should be the same. But we will assign then different switch
             //             index; or there is no way to differentiate them after abstracting a 2D wire into a 1D node
-            if (inward_switch_inf[to_node_index].count(switch_index) == 0)
+            if (!inward_switch_inf[to_node_index].contains(switch_index))
                 inward_switch_inf[to_node_index][switch_index] = 0;
             //VTR_ASSERT(from_node.type != OPIN);
             inward_switch_inf[to_node_index][switch_index]++;
         }
     }
 
     for (const RRNodeId rr_id : device_ctx.rr_graph.nodes()) {
-        for (const auto [rr_switch_id, node_switch_fanin] : inward_switch_inf[rr_id]) {
+        for (const RRSwitchId rr_switch_id : inward_switch_inf[rr_id] | std::views::keys) {
             float Tdel = rr_graph.rr_switch_inf(rr_switch_id).Tdel;
             const auto [arch_switch_id, fanin] = convert_switch_index(rr_switch_id);
-            if (switch_fanin_count[arch_switch_id].count(fanin) == 0) {
+            if (!switch_fanin_count[arch_switch_id].contains(fanin)) {
                 switch_fanin_count[arch_switch_id][fanin] = 0;
             }
             switch_fanin_count[arch_switch_id][fanin]++;

Original file line number	Diff line number	Diff line change
`@@ -390,7 +390,7 @@ static void compute_wire_connections(const t_physical_tile_loc& sb_loc,`
`390`	`390`	`}`
`391`	`391`
`392`	`392`	`// Check that the permutation map has an entry for this side combination`
`393`		`- if (sb.permutation_map.count(side_conn) == 0) {`
	`393`	`+ if (!sb.permutation_map.contains(side_conn)) {`
`394`	`394`	// The specified switchblock does not have any permutation funcs for `from_side` to `to_side` connection
`395`	`395`	`return;`
`396`	`396`	`}`