make format

Author: soheilshahrouz

vpr/src/draw/draw.cpp

@@ -509,7 +509,7 @@ void init_draw_coords(float clb_width, const BlkLocRegistry& blk_loc_registry) {
 
     // Load coordinates of sub-blocks inside the clbs
     draw_internal_init_blk();
-    
+
 #else
     (void)clb_width;
     (void)blk_loc_registry;

vpr/src/draw/draw_rr_edges.cpp

@@ -58,7 +58,7 @@ void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, RRSwitchId r
             if (rr_graph.node_direction(to_node) == Direction::INC) { // INC wire starts at bottom edge
                 if (rr_graph.node_direction(from_node) == Direction::DEC) {
                     y2 = to_chan.bottom();
-                    y1 = draw_coords->tile_y[to_ylow] + 0.1 * draw_coords->get_tile_height() ;
+                    y1 = draw_coords->tile_y[to_ylow] + 0.1 * draw_coords->get_tile_height();
                 } else {
                     VTR_ASSERT_SAFE(rr_graph.node_direction(from_node) == Direction::INC);
                     y2 = to_chan.bottom();

vpr/src/route/rr_graph_generation/clb2clb_directs.cpp

@@ -34,7 +34,7 @@ std::vector<t_clb_to_clb_directs> alloc_and_load_clb_to_clb_directs(const std::v
 
         t_physical_tile_port tile_port = find_tile_port_by_name(physical_tile, port_name);
         /* Find the sub tile indices */
-        clb_to_clb_directs[i].from_sub_tiles = find_sub_tile_indices_by_port_name(physical_tile, port_name); 
+        clb_to_clb_directs[i].from_sub_tiles = find_sub_tile_indices_by_port_name(physical_tile, port_name);
         if (clb_to_clb_directs[i].from_sub_tiles.empty()) {
             VPR_THROW(VPR_ERROR_ARCH, "Unable to find sub tile under tile '%s' which contains the port %s.\n", tile_name.c_str(), port_name.data());
         }

vpr/src/route/rr_graph_generation/rr_graph.cpp

@@ -3094,7 +3094,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder,
     auto [z, relative_opin] = get_capacity_location_from_physical_pin(curr_type, opin);
     VTR_ASSERT(z >= 0 && z < curr_type->capacity);
     const int num_directs = directs.size();
-    
+
     // Iterate through all direct connections
     for (int i = 0; i < num_directs; i++) {
         // Find matching direct clb-to-clb connections with the same type as current grid location

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp

@@ -1756,14 +1756,14 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph,
                      */
                     std::vector<e_side> opin_grid_side = find_grid_pin_sides(grids, layer, from_grid_coordinate.x() + grid_type->pin_width_offset[opin], from_grid_coordinate.y() + grid_type->pin_height_offset[opin], opin);
                     if (1 != opin_grid_side.size()) {
-                      VPR_FATAL_ERROR(VPR_ERROR_ARCH, "[Arch LINE %d] From pin (index=%d) of direct connection '%s' does not exist on any side of the programmable block '%s'.\n", directs[i].line, opin, directs[i].from_pin.c_str());
+                        VPR_FATAL_ERROR(VPR_ERROR_ARCH, "[Arch LINE %d] From pin (index=%d) of direct connection '%s' does not exist on any side of the programmable block '%s'.\n", directs[i].line, opin, directs[i].from_pin.c_str());
                     }
 
                     /* directs[i].sub_tile_offset is added to from_capacity(z) to get the target_capacity */
                     int to_subtile_cap = z + directs[i].sub_tile_offset;
                     /* If the destination subtile is out of range, there is no qualified IPINs */
                     if (to_subtile_cap < 0 || to_subtile_cap >= to_grid_type->capacity) {
-                      continue;
+                        continue;
                     }
                     /* Iterate over all sub_tiles to get the sub_tile which the target_cap belongs to. */
                     const t_sub_tile* to_sub_tile = nullptr;
@@ -1780,7 +1780,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph,
                     int ipin = get_physical_pin_from_capacity_location(to_grid_type, relative_ipin, to_subtile_cap);
                     std::vector<e_side> ipin_grid_side = find_grid_pin_sides(grids, layer, to_grid_coordinate.x() + to_grid_type->pin_width_offset[ipin], to_grid_coordinate.y() + to_grid_type->pin_height_offset[ipin], ipin);
                     if (1 != ipin_grid_side.size()) {
-                      VPR_FATAL_ERROR(VPR_ERROR_ARCH, "[Arch LINE %d] To pin (index=%d) of direct connection '%s' does not exist on any side of the programmable block '%s'.\n", directs[i].line, relative_ipin, directs[i].to_pin.c_str());
+                        VPR_FATAL_ERROR(VPR_ERROR_ARCH, "[Arch LINE %d] To pin (index=%d) of direct connection '%s' does not exist on any side of the programmable block '%s'.\n", directs[i].line, relative_ipin, directs[i].to_pin.c_str());
                     }
 
                     RRNodeId opin_node_id = rr_graph.node_lookup().find_node(layer,
@@ -1794,10 +1794,10 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph,
 
                     /* add edges to the opin_node */
                     if (!opin_node_id) {
-                      VTR_ASSERT(opin_node_id);
+                        VTR_ASSERT(opin_node_id);
                     }
                     if (!ipin_node_id) {
-                      VTR_ASSERT(opin_node_id);
+                        VTR_ASSERT(opin_node_id);
                     }
                     rr_graph_builder.create_edge_in_cache(opin_node_id, ipin_node_id, RRSwitchId(clb_to_clb_directs[i].switch_index), false);
                 }