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soheilshahrouzsoheilshahrouz
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std::string for input/output_string in t_interconnect
1 parent 07a0f34 commit a2418f3

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6 files changed

+72
-137
lines changed

6 files changed

+72
-137
lines changed

‎libs/libarchfpga/src/arch_util.cpp‎

Lines changed: 31 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -316,8 +316,6 @@ static void free_pb_type(t_pb_type* pb_type) {
316316
delete[] pb_type->modes[i].pb_type_children;
317317
vtr::free(pb_type->modes[i].name);
318318
for (int j = 0; j < pb_type->modes[i].num_interconnect; ++j) {
319-
vtr::free(pb_type->modes[i].interconnect[j].input_string);
320-
vtr::free(pb_type->modes[i].interconnect[j].output_string);
321319
vtr::free(pb_type->modes[i].interconnect[j].name);
322320

323321
pb_type->modes[i].interconnect[j].annotations.clear();
@@ -500,14 +498,14 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
500498

501499
/* populate special lut class */
502500
void ProcessLutClass(t_pb_type* lut_pb_type) {
503-
char* default_name;
501+
std::string default_name;
504502
t_port* in_port;
505503
t_port* out_port;
506504

507505
if (strcmp(lut_pb_type->name, "lut") != 0) {
508-
default_name = vtr::strdup("lut");
506+
default_name = "lut";
509507
} else {
510-
default_name = vtr::strdup("lut_child");
508+
default_name = "lut_child";
511509
}
512510

513511
lut_pb_type->num_modes = 2;
@@ -540,14 +538,8 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
540538
sprintf(lut_pb_type->modes[0].interconnect[0].name, "complete:%s",
541539
lut_pb_type->name);
542540
lut_pb_type->modes[0].interconnect[0].type = COMPLETE_INTERC;
543-
lut_pb_type->modes[0].interconnect[0].input_string = (char*)vtr::calloc(strlen(lut_pb_type->name) + strlen(in_port->name) + 2,
544-
sizeof(char));
545-
sprintf(lut_pb_type->modes[0].interconnect[0].input_string, "%s.%s",
546-
lut_pb_type->name, in_port->name);
547-
lut_pb_type->modes[0].interconnect[0].output_string = (char*)vtr::calloc(strlen(lut_pb_type->name) + strlen(out_port->name) + 2,
548-
sizeof(char));
549-
sprintf(lut_pb_type->modes[0].interconnect[0].output_string, "%s.%s",
550-
lut_pb_type->name, out_port->name);
541+
lut_pb_type->modes[0].interconnect[0].input_string = vtr::string_fmt("%s.%s", lut_pb_type->name, in_port->name);
542+
lut_pb_type->modes[0].interconnect[0].output_string = vtr::string_fmt("%s.%s", lut_pb_type->name, out_port->name);
551543

552544
lut_pb_type->modes[0].interconnect[0].parent_mode_index = 0;
553545
lut_pb_type->modes[0].interconnect[0].parent_mode = &lut_pb_type->modes[0];
@@ -592,13 +584,8 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
592584
sprintf(lut_pb_type->modes[1].interconnect[0].name, "direct:%s",
593585
lut_pb_type->name);
594586
lut_pb_type->modes[1].interconnect[0].type = DIRECT_INTERC;
595-
lut_pb_type->modes[1].interconnect[0].input_string = (char*)vtr::calloc(strlen(lut_pb_type->name) + strlen(in_port->name) + 2,
596-
sizeof(char));
597-
sprintf(lut_pb_type->modes[1].interconnect[0].input_string, "%s.%s",
598-
lut_pb_type->name, in_port->name);
599-
lut_pb_type->modes[1].interconnect[0].output_string = (char*)vtr::calloc(strlen(default_name) + strlen(in_port->name) + 2, sizeof(char));
600-
sprintf(lut_pb_type->modes[1].interconnect[0].output_string, "%s.%s",
601-
default_name, in_port->name);
587+
lut_pb_type->modes[1].interconnect[0].input_string = vtr::string_fmt(lut_pb_type->name, in_port->name);
588+
lut_pb_type->modes[1].interconnect[0].output_string = default_name + '.' + in_port->name;
602589
lut_pb_type->modes[1].interconnect[0].infer_annotations = true;
603590

604591
lut_pb_type->modes[1].interconnect[0].parent_mode_index = 1;
@@ -610,46 +597,35 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
610597
lut_pb_type->name);
611598

612599
lut_pb_type->modes[1].interconnect[1].type = DIRECT_INTERC;
613-
lut_pb_type->modes[1].interconnect[1].input_string = (char*)vtr::calloc(strlen(default_name) + strlen(out_port->name) + 4, sizeof(char));
614-
sprintf(lut_pb_type->modes[1].interconnect[1].input_string, "%s.%s",
615-
default_name, out_port->name);
616-
lut_pb_type->modes[1].interconnect[1].output_string = (char*)vtr::calloc(strlen(lut_pb_type->name) + strlen(out_port->name)
617-
+ strlen(in_port->name) + 2,
618-
sizeof(char));
619-
sprintf(lut_pb_type->modes[1].interconnect[1].output_string, "%s.%s",
620-
lut_pb_type->name, out_port->name);
600+
lut_pb_type->modes[1].interconnect[1].input_string = vtr::string_fmt("%s.%s", default_name, out_port->name);
601+
lut_pb_type->modes[1].interconnect[1].output_string = vtr::string_fmt("%s.%s", lut_pb_type->name, out_port->name);
621602
lut_pb_type->modes[1].interconnect[1].infer_annotations = true;
622603

623604
lut_pb_type->modes[1].interconnect[1].parent_mode_index = 1;
624605
lut_pb_type->modes[1].interconnect[1].parent_mode = &lut_pb_type->modes[1];
625606
lut_pb_type->modes[1].interconnect[1].interconnect_power = new t_interconnect_power();
626607

627-
free(default_name);
628-
629608
free(lut_pb_type->blif_model);
630609
lut_pb_type->blif_model = nullptr;
631610
lut_pb_type->model_id = LogicalModelId::INVALID();
632611
}
633612

634613
/* populate special memory class */
635614
void ProcessMemoryClass(t_pb_type* mem_pb_type) {
636-
char* default_name;
637-
char *input_name, *input_port_name, *output_name, *output_port_name;
638-
int i, j, i_inter, num_pb;
639-
615+
std::string default_name;
640616
if (strcmp(mem_pb_type->name, "memory_slice") != 0) {
641-
default_name = vtr::strdup("memory_slice");
617+
default_name = "memory_slice";
642618
} else {
643-
default_name = vtr::strdup("memory_slice_1bit");
619+
default_name = "memory_slice_1bit";
644620
}
645621

646622
mem_pb_type->modes = new t_mode[1];
647-
mem_pb_type->modes[0].name = vtr::strdup(default_name);
623+
mem_pb_type->modes[0].name = vtr::strdup(default_name.data());
648624
mem_pb_type->modes[0].parent_pb_type = mem_pb_type;
649625
mem_pb_type->modes[0].index = 0;
650626
mem_pb_type->modes[0].mode_power = new t_mode_power();
651-
num_pb = ARCH_FPGA_UNDEFINED_VAL;
652-
for (i = 0; i < mem_pb_type->num_ports; i++) {
627+
int num_pb = ARCH_FPGA_UNDEFINED_VAL;
628+
for (int i = 0; i < mem_pb_type->num_ports; i++) {
653629
if (mem_pb_type->ports[i].port_class != nullptr
654630
&& strstr(mem_pb_type->ports[i].port_class, "data")
655631
== mem_pb_type->ports[i].port_class) {
@@ -684,18 +660,19 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
684660
VTR_ASSERT_MSG(mem_pb_type->modes[0].num_interconnect > 0, error_msg.c_str());
685661
mem_pb_type->modes[0].interconnect = new t_interconnect[mem_pb_type->modes[0].num_interconnect];
686662

687-
for (i = 0; i < mem_pb_type->modes[0].num_interconnect; i++) {
663+
for (int i = 0; i < mem_pb_type->modes[0].num_interconnect; i++) {
688664
mem_pb_type->modes[0].interconnect[i].parent_mode_index = 0;
689665
mem_pb_type->modes[0].interconnect[i].parent_mode = &mem_pb_type->modes[0];
690666
}
691667

692668
/* Process interconnect */
693-
i_inter = 0;
694-
for (i = 0; i < mem_pb_type->num_ports; i++) {
669+
int i_inter = 0;
670+
for (int i = 0; i < mem_pb_type->num_ports; i++) {
695671
mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC;
696-
input_port_name = mem_pb_type->ports[i].name;
697-
output_port_name = mem_pb_type->ports[i].name;
672+
char* input_port_name = mem_pb_type->ports[i].name;
673+
char* output_port_name = mem_pb_type->ports[i].name;
698674

675+
std::string_view input_name, output_name;
699676
if (mem_pb_type->ports[i].type == IN_PORT) {
700677
input_name = mem_pb_type->name;
701678
output_name = default_name;
@@ -717,39 +694,21 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
717694
mem_pb_type->modes[0].pb_type_children[0].ports[i].num_pins = 1;
718695
mem_pb_type->modes[0].pb_type_children[0].num_input_pins -= (mem_pb_type->ports[i].num_pins - 1);
719696

720-
mem_pb_type->modes[0].interconnect[i_inter].input_string = (char*)vtr::calloc(strlen(input_name) + strlen(input_port_name)
721-
+ 2,
722-
sizeof(char));
723-
sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string,
724-
"%s.%s", input_name, input_port_name);
725-
mem_pb_type->modes[0].interconnect[i_inter].output_string = (char*)vtr::calloc(strlen(output_name) + strlen(output_port_name)
726-
+ 2 * (6 + num_pb / 10),
727-
sizeof(char));
728-
sprintf(mem_pb_type->modes[0].interconnect[i_inter].output_string,
729-
"%s[%d:0].%s", output_name, num_pb - 1,
730-
output_port_name);
697+
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name, input_port_name);
698+
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:0].%s", output_name, num_pb - 1, output_port_name);
731699
} else {
732700
/* force data pins to be one bit wide and update stats */
733701
mem_pb_type->modes[0].pb_type_children[0].ports[i].num_pins = 1;
734702
mem_pb_type->modes[0].pb_type_children[0].num_output_pins -= (mem_pb_type->ports[i].num_pins - 1);
735-
736-
mem_pb_type->modes[0].interconnect[i_inter].input_string = (char*)vtr::calloc(strlen(input_name) + strlen(input_port_name)
737-
+ 2 * (6 + num_pb / 10),
738-
sizeof(char));
739-
sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string,
740-
"%s[%d:0].%s", input_name, num_pb - 1, input_port_name);
741-
mem_pb_type->modes[0].interconnect[i_inter].output_string = (char*)vtr::calloc(strlen(output_name) + strlen(output_port_name)
742-
+ 2,
743-
sizeof(char));
744-
sprintf(mem_pb_type->modes[0].interconnect[i_inter].output_string,
745-
"%s.%s", output_name, output_port_name);
703+
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:0].%s", input_name, num_pb - 1, input_port_name);
704+
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name, output_port_name);
746705
}
747706

748707
/* Allocate interconnect power structures */
749708
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power();
750709
i_inter++;
751710
} else {
752-
for (j = 0; j < num_pb; j++) {
711+
for (int j = 0; j < num_pb; j++) {
753712
/* Anything that is not data must be an input */
754713
mem_pb_type->modes[0].interconnect[i_inter].name = (char*)vtr::calloc(i_inter / 10 + j / 10 + 10,
755714
sizeof(char));
@@ -759,30 +718,12 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
759718

760719
if (mem_pb_type->ports[i].type == IN_PORT) {
761720
mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC;
762-
mem_pb_type->modes[0].interconnect[i_inter].input_string = (char*)vtr::calloc(strlen(input_name) + strlen(input_port_name)
763-
+ 2,
764-
sizeof(char));
765-
sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string,
766-
"%s.%s", input_name, input_port_name);
767-
mem_pb_type->modes[0].interconnect[i_inter].output_string = (char*)vtr::calloc(strlen(output_name)
768-
+ strlen(output_port_name)
769-
+ 2 * (6 + num_pb / 10),
770-
sizeof(char));
771-
sprintf(mem_pb_type->modes[0].interconnect[i_inter].output_string,
772-
"%s[%d:%d].%s", output_name, j, j,
773-
output_port_name);
721+
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name, input_port_name);
722+
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:%d].%s", output_name, j, j, output_port_name);
774723
} else {
775724
mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC;
776-
mem_pb_type->modes[0].interconnect[i_inter].input_string = (char*)vtr::calloc(strlen(input_name) + strlen(input_port_name)
777-
+ 2 * (6 + num_pb / 10),
778-
sizeof(char));
779-
sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string,
780-
"%s[%d:%d].%s", input_name, j, j, input_port_name);
781-
mem_pb_type->modes[0].interconnect[i_inter].output_string = (char*)vtr::calloc(strlen(output_name)
782-
+ strlen(output_port_name) + 2,
783-
sizeof(char));
784-
sprintf(mem_pb_type->modes[0].interconnect[i_inter].output_string,
785-
"%s.%s", output_name, output_port_name);
725+
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:%d].%s", input_name, j, j, input_port_name);
726+
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name, output_port_name);
786727
}
787728

788729
/* Allocate interconnect power structures */
@@ -793,8 +734,6 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
793734
}
794735

795736
mem_pb_type->modes[0].num_interconnect = i_inter;
796-
797-
free(default_name);
798737
}
799738

800739
e_power_estimation_method power_method_inherited(e_power_estimation_method parent_power_method) {
@@ -950,7 +889,7 @@ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation,
950889
if (!clock_valid) {
951890
archfpga_throw(get_arch_file_name(), annotation->line_num,
952891
"Clock '%s' does not match any clock defined in pb_type '%s'.\n",
953-
annotation->clock, parent_pb_type->name);
892+
annotation->clock.c_str(), parent_pb_type->name);
954893
}
955894
}
956895

‎libs/libarchfpga/src/echo_arch.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -397,8 +397,8 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
397397
for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) {
398398
fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs.c_str(),
399399
pb_type->modes[i].interconnect[j].type,
400-
pb_type->modes[i].interconnect[j].input_string,
401-
pb_type->modes[i].interconnect[j].output_string);
400+
pb_type->modes[i].interconnect[j].input_string.c_str(),
401+
pb_type->modes[i].interconnect[j].output_string.c_str());
402402
for (const t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) {
403403
fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs.c_str(),
404404
annotation.input_pins.c_str(),

‎libs/libarchfpga/src/physical_types.h‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1108,8 +1108,8 @@ struct t_interconnect {
11081108
e_interconnect type;
11091109
char* name;
11101110

1111-
char* input_string;
1112-
char* output_string;
1111+
std::string input_string;
1112+
std::string output_string;
11131113

11141114
std::vector<t_pin_to_pin_annotation> annotations;
11151115
bool infer_annotations;
@@ -1127,8 +1127,6 @@ struct t_interconnect {
11271127
t_interconnect() {
11281128
type = (e_interconnect)0;
11291129
name = nullptr;
1130-
input_string = nullptr;
1131-
output_string = nullptr;
11321130
infer_annotations = false;
11331131
line_num = 0;
11341132
parent_mode_index = 0;

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