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separate tasks for fixed custom grid
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vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/config.txt

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circuit_list_add=raygentop.v
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# Add architectures to list to sweep
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arch_list_add=fixed_grid.xml
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arch_list_add=column_io.xml
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arch_list_add=multiwidth_blocks.xml
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arch_list_add=non_column.xml

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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fixed_grid.xml raygentop.v common 17.26 vpr 85.18 MiB -1 -1 1.99 42340 4 0.56 -1 -1 36976 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 87220 236 305 3177 2989 1 1517 675 25 25 625 -1 25x25 46.3 MiB 2.03 30552.8 14077 237395 78558 156700 2137 85.2 MiB 1.24 0.02 6.54728 4.56956 -2883.52 -4.56956 4.56956 0.59 0.00510036 0.0045553 0.478327 0.433095 -1 -1 -1 -1 56 26200 45 3.19446e+07 9.76854e+06 2.27235e+06 3635.76 7.42 1.96901 1.80319 68115 457904 -1 22555 19 6811 19098 2015069 507374 4.83769 4.83769 -3127.42 -4.83769 0 0 2.89946e+06 4639.14 0.10 0.64 0.31 -1 -1 0.10 0.288232 0.270013
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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column_io.xml raygentop.v common 17.82 vpr 84.73 MiB -1 -1 1.83 42716 4 0.55 -1 -1 36980 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 86760 236 305 3177 2989 1 1517 675 25 25 625 io auto 45.9 MiB 2.03 28735.7 12823 269944 91841 150002 28101 84.7 MiB 1.31 0.02 6.40411 4.48404 -2791.58 -4.48404 4.48404 0.52 0.00521698 0.00467311 0.509336 0.461746 -1 -1 -1 -1 56 25953 39 2.82259e+07 9.76854e+06 2.10191e+06 3363.06 8.45 2.51155 2.29649 61008 409515 -1 22418 17 6198 16171 1634792 415988 4.80994 4.80994 -3067.42 -4.80994 0 0 2.68365e+06 4293.83 0.09 0.57 0.28 -1 -1 0.09 0.272003 0.256238
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multiwidth_blocks.xml raygentop.v common 17.23 vpr 84.99 MiB -1 -1 1.90 42532 4 0.57 -1 -1 36716 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 87028 236 305 3177 2989 1 1517 675 19 19 361 io clb auto 45.9 MiB 1.98 26256.7 13417 228518 71674 152513 4331 85.0 MiB 1.15 0.02 6.15992 4.61893 -2885.89 -4.61893 4.61893 0.26 0.0053293 0.00477846 0.433268 0.393945 -1 -1 -1 -1 64 25958 35 1.65001e+07 9.76854e+06 1.21492e+06 3365.43 8.56 2.43954 2.22189 35881 226057 -1 21615 21 6791 19110 2067703 557503 4.85645 4.85645 -3124.54 -4.85645 0 0 1.53033e+06 4239.13 0.05 0.64 0.16 -1 -1 0.05 0.302016 0.284216
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non_column.xml raygentop.v common 18.43 vpr 98.71 MiB -1 -1 2.19 42532 4 0.55 -1 -1 36960 -1 -1 129 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 101080 236 305 3170 2982 1 1517 677 33 33 1089 io auto 47.8 MiB 2.08 37578.8 15176 276980 99233 136480 41267 97.2 MiB 1.29 0.02 7.54198 5.00926 -2873.75 -5.00926 5.00926 1.01 0.00471858 0.00431736 0.481962 0.436402 -1 -1 -1 -1 54 29848 41 5.44432e+07 9.87633e+06 3.30487e+06 3034.77 6.91 1.81197 1.64433 100302 649205 -1 25026 20 7001 18961 1915485 504481 5.15555 5.15555 -3132.11 -5.15555 0 0 4.28921e+06 3938.67 0.17 0.64 0.56 -1 -1 0.17 0.283887 0.264969
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##############################################
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# Configuration file for running experiments
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##############################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/verilog
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# Path to directory of architectures to use
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archs_dir=arch/custom_grid
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# Add circuits to list to sweep
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circuit_list_add=raygentop.v
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# Add architectures to list to sweep
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arch_list_add=fixed_grid.xml
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# Parse info and how to parse
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parse_file=vpr_standard.txt
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# How to parse QoR info
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qor_parse_file=qor_standard.txt
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# Pass requirements
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pass_requirements_file=pass_requirements.txt
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# Script parameters
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script_params =--device "25x25"
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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fixed_grid.xml raygentop.v common 17.26 vpr 85.18 MiB -1 -1 1.99 42340 4 0.56 -1 -1 36976 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 87220 236 305 3177 2989 1 1517 675 25 25 625 -1 25x25 46.3 MiB 2.03 30552.8 14077 237395 78558 156700 2137 85.2 MiB 1.24 0.02 6.54728 4.56956 -2883.52 -4.56956 4.56956 0.59 0.00510036 0.0045553 0.478327 0.433095 -1 -1 -1 -1 56 26200 45 3.19446e+07 9.76854e+06 2.27235e+06 3635.76 7.42 1.96901 1.80319 68115 457904 -1 22555 19 6811 19098 2015069 507374 4.83769 4.83769 -3127.42 -4.83769 0 0 2.89946e+06 4639.14 0.10 0.64 0.31 -1 -1 0.10 0.288232 0.270013

vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

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regression_tests/vtr_reg_strong/strong_cluster_seed_type
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regression_tests/vtr_reg_strong/strong_constant_outputs
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regression_tests/vtr_reg_strong/strong_custom_grid
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regression_tests/vtr_reg_strong/strong_custom_grid_fixed
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regression_tests/vtr_reg_strong/strong_custom_pin_locs
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regression_tests/vtr_reg_strong/strong_custom_switch_block
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regression_tests/vtr_reg_strong/strong_custom_sb_loc

vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/config.txt

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circuit_list_add=raygentop.v
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# Add architectures to list to sweep
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arch_list_add=fixed_grid.xml
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arch_list_add=column_io.xml
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arch_list_add=multiwidth_blocks.xml
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arch_list_add=non_column.xml

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