Merge pull request #3355 from AlexandreSinger/feature-spelling

[Spelling] Fixed Spelling in the Libs Directory

Author: AlexandreSinger

libs/libarchfpga/arch/mult_luts_arch.xml

@@ -140,7 +140,7 @@
   </device>
   <switchlist>
     <switch type="mux" name="0" R="94.841003" Cin="1.537000e-14" Cout="2.194000e-13" Tdel="6.562000e-11" mux_trans_size="10.000000" buf_size="1"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <!--switch ipin_cblock resistance set to yield for 4x minimum drive strength buffer-->
     <switch type="mux" name="ipin_cblock" R="1431.71752925" Cout="0." Cin="1.191000e-14" Tdel="1.482000e-10" mux_trans_size="1.000000" buf_size="auto"/>
   </switchlist>
   <segmentlist>

libs/libarchfpga/arch/sample_arch.xml

@@ -51,7 +51,7 @@
   & delay of the Stratix IV crossbar as a good approximation of our crossbar.
 
   For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  delays measured from Stratix IV which is dependent on the input used (ie. some 
   LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
   not consider differences in LUT input delays.
 
@@ -256,7 +256,7 @@
 	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
 	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
     <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <!--switch ipin_cblock resistance set to yield for 4x minimum drive strength buffer-->
     <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
   </switchlist>
   <segmentlist>

libs/libarchfpga/src/arch_check.h

@@ -55,7 +55,7 @@ void warn_model_missing_timing(const t_model& model, const char* file, uint32_t
 void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_sub_tile* sub_tile, t_logical_block_type_ptr logical_block);
 
 /**
- * @brief Checks the timing consistency between tha pb_type and the corresponding model.
+ * @brief Checks the timing consistency between a pb_type and the corresponding model.
  *
  * @param pb_type pb type to check
  * @param arch architecture data structure

libs/libarchfpga/src/arch_util.cpp

@@ -1148,7 +1148,7 @@ void setup_pin_classes(t_physical_tile_type* type) {
                         // as ignored pins (i.e. connections are not created in the rr_graph and
                         // nets connected to the port are ignored as well).
                         type->is_ignored_pin[pin_count] = port.is_clock || port.is_non_clock_global;
-                        // clock pins and other specified global ports are flaged as global
+                        // clock pins and other specified global ports are flagged as global
                         type->is_pin_global[pin_count] = port.is_clock || port.is_non_clock_global;
 
                         if (port.is_clock) {

libs/libarchfpga/src/echo_arch.cpp

@@ -23,7 +23,7 @@ static void PrintPb_types_recPower(FILE* Echo,
                                    const char* tabs);
 
 /* Output the data from architecture data so user can verify it
- * was interpretted correctly. */
+ * was interpreted correctly. */
 void EchoArch(const char* EchoFile,
               const std::vector<t_physical_tile_type>& PhysicalTileTypes,
               const std::vector<t_logical_block_type>& LogicalBlockTypes,
@@ -420,7 +420,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
     } else { /*leaf pb with unknown model*/
         /*LUT(names) already handled, it naturally has 2 modes.
          * I/O has no annotations to be displayed
-         * All other library or user models may have delays specificied, e.g. Tsetup and Tcq
+         * All other library or user models may have delays specified, e.g. Tsetup and Tcq
          * Display the additional information*/
         std::string pb_type_model_name = models.get_model(pb_type->model_id).name;
         if (pb_type_model_name != LogicalModels::MODEL_NAMES
@@ -633,7 +633,7 @@ static void PrintPb_types_recPower(FILE* Echo,
                         pb_type->pb_type_power->absolute_power_per_instance.dynamic);
             break;
         default:
-            fprintf(Echo, "%s\tpower method: error has occcured\n", tabs);
+            fprintf(Echo, "%s\tpower method: error has occcurred\n", tabs);
             break;
     }
 }

libs/libarchfpga/src/logic_types.h

@@ -92,7 +92,7 @@ typedef vtr::StrongId<struct logical_model_id_tag, size_t> LogicalModelId;
  *
  * There are two types of logical models:
  *  1) Library Models: These are models that all architectures share. These are
- *                     created in the construtor of this class.
+ *                     created in the constructor of this class.
  *  2) User Models: These are models defined by the user and are created outside
  *                  of this class (usually by parsing an architecture file).
  */

libs/libarchfpga/src/physical_types.h

@@ -494,7 +494,7 @@ enum class e_sb_type {
  * pin_avg_width_offset: Average width offset to specified pin (exact if only a single physical pin instance)
  * pin_avg_height_offset: Average height offset to specified pin (exact if only a single physical pin instance)
  * pin_class: The class a pin belongs to
- * is_ignored_pin: Whether or not a pin is ignored durring rr_graph generation and routing.
+ * is_ignored_pin: Whether or not a pin is ignored during rr_graph generation and routing.
  *                 This is usually the case for clock pins and other global pins unless the
  *                 clock_modeling option is set to route the clock through regular inter-block
  *                 wiring or through a dedicated clock network.
@@ -998,7 +998,7 @@ struct t_pb_type {
      * @brief Check if t_pb_type is the root of the pb graph. Root pb_types correspond to a single top level block type and map to a particular type
      * of location in the FPGA device grid (e.g. Logic, DSP, RAM etc.)
      *
-     * @return if t_pb_type is root ot not
+     * @return if t_pb_type is root or not
      */
     inline bool is_root() const {
         return parent_mode == nullptr;
@@ -1007,7 +1007,7 @@ struct t_pb_type {
     /**
      * @brief Check if t_pb_type is a primitive block or equivalently a leaf of the pb graph.
      *
-     * @return if t_pb_type is primitive/leaf ot not
+     * @return if t_pb_type is primitive/leaf or not
      */
     inline bool is_primitive() const {
         return num_modes == 0;
@@ -1298,8 +1298,8 @@ class t_pb_graph_node {
      *          as well), but LUTs A, B and C could still be routed using the parent pb_graph_node's mode "LUTRAM".
      *          Therefore, "LUTs" is marked as illegal and all the LUTs (A, B, C and D) will have a consistent parent pb_graph_node mode, namely "LUTRAM".
      *
-     * Usage: cluster_router uses this information to exclude the expansion of a node which has a not cosistent mode.
-     *        Everytime the mode consistency check fails, the index of the mode that causes the conflict is added to this vector.
+     * Usage: cluster_router uses this information to exclude the expansion of a node which has a not consistent mode.
+     *        Every time the mode consistency check fails, the index of the mode that causes the conflict is added to this vector.
      * */
     std::vector<int> illegal_modes;
 
@@ -1975,7 +1975,7 @@ struct t_arch {
     bool shrink_boundary;
 
     /// Allow routing channels to pass through multi-width and
-    /// multi-height programable blocks
+    /// multi-height programmable blocks
     bool through_channel;
 
     /// Allow each output pin of a programmable block to drive the

libs/libarchfpga/src/physical_types_util.cpp

@@ -661,7 +661,7 @@ std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_
         return pin_name;
     }
 
-    return "<UNKOWN>";
+    return "<UNKNOWN>";
 }
 
 std::vector<std::string> block_type_class_index_to_pin_names(t_physical_tile_type_ptr type,

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -2304,7 +2304,7 @@ struct ArchReader {
         /*
          * The generic architecture data is not currently available in the interchange format
          * therefore, for a very initial implementation, the values are taken from the ones
-         * used primarly in the Xilinx series7 devices, generated using SymbiFlow.
+         * used primarily in the Xilinx series7 devices, generated using SymbiFlow.
          *
          * As the interchange format develops further, with possibly more details, this function can
          * become dynamic, allowing for different parameters for the different architectures.

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -6,7 +6,7 @@
  * help the developer build, and traverse tree (this is also sometimes referred to
  * as the Document Object Model or DOM).
  *
- * For convenience, it often makes sense to use some wraper functions (provided in
+ * For convenience, it often makes sense to use some wrapper functions (provided in
  * the pugiutil namespace of libvtrutil) which simplify loading an XML file and
  * error handling.
  *
@@ -429,7 +429,7 @@ void xml_read_arch(std::string_view arch_file,
         char* prop = get_attribute(architecture, "version", loc_data, ReqOpt::OPTIONAL).as_string(NULL);
         if (prop != NULL) {
             if (atof(prop) > atof(VPR_VERSION)) {
-                VTR_LOG_WARN( "This architecture version is for VPR %f while your current VPR version is " VPR_VERSION ", compatability issues may arise\n",
+                VTR_LOG_WARN( "This architecture version is for VPR %f while your current VPR version is " VPR_VERSION ", compatibility issues may arise\n",
                         atof(prop));
             }
         }
@@ -444,7 +444,7 @@ void xml_read_arch(std::string_view arch_file,
         next = get_single_child(architecture, "layout", loc_data);
         process_layout(next, arch, loc_data, num_of_avail_layers);
 
-        // Precess vib_layout
+        // Process vib_layout
         next = get_single_child(architecture, "vib_layout", loc_data, ReqOpt::OPTIONAL);
         if (next) {
             process_vib_layout(next, arch, loc_data);
@@ -2029,7 +2029,7 @@ static void process_fc(pugi::xml_node node,
     }
 
     /* Go through all the port/segment combinations and create the (potentially
-     * overriden) pin/seg Fc specifications */
+     * overridden) pin/seg Fc specifications */
     for (size_t iseg = 0; iseg < segments.size(); ++iseg) {
         for (int icapacity = 0; icapacity < sub_tile->capacity.total(); ++icapacity) {
             //If capacity > 0, we need t offset the block index by the number of pins per instance
@@ -3610,7 +3610,7 @@ static void process_pin_locations(pugi::xml_node Locations,
                     if (!port_pins_with_specified_locations[iinst][port.name].contains(ipin)) {
                         //Missing
                         archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
-                                       vtr::string_fmt("Pin '%s[%d].%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")",
+                                       vtr::string_fmt("Pin '%s[%d].%s[%d]' has no pin location specified (a location is required for pattern=\"custom\")",
                                                        sub_tile->name.c_str(), iinst, port.name, ipin)
                                            .c_str());
                     }
@@ -3820,7 +3820,7 @@ static std::vector<t_segment_inf> process_segments(pugi::xml_node parent,
         if (tmp) {
             segs[i].name = tmp;
         } else {
-            /* if swich block is "custom", then you have to provide a name for segment */
+            /* if switch block is "custom", then you have to provide a name for segment */
             if (switchblocklist_required) {
                 archfpga_throw(loc_data.filename_c_str(), loc_data.line(node),
                                vtr::string_fmt("No name specified for the segment #%d.\n", i).c_str());