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2 parents 86698eb + 262ca0d commit 5b17dd1

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-1274
lines changed

30 files changed

+1237
-1274
lines changed

‎libs/EXTERNAL/libcatch2‎

Submodule libcatch2 updated 22 files

‎libs/libarchfpga/src/arch_check.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -163,11 +163,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
163163
if (annotation.type == E_ANNOT_PIN_TO_PIN_DELAY) {
164164
//Check that any combinational delays specified match the 'combinational_sinks_ports' in the model
165165

166-
if (annotation.clock) {
166+
if (!annotation.clock.empty()) {
167167
//Sequential annotation, check that the clock on the specified port matches the model
168168

169-
//Annotations always put the pin in the input_pins field
170-
VTR_ASSERT(annotation.input_pins);
169+
// Annotations always put the pin in the input_pins field
170+
VTR_ASSERT(!annotation.input_pins.empty());
171171
for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
172172
InstPort annot_port(input_pin);
173173
for (const std::string& clock : vtr::StringToken(annotation.clock).split(" \t\n")) {
@@ -207,15 +207,15 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
207207
}
208208
}
209209

210-
} else if (annotation.input_pins && annotation.output_pins) {
211-
//Combinational annotation
212-
VTR_ASSERT_MSG(!annotation.clock, "Combinational annotations should have no clock");
210+
} else if (!annotation.input_pins.empty() && !annotation.output_pins.empty()) {
211+
// Combinational annotation
212+
VTR_ASSERT_MSG(annotation.clock.empty(), "Combinational annotations should have no clock");
213213
for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
214214
InstPort annot_in(input_pin);
215215
for (const std::string& output_pin : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
216216
InstPort annot_out(output_pin);
217217

218-
//Find the input model port
218+
// Find the input model port
219219
const t_model_ports* model_port = nullptr;
220220
for (const t_model_ports* port = model.inputs; port != nullptr; port = port->next) {
221221
if (port->name == annot_in.port_name()) {
@@ -230,7 +230,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
230230
annot_in.port_name().c_str(), annot_in.instance_name().c_str());
231231
}
232232

233-
//Check that the output port is listed in the model's combinational sinks
233+
// Check that the output port is listed in the model's combinational sinks
234234
auto b = model_port->combinational_sink_ports.begin();
235235
auto e = model_port->combinational_sink_ports.end();
236236
auto iter = std::find(b, e, annot_out.port_name());

‎libs/libarchfpga/src/arch_util.cpp‎

Lines changed: 87 additions & 182 deletions
Large diffs are not rendered by default.

‎libs/libarchfpga/src/arch_util.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ t_logical_block_type get_empty_logical_type(const char* name = EMPTY_BLOCK_NAME)
6969
std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical_tile_type_ptr type);
7070

7171
void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
72-
char* new_name,
72+
std::string_view new_name,
7373
t_pb_type* copy);
7474

7575
void ProcessLutClass(t_pb_type* lut_pb_type);

‎libs/libarchfpga/src/echo_arch.cpp‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -397,12 +397,12 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
397397
for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) {
398398
fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs.c_str(),
399399
pb_type->modes[i].interconnect[j].type,
400-
pb_type->modes[i].interconnect[j].input_string,
401-
pb_type->modes[i].interconnect[j].output_string);
400+
pb_type->modes[i].interconnect[j].input_string.c_str(),
401+
pb_type->modes[i].interconnect[j].output_string.c_str());
402402
for (const t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) {
403403
fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs.c_str(),
404-
annotation.input_pins,
405-
annotation.output_pins,
404+
annotation.input_pins.c_str(),
405+
annotation.output_pins.c_str(),
406406
annotation.format,
407407
annotation.annotation_entries[0].second.c_str());
408408
}
@@ -428,9 +428,9 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
428428
&& pb_type_model_name != LogicalModels::MODEL_OUTPUT) {
429429
for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) {
430430
fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs.c_str(),
431-
annotation.clock,
432-
annotation.input_pins,
433-
annotation.output_pins,
431+
annotation.clock.c_str(),
432+
annotation.input_pins.c_str(),
433+
annotation.output_pins.c_str(),
434434
annotation.format,
435435
annotation.annotation_entries[0].second.c_str());
436436
}

‎libs/libarchfpga/src/physical_types.h‎

Lines changed: 8 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1076,18 +1076,13 @@ struct t_pin_to_pin_annotation {
10761076
e_pin_to_pin_annotation_type type;
10771077
e_pin_to_pin_annotation_format format;
10781078

1079-
char* input_pins;
1080-
char* output_pins;
1081-
char* clock;
1079+
std::string input_pins;
1080+
std::string output_pins;
1081+
std::string clock;
10821082

10831083
int line_num; /* used to report what line number this annotation is found in architecture file */
10841084

10851085
t_pin_to_pin_annotation() noexcept {
1086-
annotation_entries = std::vector<std::pair<int, std::string>>();
1087-
input_pins = nullptr;
1088-
output_pins = nullptr;
1089-
clock = nullptr;
1090-
10911086
line_num = 0;
10921087
type = (e_pin_to_pin_annotation_type)0;
10931088
format = (e_pin_to_pin_annotation_format)0;
@@ -1113,8 +1108,8 @@ struct t_interconnect {
11131108
e_interconnect type;
11141109
char* name;
11151110

1116-
char* input_string;
1117-
char* output_string;
1111+
std::string input_string;
1112+
std::string output_string;
11181113

11191114
std::vector<t_pin_to_pin_annotation> annotations;
11201115
bool infer_annotations;
@@ -1132,8 +1127,6 @@ struct t_interconnect {
11321127
t_interconnect() {
11331128
type = (e_interconnect)0;
11341129
name = nullptr;
1135-
input_string = nullptr;
1136-
output_string = nullptr;
11371130
infer_annotations = false;
11381131
line_num = 0;
11391132
parent_mode_index = 0;
@@ -1971,7 +1964,7 @@ struct t_arch {
19711964
std::vector<vtr::interned_string> interned_strings;
19721965

19731966
/// Secure hash digest of the architecture file to uniquely identify this architecture
1974-
char* architecture_id;
1967+
std::string architecture_id;
19751968

19761969
// Options for tileable routing architectures
19771970
// These are used for an alternative, tilable, rr-graph generator that can produce
@@ -2006,12 +1999,12 @@ struct t_arch {
20061999
int sub_fs;
20072000

20082001
/// Connecting type for pass tracks in each switch block
2009-
enum e_switch_block_type sb_sub_type;
2002+
e_switch_block_type sb_sub_type;
20102003

20112004
// End of tileable architecture options
20122005

20132006
t_chan_width_dist Chans;
2014-
enum e_switch_block_type sb_type;
2007+
e_switch_block_type sb_type;
20152008
std::vector<t_switchblock_inf> switchblocks;
20162009
float R_minW_nmos;
20172010
float R_minW_pmos;

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp‎

Lines changed: 34 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -242,28 +242,28 @@ static t_port get_generic_port(t_arch* arch,
242242
}
243243

244244
/** @brief Returns true if a given port name exists in the given complex block */
245-
static bool block_port_exists(t_pb_type* pb_type, std::string port_name) {
245+
static bool block_port_exists(t_pb_type* pb_type, std::string_view port_name) {
246246
for (int iport = 0; iport < pb_type->num_ports; iport++) {
247247
const t_port port = pb_type->ports[iport];
248248

249-
if (std::string(port.name) == port_name)
249+
if (port.name == port_name)
250250
return true;
251251
}
252252

253253
return false;
254254
}
255255

256-
/** @brief Returns a pack pattern given it's name, input and output strings */
257-
static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) {
256+
/** @brief Returns a pack pattern given its name, input and output strings */
257+
static t_pin_to_pin_annotation get_pack_pattern(std::string_view pp_name, std::string_view input, std::string_view output) {
258258
t_pin_to_pin_annotation pp;
259259

260260
pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
261261
pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT;
262-
pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name});
263-
pp.input_pins = vtr::strdup(input.c_str());
264-
pp.output_pins = vtr::strdup(output.c_str());
262+
pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name.data()});
263+
pp.input_pins = input;
264+
pp.output_pins = output;
265265

266-
pp.clock = nullptr;
266+
pp.clock.clear();
267267

268268
return pp;
269269
}
@@ -1216,8 +1216,8 @@ struct ArchReader {
12161216
ostr = std::string(pb_type->name) + ".in[" + std::to_string(j) + "]";
12171217
name = istr + "_to_" + ostr;
12181218

1219-
ic->input_string = vtr::strdup(istr.c_str());
1220-
ic->output_string = vtr::strdup(ostr.c_str());
1219+
ic->input_string = istr;
1220+
ic->output_string = ostr;
12211221
ic->name = vtr::strdup(name.c_str());
12221222
}
12231223

@@ -1231,8 +1231,8 @@ struct ArchReader {
12311231
ostr = std::string(parent->name) + "." + lut_bel.output_pin;
12321232
name = istr + "_to_" + ostr;
12331233

1234-
ic->input_string = vtr::strdup(istr.c_str());
1235-
ic->output_string = vtr::strdup(ostr.c_str());
1234+
ic->input_string = istr;
1235+
ic->output_string = ostr;
12361236
ic->name = vtr::strdup(name.c_str());
12371237
}
12381238
}
@@ -1267,14 +1267,12 @@ struct ArchReader {
12671267
mode->interconnect = new t_interconnect[mode->num_interconnect];
12681268
t_interconnect* ic = &mode->interconnect[0];
12691269

1270-
std::string istr, ostr, name;
1270+
std::string istr = std::string(pb_type->name) + ".in";
1271+
std::string ostr = std::string(pb_type->name) + ".out";
1272+
std::string name = "passthrough";
12711273

1272-
istr = std::string(pb_type->name) + ".in";
1273-
ostr = std::string(pb_type->name) + ".out";
1274-
name = "passthrough";
1275-
1276-
ic->input_string = vtr::strdup(istr.c_str());
1277-
ic->output_string = vtr::strdup(ostr.c_str());
1274+
ic->input_string = istr;
1275+
ic->output_string = ostr;
12781276
ic->name = vtr::strdup(name.c_str());
12791277

12801278
ic->type = COMPLETE_INTERC;
@@ -1329,8 +1327,8 @@ struct ArchReader {
13291327
ostr = std::string(lut->name) + ".in";
13301328
name = istr + "_to_" + ostr;
13311329

1332-
ic->input_string = vtr::strdup(istr.c_str());
1333-
ic->output_string = vtr::strdup(ostr.c_str());
1330+
ic->input_string = istr;
1331+
ic->output_string = ostr;
13341332
ic->name = vtr::strdup(name.c_str());
13351333

13361334
// Output
@@ -1343,8 +1341,8 @@ struct ArchReader {
13431341
ostr = std::string(pb_type->name) + ".out";
13441342
name = istr + "_to_" + ostr;
13451343

1346-
ic->input_string = vtr::strdup(istr.c_str());
1347-
ic->output_string = vtr::strdup(ostr.c_str());
1344+
ic->input_string = istr;
1345+
ic->output_string = ostr;
13481346
ic->name = vtr::strdup(name.c_str());
13491347
}
13501348

@@ -1458,15 +1456,15 @@ struct ArchReader {
14581456
o_ic->type = DIRECT_INTERC;
14591457
o_ic->parent_mode_index = 0;
14601458
o_ic->parent_mode = omode;
1461-
o_ic->input_string = vtr::strdup(opad_istr.c_str());
1462-
o_ic->output_string = vtr::strdup(opad_ostr.c_str());
1459+
o_ic->input_string = opad_istr;
1460+
o_ic->output_string = opad_ostr;
14631461

14641462
i_ic->name = vtr::strdup(i_ic_name.c_str());
14651463
i_ic->type = DIRECT_INTERC;
14661464
i_ic->parent_mode_index = 0;
14671465
i_ic->parent_mode = imode;
1468-
i_ic->input_string = vtr::strdup(ipad_istr.c_str());
1469-
i_ic->output_string = vtr::strdup(ipad_ostr.c_str());
1466+
i_ic->input_string = ipad_istr.c_str();
1467+
i_ic->output_string = ipad_ostr.c_str();
14701468

14711469
omode->interconnect[0] = *o_ic;
14721470
imode->interconnect[0] = *i_ic;
@@ -1611,8 +1609,8 @@ struct ArchReader {
16111609
ic->type = DIRECT_INTERC;
16121610
ic->parent_mode_index = idx;
16131611
ic->parent_mode = mode;
1614-
ic->input_string = vtr::strdup(istr.c_str());
1615-
ic->output_string = vtr::strdup(ostr.c_str());
1612+
ic->input_string = istr;
1613+
ic->output_string = ostr;
16161614
}
16171615

16181616
create_ports(leaf, pins, name);
@@ -1667,8 +1665,8 @@ struct ArchReader {
16671665
ic->type = ic_type;
16681666
ic->parent_mode_index = idx;
16691667
ic->parent_mode = mode;
1670-
ic->input_string = vtr::strdup(istr.c_str());
1671-
ic->output_string = vtr::strdup(ostr.c_str());
1668+
ic->input_string = istr;
1669+
ic->output_string = ostr;
16721670
}
16731671

16741672
/** @brief Processes all the ports of a given complex block.
@@ -1787,8 +1785,8 @@ struct ArchReader {
17871785

17881786
VTR_ASSERT(names.insert(ic_name).second);
17891787
ic->name = vtr::strdup(ic_name.c_str());
1790-
ic->input_string = vtr::strdup(input.c_str());
1791-
ic->output_string = vtr::strdup(outputs_str.c_str());
1788+
ic->input_string = input;
1789+
ic->output_string = outputs_str;
17921790
}
17931791

17941792
// Checks and, in case, adds all the necessary pack patterns to the marked interconnects
@@ -2144,8 +2142,8 @@ struct ArchReader {
21442142
ic->type = DIRECT_INTERC;
21452143
ic->parent_mode_index = 0;
21462144
ic->parent_mode = mode;
2147-
ic->input_string = vtr::strdup(istr.c_str());
2148-
ic->output_string = vtr::strdup(ostr.c_str());
2145+
ic->input_string = istr;
2146+
ic->output_string = ostr;
21492147

21502148
count++;
21512149
}
@@ -2529,7 +2527,7 @@ void FPGAInterchangeReadArch(const char* FPGAInterchangeDeviceFile,
25292527

25302528
auto device_reader = message_reader.getRoot<DeviceResources::Device>();
25312529

2532-
arch->architecture_id = vtr::strdup(vtr::secure_digest_file(FPGAInterchangeDeviceFile).c_str());
2530+
arch->architecture_id = vtr::secure_digest_file(FPGAInterchangeDeviceFile);
25332531

25342532
ArchReader reader(arch, device_reader, FPGAInterchangeDeviceFile, PhysicalTileTypes, LogicalBlockTypes);
25352533
reader.read_arch();

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