Skip to content

Commit 4ce0c34

Browse files
soheilshahrouzsoheilshahrouz
committed
local loop variables in arch_util.cpp
1 parent d744f8c commit 4ce0c34

File tree

2 files changed

+30
-38
lines changed

2 files changed

+30
-38
lines changed

‎libs/libarchfpga/src/arch_util.cpp‎

Lines changed: 29 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
#include <sstream>
33
#include <string>
44
#include <vector>
5+
#include <ranges>
56

67
#include "logic_types.h"
78
#include "physical_types.h"
@@ -213,29 +214,27 @@ static void free_all_pb_graph_nodes(std::vector<t_logical_block_type>& type_desc
213214
}
214215

215216
static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
216-
int i, j, k;
217-
const t_pb_type* pb_type;
218-
219-
pb_type = pb_graph_node->pb_type;
217+
const t_pb_type* pb_type = pb_graph_node->pb_type;
220218

221219
/*free all lists of connectable input pin pointer of pb_graph_node and it's children*/
222220
/*free_list_of_connectable_input_pin_ptrs (pb_graph_node);*/
223221

224222
/* Free ports for pb graph node */
225-
for (i = 0; i < pb_graph_node->num_input_ports; i++) {
226-
for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) {
223+
for (int i = 0; i < pb_graph_node->num_input_ports; i++) {
224+
for (int j = 0; j < pb_graph_node->num_input_pins[i]; j++) {
227225
if (pb_graph_node->input_pins[i][j].parent_pin_class)
228226
delete[] pb_graph_node->input_pins[i][j].parent_pin_class;
229227
}
230228
delete[] pb_graph_node->input_pins[i];
231229
}
232-
for (i = 0; i < pb_graph_node->num_output_ports; i++) {
233-
for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) {
230+
231+
for (int i = 0; i < pb_graph_node->num_output_ports; i++) {
232+
for (int j = 0; j < pb_graph_node->num_output_pins[i]; j++) {
234233
if (pb_graph_node->output_pins[i][j].parent_pin_class)
235234
delete[] pb_graph_node->output_pins[i][j].parent_pin_class;
236235

237236
if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs) {
238-
for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
237+
for (int k = 0; k < pb_graph_node->pb_type->depth; k++) {
239238
delete[] pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k];
240239
}
241240
delete[] pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs;
@@ -246,8 +245,9 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
246245
}
247246
delete[] pb_graph_node->output_pins[i];
248247
}
249-
for (i = 0; i < pb_graph_node->num_clock_ports; i++) {
250-
for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) {
248+
249+
for (int i = 0; i < pb_graph_node->num_clock_ports; i++) {
250+
for (int j = 0; j < pb_graph_node->num_clock_pins[i]; j++) {
251251
if (pb_graph_node->clock_pins[i][j].parent_pin_class)
252252
delete[] pb_graph_node->clock_pins[i][j].parent_pin_class;
253253
}
@@ -266,12 +266,12 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
266266
delete[] pb_graph_node->output_pin_class_size;
267267

268268
if (pb_graph_node->interconnect_pins) {
269-
for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) {
269+
for (int i = 0; i < pb_graph_node->pb_type->num_modes; i++) {
270270
if (pb_graph_node->interconnect_pins[i] == nullptr) continue;
271271

272272
t_mode* mode = &pb_graph_node->pb_type->modes[i];
273273

274-
for (j = 0; j < mode->num_interconnect; ++j) {
274+
for (int j = 0; j < mode->num_interconnect; ++j) {
275275
//The interconnect_pins data structures are only initialized for power analysis and
276276
//are bizarrely baroque...
277277
t_interconnect* interconn = pb_graph_node->interconnect_pins[i][j].interconnect;
@@ -293,9 +293,9 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
293293
delete[] pb_graph_node->interconnect_pins;
294294
delete pb_graph_node->pb_node_power;
295295

296-
for (i = 0; i < pb_type->num_modes; i++) {
297-
for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) {
298-
for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) {
296+
for (int i = 0; i < pb_type->num_modes; i++) {
297+
for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) {
298+
for (int k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) {
299299
free_pb_graph(&pb_graph_node->child_pb_graph_nodes[i][j][k]);
300300
}
301301
vtr::free(pb_graph_node->child_pb_graph_nodes[i][j]);
@@ -339,17 +339,14 @@ static void free_pb_type(t_pb_type* pb_type) {
339339
}
340340

341341
t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, int* low_index) {
342-
t_port* port;
343342
int i;
344343
unsigned int high;
345344
unsigned int low;
346-
unsigned int bracket_pos;
347-
unsigned int colon_pos;
348345

349-
bracket_pos = strcspn(name, "[");
346+
unsigned int bracket_pos = strcspn(name, "[");
350347

351348
/* Find port by name */
352-
port = nullptr;
349+
t_port* port = nullptr;
353350
for (i = 0; i < pb_type->num_ports; i++) {
354351
char* compare_to = pb_type->ports[i].name;
355352

@@ -367,7 +364,7 @@ t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, in
367364
if (strlen(name) > bracket_pos) {
368365
high = atoi(&name[bracket_pos + 1]);
369366

370-
colon_pos = strcspn(name, ":");
367+
unsigned int colon_pos = strcspn(name, ":");
371368

372369
if (colon_pos < strlen(name)) {
373370
low = atoi(&name[colon_pos + 1]);
@@ -535,8 +532,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
535532
lut_pb_type->modes[0].num_interconnect = 1;
536533
lut_pb_type->modes[0].interconnect = new t_interconnect[1];
537534
lut_pb_type->modes[0].interconnect[0].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 10, sizeof(char));
538-
sprintf(lut_pb_type->modes[0].interconnect[0].name, "complete:%s",
539-
lut_pb_type->name);
535+
sprintf(lut_pb_type->modes[0].interconnect[0].name, "complete:%s", lut_pb_type->name);
540536
lut_pb_type->modes[0].interconnect[0].type = COMPLETE_INTERC;
541537
lut_pb_type->modes[0].interconnect[0].input_string = vtr::string_fmt("%s.%s", lut_pb_type->name, in_port->name);
542538
lut_pb_type->modes[0].interconnect[0].output_string = vtr::string_fmt("%s.%s", lut_pb_type->name, out_port->name);
@@ -580,8 +576,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
580576
lut_pb_type->modes[1].num_interconnect = 2;
581577
lut_pb_type->modes[1].interconnect = new t_interconnect[lut_pb_type->modes[1].num_interconnect];
582578
lut_pb_type->modes[1].interconnect[0].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 10, sizeof(char));
583-
sprintf(lut_pb_type->modes[1].interconnect[0].name, "direct:%s",
584-
lut_pb_type->name);
579+
sprintf(lut_pb_type->modes[1].interconnect[0].name, "direct:%s", lut_pb_type->name);
585580
lut_pb_type->modes[1].interconnect[0].type = DIRECT_INTERC;
586581
lut_pb_type->modes[1].interconnect[0].input_string = vtr::string_fmt(lut_pb_type->name, in_port->name);
587582
lut_pb_type->modes[1].interconnect[0].output_string = default_name + '.' + in_port->name;
@@ -592,8 +587,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
592587
lut_pb_type->modes[1].interconnect[0].interconnect_power = new t_interconnect_power();
593588

594589
lut_pb_type->modes[1].interconnect[1].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 11, sizeof(char));
595-
sprintf(lut_pb_type->modes[1].interconnect[1].name, "direct:%s",
596-
lut_pb_type->name);
590+
sprintf(lut_pb_type->modes[1].interconnect[1].name, "direct:%s", lut_pb_type->name);
597591

598592
lut_pb_type->modes[1].interconnect[1].type = DIRECT_INTERC;
599593
lut_pb_type->modes[1].interconnect[1].input_string = vtr::string_fmt("%s.%s", default_name.c_str(), out_port->name);
@@ -867,15 +861,14 @@ void SyncModelsPbTypes_rec(t_arch* arch,
867861
*/
868862
void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation,
869863
t_pb_type* parent_pb_type) {
870-
int i_port;
871864
bool clock_valid = false; //Determine if annotation's clock is same as primitive's clock
872865

873866
if (!parent_pb_type || !annotation) {
874867
archfpga_throw(__FILE__, __LINE__,
875868
"Annotation_clock check encounters invalid annotation or primitive.\n");
876869
}
877870

878-
for (i_port = 0; i_port < parent_pb_type->num_ports; i_port++) {
871+
for (int i_port = 0; i_port < parent_pb_type->num_ports; i_port++) {
879872
if (parent_pb_type->ports[i_port].is_clock) {
880873
if (parent_pb_type->ports[i_port].name == annotation->clock) {
881874
clock_valid = true;
@@ -979,7 +972,7 @@ bool has_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* po
979972
for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) {
980973
InstPort annot_in(annotation.input_pins);
981974
if (annot_in.port_name() == port->name) {
982-
for (const auto& [key, _] : annotation.annotation_entries) {
975+
for (const int key : annotation.annotation_entries | std::views::keys) {
983976
if (key == annot_type) {
984977
return true;
985978
}
@@ -997,9 +990,8 @@ bool has_combinational_annotation(const t_pb_type* pb_type, std::string_view in_
997990
for (const std::string& annot_out_str : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
998991
InstPort out_pins(annot_out_str);
999992
if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) {
1000-
for (const auto& [key, _] : annotation.annotation_entries) {
1001-
if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX
1002-
|| key == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
993+
for (const int key : annotation.annotation_entries | std::views::keys) {
994+
if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX || key == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
1003995
return true;
1004996
}
1005997
}
@@ -1031,7 +1023,7 @@ void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTile
10311023
return lhs_diff_num_pins < rhs_diff_num_pins;
10321024
};
10331025

1034-
std::sort(equivalent_sites.begin(), equivalent_sites.end(), criteria);
1026+
std::ranges::stable_sort(equivalent_sites, criteria);
10351027

10361028
for (t_logical_block_type& logical_block : LogicalBlockTypes) {
10371029
for (t_logical_block_type_ptr site : equivalent_sites) {
@@ -1068,15 +1060,15 @@ void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTile
10681060
return lhs_diff_num_pins < rhs_diff_num_pins;
10691061
};
10701062

1071-
std::sort(equivalent_tiles.begin(), equivalent_tiles.end(), criteria);
1063+
std::ranges::stable_sort(equivalent_tiles, criteria);
10721064

10731065
for (int pin = 0; pin < logical_block.pb_type->num_pins; pin++) {
10741066
for (auto& tile : equivalent_tiles) {
10751067
auto direct_maps = tile->tile_block_pin_directs_map.at(logical_block.index);
10761068

10771069
for (auto& sub_tile : tile->sub_tiles) {
10781070
auto equiv_sites = sub_tile.equivalent_sites;
1079-
if (std::find(equiv_sites.begin(), equiv_sites.end(), &logical_block) == equiv_sites.end()) {
1071+
if (std::ranges::find(equiv_sites, &logical_block) == equiv_sites.end()) {
10801072
continue;
10811073
}
10821074

‎vpr/src/base/load_flat_place.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,7 @@ FlatPlacementInfo read_flat_placement(const std::string& read_flat_place_file_pa
190190
bool load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) {
191191
VTR_LOG("load_flat_placement(); when implemented, this function:");
192192
VTR_LOG("\n\tLoads flat placement file: %s, ", vpr_setup.FileNameOpts.FlatPlaceFile.c_str());
193-
VTR_LOG("\n\tArch id: %s, ", arch.architecture_id);
193+
VTR_LOG("\n\tArch id: %s, ", arch.architecture_id.c_str());
194194
VTR_LOG("\n\tPrints clustered netlist file: %s, ", vpr_setup.FileNameOpts.NetFile.c_str());
195195
VTR_LOG("\n\tPrints fix clusters file: %s\n", vpr_setup.FileNameOpts.write_constraints_file.c_str());
196196

0 commit comments

Comments
 (0)