Merge commit master into temp_chanz_rr_type

Author: soheilshahrouz

.github/workflows/nightly_test_manual.yml

@@ -50,6 +50,7 @@ jobs:
         make get_ispd_benchmarks
         ./dev/upgrade_vtr_archs.sh
         make get_symbiflow_benchmarks
+        make get_zeroasic_rr_graphs
 
     # Build VTR using the default build options.
     - name: 'Build VTR'
@@ -114,3 +115,23 @@ jobs:
           vtr_flow/**/*.log
           vtr_flow/**/vpr.out
           vtr_flow/**/parse_results*.txt
+
+    - name: Generate golden results
+      if: success() || failure()
+      run: |
+        source .venv/bin/activate
+        ./run_reg_test.py vtr_reg_nightly_test1 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test2 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test3 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test4 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test5 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test6 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test7 -create_golden
+
+    - name: Upload golden results
+      if: success() || failure()
+      uses: actions/upload-artifact@v4
+      with:
+        name: nightly_tests_golden
+        path: |
+          vtr_flow/**/vtr_reg_nightly*/**/golden_results.txt

.gitmodules

@@ -10,3 +10,6 @@
 [submodule "libs/EXTERNAL/libezgl"]
 	path = libs/EXTERNAL/libezgl
 	url = https://github.com/verilog-to-routing/ezgl.git
+[submodule "libs/EXTERNAL/yosys"]
+	path = libs/EXTERNAL/yosys
+	url = https://github.com/YosysHQ/yosys.git

CMakeLists.txt

@@ -227,18 +227,17 @@ foreach(flag ${FLEX_BISON_WARN_SUPPRESS_FLAGS_TO_CHECK})
     endif()
 endforeach()
 
-#Suppress IPO link warnings
-set(IPO_LINK_WARN_SUPRESS_FLAGS " ")
-set(IPO_LINK_WARN_SUPRESS_FLAGS_TO_CHECK
-    "-Wno-null-dereference"
-    )
-foreach(flag ${IPO_LINK_WARN_SUPRESS_FLAGS_TO_CHECK})
-    CHECK_CXX_COMPILER_FLAG(${flag} CXX_COMPILER_SUPPORTS_${flag})
-    if(CXX_COMPILER_SUPPORTS_${flag})
-        #Flag supported, so enable it
-        set(IPO_LINK_WARN_SUPRESS_FLAGS "${IPO_LINK_WARN_SUPRESS_FLAGS} ${flag}")
-    endif()
-endforeach()
+# Suppress IPO link warnings.
+# When IPO is turned on, it sometimes leads to false positives for warnings
+# since it checks for warnings after some of the source files have been compiled.
+# We globally suppress these warnings here. Any CMake executable which is added
+# after this line will have these warnings suppressed at link time.
+if (CMAKE_INTERPROCEDURAL_OPTIMIZATION)
+    message(STATUS "IPO: Suppressing known VTR warnings.")
+    add_link_options(-Wno-alloc-size-larger-than  # libarchfpga allocates C-style arrays using integers.
+                     -Wno-stringop-overflow       # EXTERNAL/capnproto has some string overflow warnings.
+                     )
+endif()
 
 #
 # Sanitizer flags
@@ -361,6 +360,14 @@ add_custom_target(get_symbiflow_benchmarks
     WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
     COMMENT "Downloading (~100MB) and extracting SymbiFlow architectures (~2.7GB) into VTR source tree.")
 
+#
+# Zero ASIC RR Graph Files
+#
+add_custom_target(get_zeroasic_rr_graphs
+    COMMAND ./vtr_flow/scripts/get_zeroasic_rr_graphs.py --vtr_flow_dir ./vtr_flow
+    WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
+    COMMENT "Downloading (~2MB) and extracting Zero ASIC RR graphs (~0.1GB) into VTR source tree.")
+
 #
 # Unit Testing
 #
@@ -406,24 +413,6 @@ if(${WITH_ABC})
     add_subdirectory(abc)
 endif()
 
-if(${WITH_PARMYS}) # define cmake params to compile Yosys
-    add_definitions("-D_YOSYS_")
-
-    set(MAKE_PROGRAM "$(MAKE)")
-    if(${CMAKE_GENERATOR} STREQUAL "Ninja")
-        set(MAKE_PROGRAM "make")
-    endif()
-
-    # Commented out since a make file should not call another make command with
-    # threads. It should pass this information from the parent automatically.
-    # if(NOT DEFINED "${CMAKE_BUILD_PARALLEL_LEVEL}")
-    #     set(CUSTOM_BUILD_PARALLEL_LEVEL 16)
-    # else()
-    #     set(CUSTOM_BUILD_PARALLEL_LEVEL "${CMAKE_BUILD_PARALLEL_LEVEL}")
-    # endif()
-    add_subdirectory(yosys)
-endif()
-
 add_subdirectory(libs) #libs/CMakeLists.txt handles adding warnings flags to non-external libraries
 
 if(${WITH_PARMYS})

blifexplorer/CMakeLists.txt

@@ -56,13 +56,6 @@ else()
                             ${CMAKE_DL_LIBS}
     )
 
-    #Supress IPO link warnings if IPO is enabled
-    get_target_property(TEST_BLIFEXPLORER_USES_IPO blifexplorer INTERPROCEDURAL_OPTIMIZATION)
-    if (TEST_BLIFEXPLORER_USES_IPO)
-        set_property(TARGET blifexplorer APPEND PROPERTY LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS})
-    endif()
-
-
     install(TARGETS blifexplorer DESTINATION bin)
 
 endif()

dev/subtree_config.xml

@@ -49,11 +49,6 @@
         internal_path="vtr_flow/benchmarks/system_verilog/fx68k"
         external_url="https://github.com/ijor/fx68k.git"
         default_external_ref="master"/>
-    <subtree
-        name="yosys"
-        internal_path="yosys"
-        external_url="https://github.com/YosysHQ/yosys.git"
-        default_external_ref="yosys-0.32"/>
     <subtree
         name="parmys"
         internal_path="parmys"

dev/vtr_test_suite_verifier/test_suites_info.json

@@ -19,14 +19,12 @@
         "name": "vtr_reg_strong",
         "ignored_tasks": [
             "strong_router_heap",
-            "strong_verify_rr_graph_3d",
-            "strong_xilinx_support"
+            "strong_verify_rr_graph_3d"
         ]
     },
     {
         "name": "vtr_reg_strong_odin",
         "ignored_tasks": [
-            "strong_xilinx_support",
             "strong_router_heap",
             "strong_cluster_seed_type"
         ]
@@ -44,8 +42,7 @@
         "name": "vtr_reg_nightly_test2",
         "ignored_tasks": [
             "complex_switch",
-            "vpr_verify_custom_sb_diff_chan_width",
-            "vtr_xilinx_qor"
+            "vpr_verify_custom_sb_diff_chan_width"
         ]
     },
     {

doc/.gitignore

@@ -1,2 +1,3 @@
 #Sphinx
 _build
+.venv

doc/README

@@ -14,19 +14,22 @@ Currently VTR's documenation is automatically built by https://readthedocs.org/p
 How to build documentation
 --------------------------
 
-To build the documentation locally you need sphinx installed:
+To build the documentation locally you need to to install Doxygen (Optional) and the python dependencies. You can use your distribution's package manager to install Doxygen. Ubuntu and Debian users can use the following command:
 
-    For ubuntu/debian based systems:
+    $ sudo apt install doxygen
 
-        $ apt-get install python-sphinx
+While Fedora and RHEL users can use the following command:
 
-    To properly build citations and the bibliography, we use the sphinxcontrib-bibtex extension:
+    $ sudo dnf install doxygen
 
-        $ pip install sphinxcontrib-bibtex
+You can install python dependencies by fist optionally making a virtual environment:
 
-    To install all the python requirements:
+    $ python -m venv .venv
+    $ source .venv/bin/activate
 
-        $ pip install -r requirements.txt
+And then using the requirements file to install the dependencies:
+
+    $ pip install -r requirements.txt
 
 To build the documentation just run:
 

doc/requirements.txt

@@ -2,11 +2,12 @@
 # used by Read The Docs to install python required
 # modules with pip.
 
-sphinx<7
+# Pinned sphinx's version to avoid breakage in future
+sphinx == 8.2.3
 sphinx_rtd_theme
 
 # Support custom domains
-sphinxcontrib-domaintools
+git+https://github.com/AmirhosseinPoolad/sphinxcontrib-domaintools
 
 # Support Markdown
 sphinx-markdown-tables

doc/src/arch/reference.rst

@@ -1167,6 +1167,24 @@ The following tags are common to all ``<tile>`` tags:
 
                 **Default:** ``0``
 
+            If the subtile capacity is greater than 1, you can specify the capacity range when defining the pin locations. For example:
+
+            .. code-block:: xml
+
+                <sub_tile name="io_bottom" capacity="6">
+                    <equivalent_sites>
+                        <site pb_type="io"/>
+                    </equivalent_sites>
+                    <input name="outpad" num_pins="1"/>
+                    <output name="inpad" num_pins="1"/>
+                    <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+                    <pinlocations pattern="custom">
+                        <loc side="top">io_bottom[0:1].outpad io_bottom[0:3].inpad io_bottom[2:5].outpad io_bottom[4:5].inpad</loc>
+                    </pinlocations>
+                </sub_tile>
+            
+            If no capacity range is specified, it is assumed that the location applies to all capacity instances.
+
         Physical equivalence for a pin is specified by listing a pin more than once for different locations.
         For example, a LUT whose output can exit from the top and bottom of a block will have its output pin specified twice: once for the top and once for the bottom.