Merge pull request #3181 from verilog-to-routing/synlig_to_yosys_slang

Switching from Synlig to Yosys-Slang

Author: AlexandreSinger

.github/workflows/test.yml

@@ -311,6 +311,10 @@ jobs:
             name: 'Strong',
             suite: 'vtr_reg_strong'
           },
+          {
+            name: 'SystemVerilog',
+            suite: 'vtr_reg_system_verilog'
+          },
           {
             name: 'Valgrind Memory',
             suite: 'vtr_reg_valgrind_small'

.gitmodules

@@ -13,3 +13,6 @@
 [submodule "libs/EXTERNAL/yosys"]
 	path = libs/EXTERNAL/yosys
 	url = https://github.com/YosysHQ/yosys.git
+[submodule "libs/EXTERNAL/yosys-slang"]
+	path = libs/EXTERNAL/yosys-slang
+	url = https://github.com/povik/yosys-slang.git

CMakeLists.txt

@@ -56,7 +56,7 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
 
 # Allow the user to enable building Yosys
 option(WITH_PARMYS "Enable Yosys as elaborator and parmys-plugin as partial mapper" ON)
-option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF)
+option(SLANG_SYSTEMVERILOG "Enable building and installing Yosys-Slang plugin for parsing SystemVerilog" ON)
 
 set(VTR_VERSION_MAJOR 9)
 set(VTR_VERSION_MINOR 0)
@@ -437,11 +437,12 @@ if(${WITH_ODIN})
     endif()
 endif()
 
-# handle cmake params to compile Yosys SystemVerilog/UHDM plugins
-if(${SYNLIG_SYSTEMVERILOG})
-    # avoid compiling plugins in case the Parmys frontend is not active
+# handle cmake params to compile yosys-slang plugin for Yosys
+if(${SLANG_SYSTEMVERILOG})
+    # avoid compiling yosys-slang plugin in case the Parmys frontend is not active
     if(NOT ${WITH_PARMYS})
-        message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Parmys frontend. Please set WITH_PARMYS.")
+        message(WARNING "Parmys is not enabled, disabling Yosys-Slang as well.")
+        set(SLANG_SYSTEMVERILOG OFF)
     endif()
 endif()
 

dev/vtr_test_suite_verifier/test_suites_info.json

@@ -11,6 +11,10 @@
         "name": "parmys_reg_basic",
         "ignored_tasks": []
     },
+    {
+        "name": "vtr_reg_system_verilog",
+        "ignored_tasks": []
+    },
     {
         "name": "vtr_reg_valgrind_small",
         "ignored_tasks": []

doc/src/vtr/run_vtr_flow.rst

@@ -73,15 +73,12 @@ The parser for these runs is considered the Yosys conventional Verilog/SystemVer
 
 .. code-block:: bash
 
-    # Using the Synlig System_Verilog tool if installed, otherwise the Yosys conventional Verilog parser
-    ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -parser system-verilog
-
-    # Using the Surelog plugin if installed, otherwise failure on the unsupported file type
-    ./run_vtr_flow <path/to/UHDM/File> <path/to/arch/file> -parser surelog
+    # Using the Yosys-Slang plugin for Yosys, otherwise the Yosys conventional Verilog parser
+    ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -parser slang
 
-Running the default VTR flow using the Parmys standalone front-end.
-The Synlig HDL parser supports the (i.e., ``read_systemverilog``) and (i.e., ``read_uhdm``) commands. It utilizes Surelog for SystemVerilog 2017 processing and Yosys for synthesis.
-Enable Synlig tool with the ``-DSYNLIG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end.
+Will run the VTR flow (default configuration) with Yosys-Slang plugin for Yosys frontend using Parmys plugin as partial mapper.
+The Yosys-Slang SystemVerilog parser supports the (i.e., ``read_slang``) command. Yosys-Slang builds on top of the slang library to provide comprehensive SystemVerilog support.
+Enable the Yosys-Slang plugin with the ``-DSLANG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end.
 
 .. code-block:: bash
 
@@ -260,19 +257,24 @@ Detailed Command-line Options
 
 .. option:: -parser <PARSER>
 
-    Specify a parser for the Yosys synthesizer [default (Verilog-2005), surelog (UHDM), system-verilog].
+    Specify a parser for the Yosys synthesizer [default (Verilog-2005), slang (SystemVerilog)].
     The script uses the default conventional Verilog parser if this argument is not used.
 
     **Default:** default
 
 .. note::
 
-    Universal Hardware Data Model (UHDM) is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.
-    UHDM is used as a compiled interchange format in between SystemVerilog tools. Typical inputs to the UHDM flow are files with ``.v`` or ``.sv`` extensions.
-    The ``system-verilog`` parser, which represents the ``read_systemverilog`` command, reads SystemVerilog files directly in Yosys.
-    It executes Surelog with provided filenames and converts them (in memory) into UHDM file. Then, this UHDM file is converted into Yosys AST. `[Yosys-SystemVerilog] <https://github.com/antmicro/yosys-systemverilog#usage>`_
-    On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys <https://github.com/chipsalliance/UHDM-integration-tests#uhdm-yosys>`_, `Surelog] <https://github.com/chipsalliance/Surelog#surelog>`_
+    Yosys-Slang is a Yosys plugin that is built on top of the slang library to provide comprehensive SystemVerilog support.
+    It supports the ``read_slang`` command, used with the ``-C`` command-line option to read include-files from a text file containing include-file names.
+    It is used to read SystemVerilog files directly in Yosys.
+    For more information on Yosys-Slang, see `[Yosys-Slang] <https://github.com/povik/yosys-slang.git>`_
 
 .. note::
 
     Parmys is a Yosys plugin which provides intelligent partial mapping features (inference, binding, and hard/soft logic trade-offs) from Odin-II for Yosys. For more information on available paramters see the `Parmys <https://github.com/CAS-Atlantic/parmys-plugin.git>`_ plugin page.
+
+.. Universal Hardware Data Model (UHDM) is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.
+..     UHDM is used as a compiled interchange format in between SystemVerilog tools. Typical inputs to the UHDM flow are files with ``.v`` or ``.sv`` extensions.
+..     The ``system-verilog`` parser, which represents the ``read_systemverilog`` command, reads SystemVerilog files directly in Yosys.
+..     It executes Surelog with provided filenames and converts them (in memory) into UHDM file. Then, this UHDM file is converted into Yosys AST. `[Yosys-SystemVerilog] <https://github.com/antmicro/yosys-systemverilog#usage>`_
+..     On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys <https://github.com/chipsalliance/UHDM-integration-tests#uhdm-yosys>`_, `Surelog] <https://github.com/chipsalliance/Surelog#surelog>`_

libs/EXTERNAL/CMakeLists.txt

@@ -1,6 +1,8 @@
 include(ExternalProject)
 include(ProcessorCount)
 
+find_package(Git REQUIRED)
+
 #Manually synchronized external libraries
 add_subdirectory(libpugixml)
 
@@ -10,7 +12,6 @@ add_subdirectory(libsdcparse)
 add_subdirectory(libblifparse)
 add_subdirectory(libtatum)
 add_subdirectory(libcatch2)
-#add_subdirectory(synlig)
 #add_subdirectory(parmys)
 
 #Proc numbers
@@ -60,11 +61,11 @@ if (${WITH_PARMYS})
 
 	#Initialize yosys submodules
 	execute_process(
-	 COMMAND git submodule update --init
+	 COMMAND ${GIT_EXECUTABLE} submodule update --init
 	 WORKING_DIRECTORY ${YOSYS_SRC_DIR}
 	)
 	execute_process(
-	  COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive git\ submodule\ update\ --init
+	  COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive ${GIT_EXECUTABLE}\ submodule\ update\ --init
 	  WORKING_DIRECTORY ${YOSYS_SRC_DIR}
 	)
 
@@ -73,104 +74,61 @@ if (${WITH_PARMYS})
 		COMMAND ${MAKE_PROGRAM} -C ${YOSYS_SRC_DIR}
 		    ENABLE_ABC=0
 		    PREFIX=${CMAKE_BINARY_DIR}
-
+            > /dev/null 2>&1
 		 COMMAND ${MAKE_PROGRAM} 
 		    -C ${YOSYS_SRC_DIR}
 		    install
 		    ENABLE_ABC=0
 		    PREFIX=${CMAKE_BINARY_DIR}
-
+            > /dev/null 2>&1
 		WORKING_DIRECTORY ${YOSYS_SRC_DIR})
 
 	add_custom_target(yosys ALL DEPENDS ${YOSYS_BUILD_DIR})
 
-    if (${SYNLIG_SYSTEMVERILOG})
-
-        set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
-        set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build)
-        set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins)
-
-        ExternalProject_Add(surelog
-                # root directory for Surelog project
-                PREFIX "surelog"
-
-                GIT_REPOSITORY https://github.com/chipsalliance/Surelog.git
-                GIT_TAG v1.71
-                GIT_PROGRESS TRUE
-                GIT_SHALLOW TRUE
-
-                # setting source, build and install directories
-                SOURCE_DIR "${SURELOG_SOURCE_DIR}"
-                BUILD_IN_SOURCE FALSE
-                INSTALL_DIR "${SURELOG_BINARY_DIR}"
-
-                # define Surelog cache values
-                CMAKE_CACHE_ARGS
-                "-DCMAKE_BUILD_TYPE:STRING=Release"
-                "-DCMAKE_INSTALL_PREFIX:PATH=${CMAKE_BINARY_DIR}"
-                "-DCMAKE_POSITION_INDEPENDENT_CODE:BOOL=ON"
-                "-DCMAKE_WARN_DEPRECATED:BOOL=OFF"
-
-                # redirect logs to a logfile
-                LOG_BUILD ON
-                LOG_UPDATE ON
-                LOG_INSTALL ON
-                LOG_CONFIGURE OFF
-                LOG_OUTPUT_ON_FAILURE ON
-
-                # dependency
-                DEPENDS  yosys
-                )
-
-     # Synlig integration (manages Surelog and UHDM internally)                
-
-        # Synlig integration (manages Surelog and UHDM internally)
-        set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig)
+    if (${SLANG_SYSTEMVERILOG})
+        set(SLANG_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-slang)
+        set(SLANG_BUILD_DIR ${CMAKE_BINARY_DIR}/yosys-slang)
+        #Initialize yosys-slang submodules
+        execute_process(
+	        COMMAND ${GIT_EXECUTABLE} submodule update --init
+	        WORKING_DIRECTORY ${SLANG_SRC_DIR}
+	    )
+	    execute_process(
+	        COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive ${GIT_EXECUTABLE}\ submodule\ update\ --init
+	        WORKING_DIRECTORY ${SLANG_SRC_DIR}
+	    )
+        set(SLANG_FE "${SLANG_SRC_DIR}/src/slang_frontend.cc")
+        ExternalProject_Add(
+            yosys-slang
+            SOURCE_DIR ${SLANG_SRC_DIR}
+            BINARY_DIR ${SLANG_BUILD_DIR}
+
+            #Disabling UndrivenPass in slang_frontend.cc
+            PATCH_COMMAND
+                ${CMAKE_COMMAND} -E echo "Patching slang_frontend.cc to disable UndrivenPass" &&
+                ${CMAKE_COMMAND} -DIN=${SLANG_FE} -P ${CMAKE_CURRENT_SOURCE_DIR}/patch_slang.cmake
+                
+            CONFIGURE_COMMAND ""
+            
+            # Sets location of yosys-config required by slang and suppresses warnings
+            BUILD_COMMAND 
+                ${CMAKE_COMMAND} -E env
+                    YOSYS_PREFIX=${CMAKE_BINARY_DIR}/bin/
+                ${MAKE_PROGRAM} -C ${SLANG_SRC_DIR}
+                    CMAKE_FLAGS="-DCMAKE_BUILD_TYPE=Release -DCMAKE_CXX_FLAGS=-w"
+                install
 
-        # Clone Synlig repository and ensure submodules are synced before building
-        ExternalProject_Add(synlig
-            PREFIX "synlig"
+            INSTALL_COMMAND ""
 
-            # Clone the Synlig repository
-            GIT_REPOSITORY https://github.com/chipsalliance/synlig.git
-            GIT_TAG main
-            GIT_PROGRESS TRUE
-            GIT_SHALLOW TRUE
+            DEPENDS yosys
 
-            # Set source and build directories
-            SOURCE_DIR "${SYNLIG_SOURCE_DIR}"
-            BUILD_IN_SOURCE FALSE
-            INSTALL_DIR " "
-            
-            # Sync submodules after cloning
-            
-            
-            UPDATE_COMMAND git submodule update --init --recursive third_party/surelog
-            WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR}
-            
-            BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT}
-            INSTALL_COMMAND ""
-            CONFIGURE_COMMAND ""
-            
-            # Pass necessary paths and set environment variables
-            CMAKE_CACHE_ARGS
-                "-DCMAKE_BUILD_TYPE:STRING=Release"
-                "-DSURELOG_PATH=${CMAKE_BINARY_DIR}/surelog"
-                "-DYOSYS_PATH=${CMAKE_BINARY_DIR}/yosys"
-                "-DUHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}"
-                "-DBUILD_DIR=${CMAKE_BINARY_DIR}/synlig-build"
-                "-DEXPORT_PATH=${CMAKE_BINARY_DIR}/synlig_install/usr/local/bin:$ENV{PATH}"
-            
-            LOG_BUILD ON
+            LOG_BUILD OFF
             LOG_UPDATE ON
             LOG_INSTALL ON
             LOG_CONFIGURE OFF
             LOG_OUTPUT_ON_FAILURE ON
-
-            # Ensure dependencies like Yosys are built first
-            DEPENDS yosys  # Ensure submodule sync runs before synlig build
+            
         )
-
     endif ()
 endif ()
 

libs/EXTERNAL/patch_slang.cmake

@@ -0,0 +1,18 @@
+# Patch step for yosys-slang
+#
+# The variable 'IN' points to vtr_root/libs/EXTERNAL/yosys-slang/src/slang_frontend.cc
+# This file contains the UndrivenPass that we want to disable
+#
+# This patch step finds the line where the UndrivenPass is called and comments out that line
+#
+# The UndrivenPass needs to be disabled due to unsupported synchronous rules in vtr_primitives.v
+
+if(NOT DEFINED IN)
+	message(FATAL_ERROR "patch_slang.cmake: IN (SLANG_FE) variable not set.")
+endif()
+file(READ "${IN}" SLANG_FRONTEND_CONTENTS)
+string(REPLACE "call(design, \"undriven\");" "// call(design, \"undriven\");" SLANG_PATCHED "${SLANG_FRONTEND_CONTENTS}")
+        if(NOT SLANG_FRONTEND_CONTENTS STREQUAL SLANG_PATCHED)
+            message(STATUS "Patching slang_frontend.cc to disable UndrivenPass")
+            file(WRITE "${IN}" "${SLANG_PATCHED}")
+        endif()

libs/EXTERNAL/yosys-slang

@@ -0,0 +1,24 @@
+#Parameters:
+#
+#	circuit_list - list of circuits passed into the flow
+#	file_list - text file being written to that will contain
+#	     		the names of circuits from circuit list.
+#
+#Function:
+#
+#	Validates file extensions of input files and writes the names
+#	of input files to the file list to be read by yosys-slang.
+ 
+proc build_filelist { circuit_list file_list } {
+	set fh [open $file_list "w"]
+	foreach f $circuit_list {
+		set ext [string tolower [file extension $f]]
+		if {$ext == ".sv" || $ext == ".svh" || $ext == ".v" || $ext == ".vh"} {
+			puts $fh $f
+		} else {
+			close $fh
+			error "Unsupported file type. Yosys-Slang accepts .sv .svh .v .vh. File {$f}"
+		}
+	}
+	close $fh
+}