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soheilshahrouzsoheilshahrouz
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use std::vector for arch.Switches
1 parent 419d8b6 commit 1cb8d5d

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9 files changed

+164
-227
lines changed

9 files changed

+164
-227
lines changed

‎libs/libarchfpga/src/arch_util.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -152,11 +152,10 @@ void free_arch(t_arch* arch) {
152152
return;
153153
}
154154

155-
delete[] arch->Switches;
156-
arch->Switches = nullptr;
157-
158155
free_arch_models(arch->models);
159156

157+
vtr::release_memory(arch->switches);
158+
160159
vtr::release_memory(arch->Directs);
161160

162161
vtr::free(arch->architecture_id);
@@ -230,7 +229,7 @@ t_model* free_arch_model(t_model* model) {
230229
return next_model;
231230
}
232231

233-
//Frees all the model portss in a linked list
232+
//Frees all the model ports in a linked list
234233
void free_arch_model_ports(t_model_ports* model_ports) {
235234
t_model_ports* model_port = model_ports;
236235
while (model_port) {

‎libs/libarchfpga/src/echo_arch.cpp‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -253,29 +253,29 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
253253
//13 is hard coded because format of %e is always 1.123456e+12
254254
//It always consists of 10 alphanumeric digits, a decimal
255255
//and a sign
256-
for (i = 0; i < arch->num_switches; i++) {
257-
if (arch->Switches[i].type() == SwitchType::MUX) {
258-
fprintf(Echo, "\tSwitch[%d]: name %s type mux\n", i + 1, arch->Switches[i].name.c_str());
259-
} else if (arch->Switches[i].type() == SwitchType::TRISTATE) {
260-
fprintf(Echo, "\tSwitch[%d]: name %s type tristate\n", i + 1, arch->Switches[i].name.c_str());
261-
} else if (arch->Switches[i].type() == SwitchType::SHORT) {
262-
fprintf(Echo, "\tSwitch[%d]: name %s type short\n", i + 1, arch->Switches[i].name.c_str());
263-
} else if (arch->Switches[i].type() == SwitchType::BUFFER) {
264-
fprintf(Echo, "\tSwitch[%d]: name %s type buffer\n", i + 1, arch->Switches[i].name.c_str());
256+
for (i = 0; i < (int)arch->switches.size(); i++) {
257+
if (arch->switches[i].type() == SwitchType::MUX) {
258+
fprintf(Echo, "\tSwitch[%d]: name %s type mux\n", i + 1, arch->switches[i].name.c_str());
259+
} else if (arch->switches[i].type() == SwitchType::TRISTATE) {
260+
fprintf(Echo, "\tSwitch[%d]: name %s type tristate\n", i + 1, arch->switches[i].name.c_str());
261+
} else if (arch->switches[i].type() == SwitchType::SHORT) {
262+
fprintf(Echo, "\tSwitch[%d]: name %s type short\n", i + 1, arch->switches[i].name.c_str());
263+
} else if (arch->switches[i].type() == SwitchType::BUFFER) {
264+
fprintf(Echo, "\tSwitch[%d]: name %s type buffer\n", i + 1, arch->switches[i].name.c_str());
265265
} else {
266-
VTR_ASSERT(arch->Switches[i].type() == SwitchType::PASS_GATE);
267-
fprintf(Echo, "\tSwitch[%d]: name %s type pass_gate\n", i + 1, arch->Switches[i].name.c_str());
266+
VTR_ASSERT(arch->switches[i].type() == SwitchType::PASS_GATE);
267+
fprintf(Echo, "\tSwitch[%d]: name %s type pass_gate\n", i + 1, arch->switches[i].name.c_str());
268268
}
269-
fprintf(Echo, "\t\t\t\tR %e Cin %e Cout %e\n", arch->Switches[i].R,
270-
arch->Switches[i].Cin, arch->Switches[i].Cout);
269+
fprintf(Echo, "\t\t\t\tR %e Cin %e Cout %e\n", arch->switches[i].R,
270+
arch->switches[i].Cin, arch->switches[i].Cout);
271271
fprintf(Echo, "\t\t\t\t#Tdel values %d buf_size %e mux_trans_size %e\n",
272-
(int)arch->Switches[i].Tdel_map_.size(), arch->Switches[i].buf_size,
273-
arch->Switches[i].mux_trans_size);
274-
if (arch->Switches[i].power_buffer_type == POWER_BUFFER_TYPE_AUTO) {
272+
(int)arch->switches[i].Tdel_map_.size(), arch->switches[i].buf_size,
273+
arch->switches[i].mux_trans_size);
274+
if (arch->switches[i].power_buffer_type == POWER_BUFFER_TYPE_AUTO) {
275275
fprintf(Echo, "\t\t\t\tpower_buffer_size auto\n");
276276
} else {
277277
fprintf(Echo, "\t\t\t\tpower_buffer_size %e\n",
278-
arch->Switches[i].power_buffer_size);
278+
arch->switches[i].power_buffer_size);
279279
}
280280
}
281281

@@ -293,19 +293,19 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
293293
if (seg.directionality == UNI_DIRECTIONAL) {
294294
//wire_switch == arch_opin_switch
295295
fprintf(Echo, "\t\t\t\ttype unidir mux_name for within die connections: %s\n",
296-
arch->Switches[seg.arch_wire_switch].name.c_str());
296+
arch->switches[seg.arch_wire_switch].name.c_str());
297297
//if there is more than one layer available, print the segment switch name that is used for connection between two dice
298298
for (const auto& layout : arch->grid_layouts) {
299299
int num_layers = (int)layout.layers.size();
300300
if (num_layers > 1) {
301301
fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n",
302-
arch->Switches[seg.arch_opin_between_dice_switch].name.c_str());
302+
arch->switches[seg.arch_opin_between_dice_switch].name.c_str());
303303
}
304304
}
305305
} else { //Should be bidir
306306
fprintf(Echo, "\t\t\t\ttype bidir wire_switch %s arch_opin_switch %s\n",
307-
arch->Switches[seg.arch_wire_switch].name.c_str(),
308-
arch->Switches[seg.arch_opin_switch].name.c_str());
307+
arch->switches[seg.arch_wire_switch].name.c_str(),
308+
arch->switches[seg.arch_opin_switch].name.c_str());
309309
}
310310

311311
fprintf(Echo, "\t\t\t\tcb ");

‎libs/libarchfpga/src/parse_switchblocks.cpp‎

Lines changed: 15 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -41,16 +41,16 @@ using vtr::t_formula_data;
4141
/*---- Functions for Parsing Switchblocks from Architecture ----*/
4242

4343
//Load an XML wireconn specification into a t_wireconn_inf
44-
t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const t_arch_switch_inf* switches, int num_switches);
44+
static t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const std::vector<t_arch_switch_inf>& switches);
4545

4646
//Process the desired order of a wireconn
4747
static void parse_switchpoint_order(const char* order, SwitchPointOrder& switchpoint_order);
4848

4949
//Process a wireconn defined in the inline style (using attributes)
50-
void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches);
50+
static void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector<t_arch_switch_inf>& switches);
5151

5252
//Process a wireconn defined in the multinode style (more advanced specification)
53-
void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches);
53+
static void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector<t_arch_switch_inf>& switches);
5454

5555
//Process a <from> or <to> sub-node of a multinode wireconn
5656
t_wire_switchpoints parse_wireconn_from_to_node(pugi::xml_node node, const pugiutil::loc_data& loc_data);
@@ -69,7 +69,7 @@ static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn);
6969
static void set_switch_func_type(SB_Side_Connection& conn, const char* func_type);
7070

7171
/* parse switch_override in wireconn */
72-
static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const t_arch_switch_inf* switches, int num_switches);
72+
static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const std::vector<t_arch_switch_inf>& switches);
7373

7474
/* checks for correctness of a unidir switchblock. */
7575
static void check_unidir_switchblock(const t_switchblock_inf* sb);
@@ -85,7 +85,7 @@ static void check_wireconn(const t_arch* arch, const t_wireconn_inf& wireconn);
8585
/*---- Functions for Parsing Switchblocks from Architecture ----*/
8686

8787
/* Reads-in the wire connections specified for the switchblock in the xml arch file */
88-
void read_sb_wireconns(const t_arch_switch_inf* switches, int num_switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data) {
88+
void read_sb_wireconns(const std::vector<t_arch_switch_inf>& switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data) {
8989
/* Make sure that Node is a switchblock */
9090
check_node(Node, "switchblock", loc_data);
9191

@@ -100,31 +100,29 @@ void read_sb_wireconns(const t_arch_switch_inf* switches, int num_switches, pugi
100100
SubElem = get_first_child(Node, "wireconn", loc_data);
101101
}
102102
for (int i = 0; i < num_wireconns; i++) {
103-
t_wireconn_inf wc = parse_wireconn(SubElem, loc_data, switches, num_switches); // need to pass in switch info for switch override
103+
t_wireconn_inf wc = parse_wireconn(SubElem, loc_data, switches); // need to pass in switch info for switch override
104104
sb->wireconns.push_back(wc);
105105
SubElem = SubElem.next_sibling(SubElem.name());
106106
}
107-
108-
return;
109107
}
110108

111-
t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const t_arch_switch_inf* switches, int num_switches) {
109+
static t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const std::vector<t_arch_switch_inf>& switches) {
112110
t_wireconn_inf wc;
113111

114112
size_t num_children = count_children(node, "from", loc_data, ReqOpt::OPTIONAL);
115113
num_children += count_children(node, "to", loc_data, ReqOpt::OPTIONAL);
116114

117115
if (num_children == 0) {
118-
parse_wireconn_inline(node, loc_data, wc, switches, num_switches);
116+
parse_wireconn_inline(node, loc_data, wc, switches);
119117
} else {
120118
VTR_ASSERT(num_children > 0);
121-
parse_wireconn_multinode(node, loc_data, wc, switches, num_switches);
119+
parse_wireconn_multinode(node, loc_data, wc, switches);
122120
}
123121

124122
return wc;
125123
}
126124

127-
void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches) {
125+
static void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector<t_arch_switch_inf>& switches) {
128126
//Parse an inline wireconn definition, using attributes
129127
expect_only_attributes(node, {"num_conns", "from_type", "to_type", "from_switchpoint", "to_switchpoint", "from_order", "to_order", "switch_override"}, loc_data);
130128

@@ -156,10 +154,10 @@ void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_da
156154

157155
// parse switch overrides if they exist:
158156
char_prop = get_attribute(node, "switch_override", loc_data, ReqOpt::OPTIONAL).value();
159-
parse_switch_override(char_prop, wc, switches, num_switches);
157+
parse_switch_override(char_prop, wc, switches);
160158
}
161159

162-
void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches) {
160+
void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector<t_arch_switch_inf>& switches) {
163161
expect_only_children(node, {"from", "to"}, loc_data);
164162

165163
/* get the connection style */
@@ -173,7 +171,7 @@ void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc
173171
parse_switchpoint_order(char_prop, wc.to_switchpoint_order);
174172

175173
char_prop = get_attribute(node, "switch_override", loc_data, ReqOpt::OPTIONAL).value();
176-
parse_switch_override(char_prop, wc, switches, num_switches);
174+
parse_switch_override(char_prop, wc, switches);
177175

178176
size_t num_from_children = count_children(node, "from", loc_data);
179177
size_t num_to_children = count_children(node, "to", loc_data);
@@ -378,19 +376,17 @@ void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiu
378376
/* get the next switchblock function */
379377
SubElem = SubElem.next_sibling(SubElem.name());
380378
}
381-
382-
return;
383379
}
384380

385-
static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const t_arch_switch_inf* switches, int num_switches) {
381+
static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const std::vector<t_arch_switch_inf>& switches) {
386382
// sentinel value to use default driving switch for the receiving wire type
387383
if (switch_override == std::string("")) {
388384
wireconn.switch_override_indx = DEFAULT_SWITCH; //Default
389385
return;
390386
}
391387

392388
// iterate through the valid switch names in the arch looking for the requested switch_override
393-
for (int i = 0; i < num_switches; i++) {
389+
for (int i = 0; i < (int)switches.size(); i++) {
394390
if (0 == strcmp(switch_override, switches[i].name.c_str())) {
395391
wireconn.switch_override_indx = i;
396392
return;

‎libs/libarchfpga/src/parse_switchblocks.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data);
1212

1313
/* Reads-in the wire connections specified for the switchblock in the xml arch file */
14-
void read_sb_wireconns(const t_arch_switch_inf* switches, int num_switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data);
14+
void read_sb_wireconns(const std::vector<t_arch_switch_inf>& switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data);
1515

1616
/* checks for correctness of switch block read-in from the XML architecture file */
1717
void check_switchblock(const t_switchblock_inf* sb, const t_arch* arch);

‎libs/libarchfpga/src/physical_types.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2059,8 +2059,8 @@ struct t_arch {
20592059
int Fs;
20602060
float grid_logic_tile_area;
20612061
std::vector<t_segment_inf> Segments;
2062-
t_arch_switch_inf* Switches = nullptr;
2063-
int num_switches;
2062+
2063+
std::vector<t_arch_switch_inf> switches;
20642064
std::vector<t_direct_inf> Directs;
20652065

20662066
t_model* models = nullptr;

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2374,15 +2374,13 @@ struct ArchReader {
23742374
size_t num_switches = pip_timing_models.size() + 2;
23752375
std::string switch_name;
23762376

2377-
arch_->num_switches = num_switches;
2378-
23792377
if (num_switches > 0) {
2380-
arch_->Switches = new t_arch_switch_inf[num_switches];
2378+
arch_->switches.resize(num_switches);
23812379
}
23822380

23832381
float R, Cin, Cint, Cout, Tdel;
23842382
for (size_t i = 0; i < num_switches; ++i) {
2385-
t_arch_switch_inf* as = &arch_->Switches[i];
2383+
t_arch_switch_inf* as = &arch_->switches[i];
23862384

23872385
R = Cin = Cint = Cout = Tdel = 0.0;
23882386
SwitchType type;

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