Merge pull request #3157 from verilog-to-routing/sm_remove_twist_attr

Removed twist attribute from RR graph

Author: AlexandreSinger

libs/librrgraph/src/base/rr_graph_builder.cpp

@@ -26,13 +26,9 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) {
     e_rr_type node_type = node_storage_.node_type(node);
     short node_ptc_num = node_storage_.node_ptc_num(node);
     short node_layer = node_storage_.node_layer(node);
-    short node_twist = node_storage_.node_ptc_twist(node);
-    int node_offset = 0;
 
     for (int ix = node_storage_.node_xlow(node); ix <= node_storage_.node_xhigh(node); ix++) {
         for (int iy = node_storage_.node_ylow(node); iy <= node_storage_.node_yhigh(node); iy++) {
-            node_ptc_num += node_twist * node_offset;
-            node_offset++;
 
             switch (node_type) {
                 case e_rr_type::SOURCE:

libs/librrgraph/src/base/rr_graph_builder.h

@@ -205,11 +205,6 @@ class RRGraphBuilder {
         node_storage_.set_node_layer(id, layer);
     }
 
-    /** @brief set the ptc twist increment number for TILEABLE rr graphs (for more information see rr_graph_storage.h twist increment comment) */
-    inline void set_node_ptc_twist_incr(RRNodeId id, int twist){
-        node_storage_.set_node_ptc_twist_incr(id, twist);
-    }
-
 
     /** @brief set_node_pin_num() is designed for logic blocks, which are IPIN and OPIN nodes */
     inline void set_node_pin_num(RRNodeId id, int new_pin_num) {
@@ -325,11 +320,6 @@ class RRGraphBuilder {
         node_storage_.resize(size);
     }
 
-    /** @brief This function resize node ptc twist increment; Since it is only used for tileable rr-graph, we don't put it in general resize function*/
-    inline void resize_ptc_twist_incr(size_t size){
-        node_storage_.resize(size);
-    }
-
     /** @brief This function resize rr_switch to accomidate size RR Switch. */
     inline void resize_switches(size_t size) {
         rr_switch_inf_.resize(size);

libs/librrgraph/src/base/rr_graph_storage.cpp

@@ -635,11 +635,6 @@ void t_rr_graph_storage::set_node_layer(RRNodeId id, short layer) {
     node_layer_[id] = layer;
 }
 
-void t_rr_graph_storage::set_node_ptc_twist_incr(RRNodeId id, short twist_incr){
-    VTR_ASSERT(!node_ptc_twist_incr_.empty());
-    node_ptc_twist_incr_[id] = twist_incr;
-}
-
 void t_rr_graph_storage::set_node_ptc_num(RRNodeId id, int new_ptc_num) {
     node_ptc_[id].ptc_.pin_num = new_ptc_num; //TODO: eventually remove
 }
@@ -821,7 +816,6 @@ t_rr_graph_view t_rr_graph_storage::view() const {
         vtr::make_const_array_view_id(node_fan_in_),
         vtr::make_const_array_view_id(node_layer_),
         node_name_,
-        vtr::make_const_array_view_id(node_ptc_twist_incr_),
         vtr::make_const_array_view_id(edge_src_node_),
         vtr::make_const_array_view_id(edge_dest_node_),
         vtr::make_const_array_view_id(edge_switch_),

libs/librrgraph/src/base/rr_graph_storage.h

@@ -251,18 +251,6 @@ class t_rr_graph_storage {
         return std::nullopt;  // Return an empty optional if key is not found
     }
 
-    /** @brief Find the twist number that RR node uses to change ptc number across the same track.
-     * By default this number is zero, meaning that ptc number across the same track should be the same.
-     * This number is only meaningful for CHANX/CHANY nodes, not the other nodes.
-     */
-    short node_ptc_twist(RRNodeId id) const{
-        //check whether node_ptc_twist_incr has been allocated
-        if(node_ptc_twist_incr_.empty()){
-            return 0;
-        }
-        return node_ptc_twist_incr_[id];
-    }
-
     /**
      * @brief Returns the node ID of the virtual sink for the specified clock network name.
      *
@@ -504,7 +492,6 @@ class t_rr_graph_storage {
         node_ptc_.reserve(node_storage_.capacity());
         node_ptc_.resize(node_storage_.size());
         node_layer_.resize(node_storage_.size());
-        node_ptc_twist_incr_.resize(node_storage_.size());
     }
 
     /** @brief  Reserve storage for RR nodes. */
@@ -525,11 +512,6 @@ class t_rr_graph_storage {
         node_layer_.resize(size);
     }
 
-    /** @brief We only allocate the ptc twist increment array while building tileable rr-graphs */
-    void resize_ptc_twist_incr(size_t size){
-        node_ptc_twist_incr_.resize(size);
-    }
-
     /** @brief Number of RR nodes that can be accessed. */
     size_t size() const {
         return node_storage_.size();
@@ -551,7 +533,6 @@ class t_rr_graph_storage {
         node_layer_.clear();
         node_name_.clear();
         virtual_clock_network_root_idx_.clear();
-        node_ptc_twist_incr_.clear();
         edge_src_node_.clear();
         edge_dest_node_.clear();
         edge_switch_.clear();
@@ -585,7 +566,6 @@ class t_rr_graph_storage {
         node_first_edge_.shrink_to_fit();
         node_fan_in_.shrink_to_fit();
         node_layer_.shrink_to_fit();
-        node_ptc_twist_incr_.shrink_to_fit();
         edge_src_node_.shrink_to_fit();
         edge_dest_node_.shrink_to_fit();
         edge_switch_.shrink_to_fit();
@@ -620,7 +600,6 @@ class t_rr_graph_storage {
     void set_node_name(RRNodeId id, const std::string& new_name);
     void set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2);
     void set_node_layer(RRNodeId id, short layer);
-    void set_node_ptc_twist_incr(RRNodeId id, short twist);
     void set_node_cost_index(RRNodeId, RRIndexedDataId new_cost_index);
     void set_node_rc_index(RRNodeId, NodeRCIndex new_rc_index);
     void set_node_capacity(RRNodeId, short new_capacity);
@@ -872,15 +851,6 @@ class t_rr_graph_storage {
      */
     std::unordered_map<std::string, RRNodeId> virtual_clock_network_root_idx_;
 
-    /** @brief
-     *Twist Increment number is defined for CHANX/CHANY nodes; it is useful for layout of tileable FPGAs used by openFPGA.
-     *It gives us a new track index in each tile a longer wire crosses, which enables us to make long wires with a repeated single-tile pattern that "twists" the wires as they cross the tile.
-     *For example, an L4 wire would change tracks 4 times with metal shorts [e.g. 0, 2, 4, 6] and track 6 would drive a switch -- together this implements an L4 wire with only one layout tile.
-     * Twist increment number is only meaningful for CHANX and CHANY nodes; it is 0 for other node types.
-     * We also don't bother allocating this storage if the FPGA is not specified to be tileable; instead in that case the twist for all nodes will always be returned as 0.
-     */
-    vtr::vector<RRNodeId, short> node_ptc_twist_incr_;
-
     /** @brief Edge storage */
     vtr::vector<RREdgeId, RRNodeId> edge_src_node_;
     vtr::vector<RREdgeId, RRNodeId> edge_dest_node_;
@@ -954,7 +924,6 @@ class t_rr_graph_view {
         const vtr::array_view_id<RRNodeId, const t_edge_size> node_fan_in,
         const vtr::array_view_id<RRNodeId, const short> node_layer,
         const std::unordered_map<RRNodeId, std::string>& node_name,
-        const vtr::array_view_id<RRNodeId, const short> node_ptc_twist_incr,
         const vtr::array_view_id<RREdgeId, const RRNodeId> edge_src_node,
         const vtr::array_view_id<RREdgeId, const RRNodeId> edge_dest_node,
         const vtr::array_view_id<RREdgeId, const short> edge_switch,
@@ -965,7 +934,6 @@ class t_rr_graph_view {
         , node_fan_in_(node_fan_in)
         , node_layer_(node_layer)
         , node_name_(node_name)
-        , node_ptc_twist_incr_(node_ptc_twist_incr)
         , edge_src_node_(edge_src_node)
         , edge_dest_node_(edge_dest_node)
         , edge_switch_(edge_switch)
@@ -1055,20 +1023,6 @@ class t_rr_graph_view {
         return std::nullopt;  // Return an empty optional if key is not found
     }
 
-    /**
-     * @brief Retrieve the twist number (if available) that the given RRNodeId used for its PTC number.
-     *
-     * @param id The RRNodeId for which to retrieve the twist number.
-     * @return The twist number used for the PTC number, or a default value if not available.
-     */
-    short node_ptc_twist_incr(RRNodeId id) const{
-        //check if ptc twist increment allocated
-        if(node_ptc_twist_incr_.empty()){
-            return 0; //if it is not allocated we just assume that is zero
-        }
-        return node_ptc_twist_incr_[id];
-    }
-
     /**
      * @brief Prefetches hot RR node data required for optimization.
      *
@@ -1183,7 +1137,6 @@ class t_rr_graph_view {
     vtr::array_view_id<RRNodeId, const t_edge_size> node_fan_in_;
     vtr::array_view_id<RRNodeId, const short> node_layer_;
     const std::unordered_map<RRNodeId, std::string>& node_name_;
-    vtr::array_view_id<RRNodeId, const short> node_ptc_twist_incr_;
     vtr::array_view_id<RREdgeId, const RRNodeId> edge_src_node_;
     vtr::array_view_id<RREdgeId, const RRNodeId> edge_dest_node_;
     vtr::array_view_id<RREdgeId, const short> edge_switch_;

libs/librrgraph/src/base/rr_graph_view.h

@@ -223,12 +223,6 @@ class RRGraphView {
         return node_storage_.node_layer(node);
     }
 
-    /** @brief Return the ptc number twist of a specified node.
-    */
-    inline short node_ptc_twist(RRNodeId node) const {
-        return node_storage_.node_ptc_twist(node);
-    }
-
     /** @brief Return the first outgoing edge of a specified node.
     */
     inline RREdgeId node_first_edge(RRNodeId node) const {

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h

@@ -4,10 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
-
- * md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
+ * Cmdline: uxsdcxx/uxsdcxx.py /home/smahmoudi/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/smahmoudi/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: dcf32619cae0c49d168a2575bdb00896
  */
 
 #include <functional>
@@ -202,15 +201,10 @@ inline void write_rr_graph_xml(T &in, Context &context, std::ostream &os){
 }
 
 
-#if defined(_MSC_VER)
-typedef const uint32_t __declspec(align(1)) triehash_uu32;
-typedef const uint64_t __declspec(align(1)) triehash_uu64;
-#else
 typedef const uint32_t __attribute__((aligned(1))) triehash_uu32;
 typedef const uint64_t __attribute__((aligned(1))) triehash_uu64;
 static_assert(alignof(triehash_uu32) == 1, "Unaligned 32-bit access not found.");
 static_assert(alignof(triehash_uu64) == 1, "Unaligned 64-bit access not found.");
-#endif
 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
 #define onechar(c, s, l) (((uint64_t)(c)) << (s))
 #else
@@ -281,8 +275,8 @@ constexpr const char *atok_lookup_t_grid_loc[] = {"block_type_id", "height_offse
 enum class gtok_t_grid_locs {GRID_LOC};
 constexpr const char *gtok_lookup_t_grid_locs[] = {"grid_loc"};
 
-enum class atok_t_node_loc {LAYER, PTC, SIDE, TWIST, XHIGH, XLOW, YHIGH, YLOW};
-constexpr const char *atok_lookup_t_node_loc[] = {"layer", "ptc", "side", "twist", "xhigh", "xlow", "yhigh", "ylow"};
+enum class atok_t_node_loc {LAYER, PTC, SIDE, XHIGH, XLOW, YHIGH, YLOW};
+constexpr const char *atok_lookup_t_node_loc[] = {"layer", "ptc", "side", "xhigh", "xlow", "yhigh", "ylow"};
 
 
 enum class atok_t_node_timing {C, R};
@@ -1170,14 +1164,6 @@ inline atok_t_node_loc lex_attr_t_node_loc(const char *in, const std::function<v
 			default: break;
 			}
 		break;
-		case onechar('t', 0, 32) | onechar('w', 8, 32) | onechar('i', 16, 32) | onechar('s', 24, 32):
-			switch(in[4]){
-			case onechar('t', 0, 8):
-				return atok_t_node_loc::TWIST;
-			break;
-			default: break;
-			}
-		break;
 		case onechar('x', 0, 32) | onechar('h', 8, 32) | onechar('i', 16, 32) | onechar('g', 24, 32):
 			switch(in[4]){
 			case onechar('h', 0, 8):
@@ -2475,7 +2461,7 @@ inline void load_grid_loc_required_attributes(const pugi::xml_node &root, int *
 }
 
 inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * ptc, int * xhigh, int * xlow, int * yhigh, int * ylow, const std::function<void(const char *)> * report_error){
-	std::bitset<8> astate = 0;
+	std::bitset<7> astate = 0;
 	for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){
 		atok_t_node_loc in = lex_attr_t_node_loc(attr.name(), report_error);
 		if(astate[(int)in] == 0) astate[(int)in] = 1;
@@ -2490,9 +2476,6 @@ inline void load_node_loc_required_attributes(const pugi::xml_node &root, int *
 		case atok_t_node_loc::SIDE:
 			/* Attribute side set after element init */
 			break;
-		case atok_t_node_loc::TWIST:
-			/* Attribute twist set after element init */
-			break;
 		case atok_t_node_loc::XHIGH:
 			*xhigh = load_int(attr.value(), report_error);
 			break;
@@ -2508,7 +2491,7 @@ inline void load_node_loc_required_attributes(const pugi::xml_node &root, int *
 		default: break; /* Not possible. */
 		}
 	}
-	std::bitset<8> test_astate = astate | std::bitset<8>(0b00001101);
+	std::bitset<7> test_astate = astate | std::bitset<7>(0b0000101);
 	if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_node_loc, report_error);
 }
 
@@ -3432,9 +3415,6 @@ inline void load_node_loc(const pugi::xml_node &root, T &out, Context &context,
 		case atok_t_node_loc::SIDE:
 			out.set_node_loc_side(lex_enum_loc_side(attr.value(), true, report_error), context);
 			break;
-		case atok_t_node_loc::TWIST:
-			out.set_node_loc_twist(load_int(attr.value(), report_error), context);
-			break;
 		case atok_t_node_loc::XHIGH:
 			/* Attribute xhigh is already set */
 			break;
@@ -4175,8 +4155,6 @@ inline void write_node(T &in, std::ostream &os, Context &context){
 		os << " ptc=\"" << in.get_node_loc_ptc(child_context) << "\"";
 		if((bool)in.get_node_loc_side(child_context))
 			os << " side=\"" << lookup_loc_side[(int)in.get_node_loc_side(child_context)] << "\"";
-		if((bool)in.get_node_loc_twist(child_context))
-			os << " twist=\"" << in.get_node_loc_twist(child_context) << "\"";
 		os << " xhigh=\"" << in.get_node_loc_xhigh(child_context) << "\"";
 		os << " xlow=\"" << in.get_node_loc_xlow(child_context) << "\"";
 		os << " yhigh=\"" << in.get_node_loc_yhigh(child_context) << "\"";

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h

@@ -4,10 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: uxsdcxx/uxsdcap.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
-
- * md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
+ * Cmdline: uxsdcxx/uxsdcap.py /home/smahmoudi/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/smahmoudi/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: dcf32619cae0c49d168a2575bdb00896
  */
 
 #include <functional>
@@ -764,7 +763,6 @@ inline void load_node_loc_capnp_type(const ucap::NodeLoc::Reader &root, T &out,
 
 	out.set_node_loc_layer(root.getLayer(), context);
 	out.set_node_loc_side(conv_enum_loc_side(root.getSide(), report_error), context);
-	out.set_node_loc_twist(root.getTwist(), context);
 }
 
 template<class T, typename Context>
@@ -1224,8 +1222,6 @@ inline void write_node_capnp_type(T &in, ucap::Node::Builder &root, Context &con
 		node_loc.setPtc(in.get_node_loc_ptc(child_context));
 		if((bool)in.get_node_loc_side(child_context))
 			node_loc.setSide(conv_to_enum_loc_side(in.get_node_loc_side(child_context)));
-		if((bool)in.get_node_loc_twist(child_context))
-			node_loc.setTwist(in.get_node_loc_twist(child_context));
 		node_loc.setXhigh(in.get_node_loc_xhigh(child_context));
 		node_loc.setXlow(in.get_node_loc_xlow(child_context));
 		node_loc.setYhigh(in.get_node_loc_yhigh(child_context));