Add. Underflow check in posit round

Author: arunkmv

src/main/scala/PositRound.scala

@@ -34,15 +34,17 @@ class PositRound(val nbits: Int, val es: Int) extends Module with HasHardPositPa
   val fracOverflow = roundFrac(maxFractionBitsWithHiddenBit)
 
   val roundExp = WireInit(SInt((maxExponentBits + 1).W), io.in.exponent +& fracOverflow.zext)
-  val overflow = roundExp >= maxExponent.S
+  val overflow  = roundExp >= maxExponent.S
+  val underflow = roundExp <  minExponent.S
 
   io.out.exponent :=
-    Mux(io.in.isNaR || io.in.isZero,
-      0.S, Mux(overflow,
-        maxExponent.S, roundExp))
+    Mux(io.in.isNaR || io.in.isZero, 0.S,
+      Mux(overflow, maxExponent.S,
+        Mux(underflow, minExponent.S,
+          roundExp)))
 
   io.out.fraction :=
-    Mux(fracOverflow || overflow || io.in.isNaR || io.in.isZero,
+    Mux(fracOverflow || overflow || underflow || io.in.isNaR || io.in.isZero,
       Cat(1.U, 0.U(maxFractionBits.W)),
       roundFrac)
 }

src/main/scala/common.scala

@@ -66,8 +66,12 @@ trait HasHardPositParams {
 
   def maxRegime: Int = nbits - 2
 
+  def minRegime: Int = -maxRegime
+
   def maxExponent: Int = maxRegime * (1 << es)
 
+  def minExponent: Int = minRegime * (1 << es)
+
   def maxSignedInteger(w: Int): Int = (1 << (w - 1)) - 1
 
   def maxUnsignedInteger(w: Int): Int = (1 << w) - 1

src/test/scala/PositRoundSpec.scala

@@ -48,5 +48,7 @@ class PositRoundSpec extends ChiselFlatSpec {
     assert(test(16, 1, false, 0x1C, 0x1FFF, false, false, 3, true, 0x1C, 0x1000))
   }
 
-
+  it should "round to minpos if underflow" in {
+    assert(test(16, 1, false, -0x1D, 0x1FFF, false, false, 0, false, -0x1C, 0x1000))
+  }
 }