From 9597eb5136e3090b142e715e1b885103e16619f2 Mon Sep 17 00:00:00 2001 From: mw Date: Wed, 12 Aug 2026 17:38:56 -0400 Subject: [PATCH 1/2] mb/system76/rpl: Select DRIVERS_INTEL_PMC and DRIVERS_INTEL_USB4_RETIMER The adl baseboard selects both of these; rpl selects neither. They gate the build of the devicetree chip drivers used to describe a TCSS Type-C port: - drivers/intel/pmc_mux/Makefile.mk builds mux.c and conn/conn.c only when CONFIG_DRIVERS_INTEL_PMC is set - drivers/intel/usb4/retimer is gated on CONFIG_DRIVERS_INTEL_USB4_RETIMER Without them, a variant that adds "chip drivers/intel/pmc_mux" or "chip drivers/intel/usb4/retimer" to its overridetree fails to link. This commit has no functional effect on its own, and none on any variant that does not use those drivers. It is a prerequisite for the lemp12 change that follows. TEST=Builds for lemp12. No change to the built image: with no variant using these drivers yet, the .config gains the two symbols but no additional objects are linked. Change-Id: Iada38a12a1157c5190084aa7c893c13c2f29d236 Signed-off-by: mw --- src/mainboard/system76/rpl/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index b4b71d5bdb7..3779c392296 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -8,6 +8,8 @@ config BOARD_SYSTEM76_RPL_COMMON select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER select EC_SYSTEM76_EC select EC_SYSTEM76_EC_LOCKDOWN select HAVE_ACPI_RESUME From 3f55b23e030f8505dd433c5606b34c142b6355be Mon Sep 17 00:00:00 2001 From: mw Date: Wed, 12 Aug 2026 17:39:31 -0400 Subject: [PATCH 2/2] mb/system76/lemp12: Enable TCSS Type-C port, PMC mux and retimer lemp12's sole USB-C connector (J_TYPEC1) never operates above USB 2.0 and DisplayPort alt-mode never engages. Reported in firmware-open#675. soc/intel/alderlake fill_fsps_tcss_params() derives UsbTcPortEn from whether the devicetree device tcss_usb3_port1 is enabled: s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) if (is_dev_enabled(tcss_port_arr[i])) s_cfg->UsbTcPortEn |= BIT(i); chipset.cb defaults tcss_root_hub and tcss_usb3_port1 to off, the rpl baseboard declares no TCSS section, and no rpl variant enables them, so the bit stays clear and FSP-S never enables the Type-C port. The connector's USB2 pair routes to the PCH and keeps working, which is why the port enumerates devices at 480 Mbps while its SuperSpeed lanes stay dark. Enable the port and describe it the way the adl variants do. The per-port drivers/usb/acpi descriptors under xhci are added at the same time, since the pmc_mux conn node references usb2_port3 and the board has no per-port descriptors at all today. Upstream CB:94134 adds those descriptors to all twelve rpl variants; if that lands here first, that hunk can be dropped. GPP_E4 is this board's retimer force-power pad, declared in its own gpio.c as TBT_FORCE_PWR and confirmed against the Clevo L140AU schematic (board 6-71-L14A0-D02A): PCH ball FC22 -> GPPE4_TBT_FORCE_PWR -> R411 (0R, populated) -> TC_RETIMER_FORCE_PWR -> JHL8040R FORCE_PWR ball A9. All adl variants (7/7) enable tcss_usb3_port1; no rpl variant (0/12) does. The same split holds for tgl-u and mtl, which suggests the rpl directory was created without carrying the Type-C stack over. Reading their overridetrees, darp9, galp7 and oryp11 look affected the same way -- in each case the Type-C connector with no PCH usb3_ports[] entry is the one users report as broken (firmware-open#472 for oryp11, #497 for darp9). I have deliberately left those boards alone: I do not own them and cannot test them, so this change is scoped to the one board I can verify on. The same blocks should apply, with the conn alias and the retimer pad adjusted per board. TEST=Builds for lemp12 on the current release (2025-07-24_c242738). Generated static.c has _dev_tcss_usb3_port1 .enabled = 0 before this change and 1 after, and gains drivers_intel_pmc_mux_ops, drivers_intel_pmc_mux_conn_ops and drivers_intel_usb4_retimer_ops. Comparing a stock and a patched ROM built from the same tree: identical CBFS file set, FSP, microcode, payload and bootblock bit-for-bit unchanged, fallback/ramstage +2189 B and romstage +768 B. The string INTC105C appears only in the patched ramstage, and decoding the device array out of the extracted ramstage shows tcss_usb3_port1 .enabled going 0 -> 1, so the bit reaches the image that would be flashed. NOT tested on hardware. This machine's SPI flash is a leadless WSON-8 part with no external programmer attached and the flash map has a single COREBOOT region, so I have not flashed it. The runtime behaviour is unverified; I will follow up once I have flashed it, and would welcome anyone with a bench unit testing it first. Change-Id: I69f5f7ceef1f39a2be4a28a24270e9650589f915 Signed-off-by: mw --- .../rpl/variants/lemp12/overridetree.cb | 79 ++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb index c84628b6acc..bff6e8d2a40 100644 --- a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb @@ -12,8 +12,23 @@ chip soc/intel/alderlake device ref tbt_pcie_rp0 on end device ref tcss_xhci on register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end end - device ref tcss_dma0 on end device ref xhci on register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Left */ @@ -28,6 +43,56 @@ chip soc/intel/alderlake [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Right */ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* 3G/LTE */ }" + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Left"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right"" + register "type" = "UPC_TYPE_A" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 3G/LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Left"" + register "type" = "UPC_TYPE_A" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_A" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb3_port3 on end + end + end + end end device ref i2c0 on @@ -84,5 +149,17 @@ chip soc/intel/alderlake .pcie_rp_detect_timeout_ms = 50, }" end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # J_TYPEC1 + use usb2_port3 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end end end