Add detailed MMU cache statistics for fetch path

Introduce fine-grained counters to replace the previous aggregated
fetch hit/miss statistics. The new metrics track:
- total fetches
- icache hits/misses
- victim cache hits/misses
- TLB hits/misses

The old MMU statistics only distinguished total fetch hits/misses,
which no longer reflect real performance after the addition of
icache and victim cache layers. This change enables more accurate
profiling and debugging.

This provides a clearer view of instruction fetch performance and helps
identify which cache level contributes most to stalls or misses.

Author: yy214123

main.c

@@ -1024,11 +1024,31 @@ static void print_mmu_cache_stats(vm_t *vm)
     fprintf(stderr, "\n=== MMU Cache Statistics ===\n");
     for (uint32_t i = 0; i < vm->n_hart; i++) {
         hart_t *hart = vm->hart[i];
-        uint64_t fetch_hits = 0, fetch_misses = 0;
-        fetch_hits = hart->cache_fetch[1].hits + hart->cache_fetch[2].hits;
-        fetch_misses =
-            hart->cache_fetch[1].misses + hart->cache_fetch[2].misses;
-        uint64_t fetch_total = fetch_hits + fetch_misses;
+
+        /* Combine 2-entry tlb statistics */
+        uint64_t fetch_hits_tlb = 0, fetch_misses_tlb = 0;
+        fetch_hits_tlb =
+            hart->cache_fetch[0].tlb_hits + hart->cache_fetch[1].tlb_hits;
+        fetch_misses_tlb =
+            hart->cache_fetch[0].tlb_misses + hart->cache_fetch[1].tlb_misses;
+        uint64_t tlb_total = fetch_hits_tlb + fetch_misses_tlb;
+
+        /* Combine icache statistics */
+        uint64_t fetch_hits_icache = 0, fetch_misses_icache = 0;
+        fetch_hits_icache =
+            hart->cache_fetch[0].icache_hits + hart->cache_fetch[1].icache_hits;
+        fetch_misses_icache = hart->cache_fetch[0].icache_misses +
+                              hart->cache_fetch[1].icache_misses;
+
+        /* Combine victim cache statistics */
+        uint64_t fetch_hits_vcache = 0, fetch_misses_vcache = 0;
+        fetch_hits_vcache =
+            hart->cache_fetch[0].vcache_hits + hart->cache_fetch[1].vcache_hits;
+        fetch_misses_vcache = hart->cache_fetch[0].vcache_misses +
+                              hart->cache_fetch[1].vcache_misses;
+
+        uint64_t access_total =
+            hart->cache_fetch[0].total_fetch + hart->cache_fetch[1].total_fetch;
 
         /* Combine 8-set × 2-way load cache statistics */
         uint64_t load_hits = 0, load_misses = 0;
@@ -1050,14 +1070,37 @@ static void print_mmu_cache_stats(vm_t *vm)
         }
         uint64_t store_total = store_hits + store_misses;
 
-        fprintf(stderr, "\nHart %u:\n", i);
-        fprintf(stderr, "  Fetch: %12llu hits, %12llu misses", fetch_hits,
-                fetch_misses);
-        if (fetch_total > 0)
-            fprintf(stderr, " (%.2f%% hit rate)",
-                    100.0 * fetch_hits / fetch_total);
-        fprintf(stderr, "\n");
 
+        fprintf(stderr, "\n=== Introduction Cache Statistics ===\n");
+        fprintf(stderr, "  Total access:  %12llu\n", access_total);
+        if (access_total > 0) {
+            fprintf(stderr, "  Icache hits:   %12llu (%.2f%%)\n",
+                    fetch_hits_icache,
+                    (fetch_hits_icache * 100.0) / access_total);
+
+            fprintf(stderr, "  Icache misses: %12llu (%.2f%%)\n",
+                    fetch_misses_icache,
+                    (fetch_misses_icache * 100.0) / access_total);
+        }
+        if (access_total > 0 && fetch_misses_icache > 0) {
+            fprintf(stderr,
+                    "   ├ Vcache hits:    %8llu (%.2f%% of Icache misses)\n",
+                    fetch_hits_vcache,
+                    (fetch_hits_vcache * 100.0) / fetch_misses_icache,
+                    (fetch_hits_vcache * 100.0) / access_total);
+            fprintf(stderr,
+                    "   └ Vcache misses:  %8llu (%.2f%% of Icache misses)\n",
+                    fetch_misses_vcache,
+                    (fetch_misses_vcache * 100.0) / fetch_misses_icache,
+                    (fetch_misses_vcache * 100.0) / access_total);
+        }
+        if (tlb_total > 0) {
+            fprintf(stderr, "      ├ TLB hits:     %4llu (%.2f%%)\n",
+                    fetch_hits_tlb, (fetch_hits_tlb * 100.0) / (tlb_total));
+            fprintf(stderr, "      └ TLB misses:   %4llu (%.2f%%)\n",
+                    fetch_misses_tlb, (fetch_misses_tlb * 100.0) / (tlb_total));
+        }
+        fprintf(stderr, "\n=== Data Cache Statistics ===\n");
         fprintf(stderr, "  Load:  %12llu hits, %12llu misses (8x2)", load_hits,
                 load_misses);
         if (load_total > 0)

riscv.c

@@ -371,29 +371,40 @@ static void mmu_fence(hart_t *vm, uint32_t insn UNUSED)
 
 static void mmu_fetch(hart_t *vm, uint32_t addr, uint32_t *value)
 {
-    /* cache hit */
     uint32_t idx = (addr >> ICACHE_OFFSET_BITS) & ICACHE_INDEX_MASK;
     uint32_t tag = addr >> (ICACHE_OFFSET_BITS + ICACHE_INDEX_BITS);
     icache_block_t *blk = &vm->icache.i_block[idx];
     uint32_t vpn = addr >> RV_PAGE_SHIFT;
     uint32_t index = __builtin_parity(vpn) & 0x1;
 
+#ifdef MMU_CACHE_STATS
+    vm->cache_fetch[index].total_fetch++;
+#endif
+
+    /* icache lookup */
     if (likely(blk->valid && blk->tag == tag)) {
 #ifdef MMU_CACHE_STATS
-        vm->cache_fetch[index].hits++;
+        vm->cache_fetch[index].icache_hits++;
 #endif
         uint32_t ofs = addr & ICACHE_BLOCK_MASK;
         *value = *(const uint32_t *) (blk->base + ofs);
         return;
     }
 
-    /* search the victim cache */
+    /* icache miss, try victim cache */
+#ifdef MMU_CACHE_STATS
+    vm->cache_fetch[index].icache_misses++;
+#endif
+
     uint32_t vcache_key = addr >> ICACHE_OFFSET_BITS;
     for (int i = 0; i < VCACHE_BLOCKS; i++) {
         victim_cache_block_t *vblk = &vm->icache.v_block[i];
 
-        /* victim cache hit, swap blocks */
         if (vblk->valid && vblk->tag == vcache_key) {
+            /* victim cache hit, swap blocks */
+#ifdef MMU_CACHE_STATS
+            vm->cache_fetch[index].vcache_hits++;
+#endif
             icache_block_t tmp = *blk;
             *blk = *vblk;
             *vblk = tmp;
@@ -407,11 +418,15 @@ static void mmu_fetch(hart_t *vm, uint32_t addr, uint32_t *value)
     }
 
 #ifdef MMU_CACHE_STATS
-    vm->cache_fetch[index].misses++;
+    vm->cache_fetch[index].vcache_misses++;
 #endif
 
-    /* cache miss, Continue using the original va->pa*/
+    /* TLB lookup */
     if (unlikely(vpn != vm->cache_fetch[index].n_pages)) {
+        /*TLB miss: need to translate VA to PA*/
+#ifdef MMU_CACHE_STATS
+        vm->cache_fetch[index].tlb_misses++;
+#endif
         mmu_translate(vm, &addr, (1 << 3), (1 << 6), false, RV_EXC_FETCH_FAULT,
                       RV_EXC_FETCH_PFAULT);
         if (vm->error)
@@ -423,6 +438,12 @@ static void mmu_fetch(hart_t *vm, uint32_t addr, uint32_t *value)
         vm->cache_fetch[index].n_pages = vpn;
         vm->cache_fetch[index].page_addr = page_addr;
     }
+    /*TLB hit*/
+    else {
+#ifdef MMU_CACHE_STATS
+        vm->cache_fetch[index].tlb_hits++;
+#endif
+    }
 
     *value =
         vm->cache_fetch[index].page_addr[(addr >> 2) & MASK(RV_PAGE_SHIFT - 2)];

riscv.h

@@ -36,8 +36,13 @@ typedef struct {
     uint32_t n_pages;
     uint32_t *page_addr;
 #ifdef MMU_CACHE_STATS
-    uint64_t hits;
-    uint64_t misses;
+    uint64_t total_fetch;
+    uint64_t tlb_hits;
+    uint64_t tlb_misses;
+    uint64_t icache_hits;
+    uint64_t icache_misses;
+    uint64_t vcache_hits;
+    uint64_t vcache_misses;
 #endif
 } mmu_fetch_cache_t;