Update 2.4_sequential_logic.ipynb - fixed typo (freechipsproject#176)

Author: JL102

2.4_sequential_logic.ipynb

@@ -112,7 +112,7 @@
     "Note:\n",
     "* The module has an input for clock (and reset) that you didn't add- this is the implicit clock\n",
     "* The variable `register` shows up as `reg [11:0]`, as expected\n",
-    "* There is a block sectioned off by ` `ifdef Randomize` that initialized the register to some random variable before simulation starts\n",
+    "* There is a block sectioned off by `ifdef Randomize` that initialized the register to some random variable before simulation starts\n",
     "* `register` is updated on `posedge clock`"
    ]
   },
@@ -589,4 +589,4 @@
  },
  "nbformat": 4,
  "nbformat_minor": 2
-}
+}