[wasm] Adjust IRGen tests not to assume every arch support returning two ptr directly

kateinoigakukun · kateinoigakukun · commit f53fad95af94 · 2025-11-18T14:40:11.000Z
diff --git a/test/IRGen/async/builtin_executor.sil b/test/IRGen/async/builtin_executor.sil
@@ -3,6 +3,7 @@
 // REQUIRES: concurrency
 // rdar://106849189 move-only types should be supported in freestanding mode
 // UNSUPPORTED: freestanding
+// UNSUPPORTED: CPU=wasm32
 
 sil_stage canonical
 
diff --git a/test/IRGen/async/partial_apply.sil b/test/IRGen/async/partial_apply.sil
@@ -606,7 +606,7 @@ entry(%0 : $EmptyType, %1: $*SomeType, %3: $FixedType):
   return %40 : $()
 }
 
-// CHECK-LABEL: define{{( dllexport)?}}{{( protected)?}} swift{{(tail)?}}cc { ptr, ptr } @create_pa_f2(
+// CHECK-LABEL: define{{( dllexport)?}}{{( protected)?}} swift{{(tail)?}}cc {{{ ptr, ptr }|void}} @create_pa_f2(
 sil @create_pa_f2 : $@convention(thin) (@callee_guaranteed @async @convention(thick) (Int64, Int32) -> Int64, Int32) -> @owned @async @callee_guaranteed (Int64) -> Int64 {
 bb0(%thick : $@callee_guaranteed @async @convention(thick) (Int64, Int32) -> Int64 , %captured : $Int32):
   %pa_f = partial_apply [callee_guaranteed] %thick(%captured) : $@callee_guaranteed @async @convention(thick) (Int64, Int32) -> Int64
diff --git a/test/IRGen/big_types_corner_cases.swift b/test/IRGen/big_types_corner_cases.swift
@@ -3,6 +3,7 @@
 // RUN: %target-swift-frontend -disable-type-layout %s -emit-ir | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize
 // REQUIRES: optimized_stdlib
 // UNSUPPORTED: CPU=powerpc64le
+// UNSUPPORTED: CPU=wasm32
 
 public struct BigStruct {
   var i0 : Int32 = 0
diff --git a/test/IRGen/boxed_existential.sil b/test/IRGen/boxed_existential.sil
@@ -1,4 +1,5 @@
 // RUN: %target-swift-frontend %s -emit-ir | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-runtime
+// UNSUPPORTED: CPU=wasm32
 
 import Swift
 
diff --git a/test/IRGen/builtin_vector_fixed_array.sil b/test/IRGen/builtin_vector_fixed_array.sil
@@ -1,6 +1,7 @@
 // RUN: %target-swift-frontend -emit-irgen -disable-availability-checking -enable-experimental-feature BuiltinModule %s | %FileCheck %s
 
 // REQUIRES: swift_feature_BuiltinModule
+// UNSUPPORTED: CPU=wasm32
 
 import Builtin
 import Swift
diff --git a/test/IRGen/enum_dynamic_multi_payload.sil b/test/IRGen/enum_dynamic_multi_payload.sil
@@ -1,4 +1,5 @@
 // RUN: %target-swift-frontend -disable-type-layout %s -gnone -emit-ir -I %S/Inputs | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize -DINT=i%target-ptrsize --check-prefix=CHECK-%target-cpu
+// UNSUPPORTED: CPU=wasm32
 
 import Builtin
 
diff --git a/test/IRGen/enum_resilience.swift b/test/IRGen/enum_resilience.swift
@@ -8,6 +8,7 @@
 // RUN: %target-swift-frontend -emit-module -enable-library-evolution -emit-module-path=%t/resilient_enum.swiftmodule -module-name=resilient_enum -I %t %S/../Inputs/resilient_enum.swift
 // RUN: %target-swift-frontend -disable-type-layout -module-name enum_resilience -I %t -emit-ir -enable-library-evolution %s | %FileCheck %t/enum_resilience.swift -DINT=i%target-ptrsize --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-cpu
 // RUN: %target-swift-frontend -module-name enum_resilience -I %t -emit-ir -enable-library-evolution -O %s
+// UNSUPPORTED: CPU=wasm32
 
 import resilient_enum
 import resilient_struct
diff --git a/test/IRGen/errors.sil b/test/IRGen/errors.sil
@@ -1,6 +1,7 @@
 // XFAIL: CPU=powerpc64le
 // XFAIL: CPU=s390x
 // RUN: %target-swift-frontend -primary-file %s -emit-ir | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-runtime --check-prefix=CHECK-%target-cpu --check-prefix=CHECK-%target-ptrsize
+// UNSUPPORTED: CPU=wasm32
 
 sil_stage canonical
 
diff --git a/test/IRGen/isolated_any.sil b/test/IRGen/isolated_any.sil
@@ -1,6 +1,7 @@
 // RUN: %target-swift-frontend -emit-ir %s | %IRGenFileCheck %s
 
 // REQUIRES: concurrency
+// UNSUPPORTED: CPU=wasm32
 
 import Swift
 import _Concurrency
diff --git a/test/IRGen/meta_meta_type.swift b/test/IRGen/meta_meta_type.swift
@@ -4,6 +4,7 @@
 // RUN: %target-run %t/a.out | %FileCheck %s
 // RUN: %target-swift-frontend -primary-file %s -emit-ir | %FileCheck -check-prefix=CHECKIR %s
 // REQUIRES: executable_test
+// UNSUPPORTED: CPU=wasm32
 
 protocol Proto {
 }
diff --git a/test/IRGen/objc_simd.sil b/test/IRGen/objc_simd.sil
@@ -68,7 +68,7 @@ entry(%x : $float3):
 // powerpc64-LABEL: define{{( dllexport)?}}{{( protected)?}} void @simd_native_args(ptr noalias sret({{.*}}) captures(none) %0, ptr noalias captures(none) dereferenceable({{.*}}) %1)
 // powerpc64le-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float, float } @simd_native_args(float %0, float %1, float %2, float %3)
 // s390x-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float, float } @simd_native_args(float %0, float %1, float %2, float %3)
-// wasm32-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float, float } @simd_native_args(float %0, float %1, float %2, float %3)
+// wasm32-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc void @simd_native_args(ptr noalias sret(%T4simd6float4V) captures(none) %0, float %1, float %2, float %3, float %4)
 sil @simd_native_args : $@convention(thin) (float4) -> float4 {
 entry(%x : $float4):
   %f = function_ref @simd_c_args : $@convention(c) (float4) -> float4
@@ -87,7 +87,7 @@ entry(%x : $float4):
 // powerpc64-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float } @simd_native_args_float3(float %0, float %1, float %2)
 // powerpc64le-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float } @simd_native_args_float3(float %0, float %1, float %2)
 // s390x-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float } @simd_native_args_float3(float %0, float %1, float %2)
-// wasm32-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float } @simd_native_args_float3(float %0, float %1, float %2)
+// wasm32-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc void @simd_native_args_float3(ptr noalias sret(%T4simd6float3V) captures(none) %0, float %1, float %2, float %3)
 sil @simd_native_args_float3 : $@convention(thin) (float3) -> float3 {
 entry(%x : $float3):
   %f = function_ref @simd_c_args_float3 : $@convention(c) (float3) -> float3
diff --git a/test/IRGen/package-cmo-serialize-witness-thunk.swift b/test/IRGen/package-cmo-serialize-witness-thunk.swift
@@ -21,7 +21,6 @@
 // RUN: %FileCheck %s --check-prefix=CHECK-IR < %t/Lib-ir.ll
 // RUN: %FileCheck %s --check-prefix=CHECK-TBD < %t/Lib-tbd.tbd
 
-
 /// TEST that a public (or package) protocol witness thunk gets a shared linkage if Package CMO is enabled.
 /// It also gets [serialized] in emit-silgen.
 ///
@@ -33,8 +32,8 @@
 // CHECK-NO-PCMO-SIL-DAG: sil private [transparent] [thunk] @$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW : $@convention(witness_method: Proto) (@in_guaranteed Pub) -> @owned String {
 // CHECK-SIL-DAG:         sil shared [transparent] [thunk] @$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW : $@convention(witness_method: Proto) (@in_guaranteed Pub) -> @owned String {
 
-// CHECK-NO-PCMO-IR-DAG: define internal swiftcc { {{i64, ptr|i32, i32, i32}} } @"$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW"
-// CHECK-IR-DAG:         define linkonce_odr hidden swiftcc { {{i64, ptr|i32, i32, i32}} } @"$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW"
+// CHECK-NO-PCMO-IR-DAG: define internal swiftcc {{{ i64, ptr }|{ i32, i32, i32 }|void}} @"$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW"
+// CHECK-IR-DAG:         define linkonce_odr hidden swiftcc {{{ i64, ptr }|{ i32, i32, i32 }|void}} @"$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW"
 
 // protocol witness for Proto.bar(_:) in conformance Pub
 
diff --git a/test/IRGen/package_bypass_resilience_class.swift b/test/IRGen/package_bypass_resilience_class.swift
@@ -130,7 +130,7 @@ class UFIKlass {
   var varNonUfi: String?
 
   // variable initialization expression of Core.UFIKlass.varUfi
-  // CHECK-OPT-DAG: define {{(dllexport |protected )?}}swiftcc {{.*}} @"$s4Core8UFIKlassC6varUfiSSSgvpfi"()
+  // CHECK-OPT-DAG: define {{(dllexport |protected )?}}swiftcc {{.*}} @"$s4Core8UFIKlassC6varUfiSSSgvpfi"
 
   // key path getter for Core.UFIKlass.varUfi
   // CHECK-COMMON-DAG: define linkonce_odr hidden swiftcc void @"$s4Core8UFIKlassC6varUfiSSSgvpACTK"
diff --git a/test/IRGen/partial_apply_coro.sil b/test/IRGen/partial_apply_coro.sil
@@ -3,6 +3,7 @@
 // RUN: %target-swift-frontend -Xllvm -sil-disable-pass=OnoneSimplification -I %t -emit-ir -disable-emit-type-malloc-for-coro-frame %s -o - | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-cpu
 
 // REQUIRES: concurrency
+// UNSUPPORTED: CPU=wasm32
 
 import Builtin
 import Swift
diff --git a/test/IRGen/simple_partial_apply.sil b/test/IRGen/simple_partial_apply.sil
@@ -1,4 +1,5 @@
 // RUN: %target-swift-frontend -emit-ir %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-cpu
+// UNSUPPORTED: CPU=wasm32
 
 sil_stage canonical
 
diff --git a/test/IRGen/struct_resilience.swift b/test/IRGen/struct_resilience.swift
@@ -3,6 +3,7 @@
 // RUN: %target-swift-frontend -emit-module -enable-library-evolution -emit-module-path=%t/resilient_enum.swiftmodule -module-name=resilient_enum -I %t %S/../Inputs/resilient_enum.swift
 // RUN: %target-swift-frontend -module-name struct_resilience -Xllvm -sil-disable-pass=MandatoryARCOpts -I %t -emit-ir -enable-library-evolution %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-cpu
 // RUN: %target-swift-frontend -module-name struct_resilience -I %t -emit-ir -enable-library-evolution -O %s
+// UNSUPPORTED: CPU=wasm32
 
 import resilient_struct
 import resilient_enum
diff --git a/test/IRGen/subclass_existentials.sil b/test/IRGen/subclass_existentials.sil
@@ -1,4 +1,5 @@
 // RUN: %target-swift-frontend -primary-file %s -emit-ir | %FileCheck %s --check-prefix=CHECK-%target-runtime --check-prefix=CHECK -DINT=i%target-ptrsize
+// UNSUPPORTED: CPU=wasm32
 
 sil_stage canonical
 
diff --git a/test/IRGen/variadic_generic_captures.swift b/test/IRGen/variadic_generic_captures.swift
@@ -1,4 +1,5 @@
 // RUN: %target-swift-frontend -emit-ir %s | %FileCheck %s -DINT=i%target-ptrsize
+// UNSUPPORTED: CPU=wasm32
 
 public func takesNoEscape(_: () -> ()) {}
 
diff --git a/test/IRGen/yield_once_biggish.sil b/test/IRGen/yield_once_biggish.sil
@@ -6,6 +6,7 @@
 // we should turn this into a REQUIRES instead.
 // UNSUPPORTED: CPU=i386
 // UNSUPPORTED: CPU=arm64_32
+// UNSUPPORTED: CPU=wasm32
 
 import Builtin
 import Swift
diff --git a/test/IRGen/yield_result.sil b/test/IRGen/yield_result.sil
@@ -1,4 +1,5 @@
 // RUN: %target-swift-frontend -emit-irgen -disable-emit-type-malloc-for-coro-frame %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECK-%target-ptrsize -DINT=i%target-ptrsize
+// UNSUPPORTED: CPU=wasm32
 
 import Builtin
 
diff --git a/test/stdlib/SIMDFloatInitializers.swift.gyb b/test/stdlib/SIMDFloatInitializers.swift.gyb
@@ -37,9 +37,9 @@ func repeating${n}x${bits}(_ scalar: ${scalar}) -> SIMD${n}<${scalar}> {
 %   if bits == 16:
 #endif
 %   end
-// CHECK${arch}: repeating${n}x${bits}{{.*}} {
+// CHECK${arch}: define {{.*}} @"{{.*}}repeating${n}x${bits}{{.*}}"({{(ptr noalias sret\(.+\) captures\(none\) %0, )?}}{{(.+)}} [[ARG:%[0-9]+]])
 // CHECK${arch}: entry:
-// CHECK${arch}: [[TMP:%[0-9]+]] = insertelement <${n} x ${llvm}> {{.*}} ${llvm} %0, i32 0
+// CHECK${arch}: [[TMP:%[0-9]+]] = insertelement <${n} x ${llvm}> {{.*}} ${llvm} [[ARG]], i32 0
 // CHECK${arch}-NEXT: [[REP:%[0-9]+]] = shufflevector <${n} x ${llvm}> [[TMP]], <${n} x ${llvm}> {{.*}}, <${n} x i32> zeroinitializer
 
 %  end
diff --git a/test/stdlib/SIMDSignedInitializers.swift.gyb b/test/stdlib/SIMDSignedInitializers.swift.gyb
@@ -23,9 +23,9 @@ import Swift
 func repeating${n}_int${bits}(_ scalar: Int${bits}) -> SIMD${n}<Int${bits}> {
   SIMD${n}(repeating: scalar)
 }
-// CHECK: repeating${n}_int${bits}{{.*}} {
+// CHECK: define {{.*}} @"{{.*}}repeating${n}_int${bits}{{.*}}"({{(ptr noalias sret\(.+\) captures\(none\) %0, )?}}{{(.+)}} [[ARG:%[0-9]+]])
 // CHECK: entry:
-// CHECK: [[TMP:%[0-9]+]] = insertelement <${n} x i${bits}> {{.*}}, i${bits} %0, i32 0
+// CHECK: [[TMP:%[0-9]+]] = insertelement <${n} x i${bits}> {{.*}}, i${bits} [[ARG]], i32 0
 // CHECK-NEXT: [[REP:%[0-9]+]] = shufflevector <${n} x i${bits}> [[TMP]], <${n} x i${bits}> {{.*}}, <${n} x i32> zeroinitializer
 
 %  end

Original file line number	Diff line number	Diff line change
`@@ -606,7 +606,7 @@ entry(%0 : $EmptyType, %1: $*SomeType, %3: $FixedType):`
`606`	`606`	`return %40 : $()`
`607`	`607`	`}`
`608`	`608`
`609`		`-// CHECK-LABEL: define{{( dllexport)?}}{{( protected)?}} swift{{(tail)?}}cc { ptr, ptr } @create_pa_f2(`
	`609`	`+// CHECK-LABEL: define{{( dllexport)?}}{{( protected)?}} swift{{(tail)?}}cc {{{ ptr, ptr }\|void}} @create_pa_f2(`
`610`	`610`	`sil @create_pa_f2 : $@convention(thin) (@callee_guaranteed @async @convention(thick) (Int64, Int32) -> Int64, Int32) -> @owned @async @callee_guaranteed (Int64) -> Int64 {`
`611`	`611`	`bb0(%thick : $@callee_guaranteed @async @convention(thick) (Int64, Int32) -> Int64 , %captured : $Int32):`
`612`	`612`	`%pa_f = partial_apply [callee_guaranteed] %thick(%captured) : $@callee_guaranteed @async @convention(thick) (Int64, Int32) -> Int64`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,5 @@`
`1`	`1`	`// RUN: %target-swift-frontend %s -emit-ir \| %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-runtime`
	`2`	`+// UNSUPPORTED: CPU=wasm32`
`2`	`3`
`3`	`4`	`import Swift`
`4`	`5`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,5 @@`
`1`	`1`	`// RUN: %target-swift-frontend -disable-type-layout %s -gnone -emit-ir -I %S/Inputs \| %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize -DINT=i%target-ptrsize --check-prefix=CHECK-%target-cpu`
	`2`	`+// UNSUPPORTED: CPU=wasm32`
`2`	`3`
`3`	`4`	`import Builtin`
`4`	`5`
Original file line number	Diff line number	Diff line change
`@@ -4,6 +4,7 @@`
`4`	`4`	`// RUN: %target-run %t/a.out \| %FileCheck %s`
`5`	`5`	`// RUN: %target-swift-frontend -primary-file %s -emit-ir \| %FileCheck -check-prefix=CHECKIR %s`
`6`	`6`	`// REQUIRES: executable_test`
	`7`	`+// UNSUPPORTED: CPU=wasm32`
`7`	`8`
`8`	`9`	`protocol Proto {`
`9`	`10`	`}`