Skip to content

Commit 571c285

Browse files
fpistmfpistm
committed
[G4] Add STM32G4xx system source file
CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. This provides system initialization template function is case of an application using a STM32G4 device Signed-off-by: Frederic.Pillon <frederic.pillon@st.com>
1 parent f1f3a31 commit 571c285

File tree

2 files changed

+276
-0
lines changed

2 files changed

+276
-0
lines changed

‎cores/arduino/stm32/system_stm32yyxx.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,9 @@
1919
#ifdef STM32G0xx
2020
#include "system_stm32g0xx.c"
2121
#endif
22+
#ifdef STM32G4xx
23+
#include "system_stm32g4xx.c"
24+
#endif
2225
#ifdef STM32H7xx
2326
#include "system_stm32h7xx.c"
2427
#endif

‎system/STM32G4xx/system_stm32g4xx.c‎

Lines changed: 273 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,273 @@
1+
/**
2+
******************************************************************************
3+
* @file system_stm32g4xx.c
4+
* @author MCD Application Team
5+
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
6+
*
7+
* This file provides two functions and one global variable to be called from
8+
* user application:
9+
* - SystemInit(): This function is called at startup just after reset and
10+
* before branch to main program. This call is made inside
11+
* the "startup_stm32g4xx.s" file.
12+
*
13+
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14+
* by the user application to setup the SysTick
15+
* timer or configure other parameters.
16+
*
17+
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18+
* be called whenever the core clock is changed
19+
* during program execution.
20+
*
21+
* After each device reset the HSI (16 MHz) is used as system clock source.
22+
* Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
23+
* configure the system clock before to branch to main program.
24+
*
25+
* This file configures the system clock as follows:
26+
*=============================================================================
27+
*-----------------------------------------------------------------------------
28+
* System Clock source | HSI
29+
*-----------------------------------------------------------------------------
30+
* SYSCLK(Hz) | 16000000
31+
*-----------------------------------------------------------------------------
32+
* HCLK(Hz) | 16000000
33+
*-----------------------------------------------------------------------------
34+
* AHB Prescaler | 1
35+
*-----------------------------------------------------------------------------
36+
* APB1 Prescaler | 1
37+
*-----------------------------------------------------------------------------
38+
* APB2 Prescaler | 1
39+
*-----------------------------------------------------------------------------
40+
* PLL_M | 1
41+
*-----------------------------------------------------------------------------
42+
* PLL_N | 16
43+
*-----------------------------------------------------------------------------
44+
* PLL_P | 7
45+
*-----------------------------------------------------------------------------
46+
* PLL_Q | 2
47+
*-----------------------------------------------------------------------------
48+
* PLL_R | 2
49+
*-----------------------------------------------------------------------------
50+
* Require 48MHz for RNG | Disabled
51+
*-----------------------------------------------------------------------------
52+
*=============================================================================
53+
******************************************************************************
54+
* @attention
55+
*
56+
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
57+
* All rights reserved.</center></h2>
58+
*
59+
* This software component is licensed by ST under BSD 3-Clause license,
60+
* the "License"; You may not use this file except in compliance with the
61+
* License. You may obtain a copy of the License at:
62+
* opensource.org/licenses/BSD-3-Clause
63+
*
64+
******************************************************************************
65+
*/
66+
67+
/** @addtogroup CMSIS
68+
* @{
69+
*/
70+
71+
/** @addtogroup stm32g4xx_system
72+
* @{
73+
*/
74+
75+
/** @addtogroup STM32G4xx_System_Private_Includes
76+
* @{
77+
*/
78+
79+
#include "stm32g4xx.h"
80+
81+
#if !defined (HSE_VALUE)
82+
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
83+
#endif /* HSE_VALUE */
84+
85+
#if !defined (HSI_VALUE)
86+
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
87+
#endif /* HSI_VALUE */
88+
89+
/**
90+
* @}
91+
*/
92+
93+
/** @addtogroup STM32G4xx_System_Private_TypesDefinitions
94+
* @{
95+
*/
96+
97+
/**
98+
* @}
99+
*/
100+
101+
/** @addtogroup STM32G4xx_System_Private_Defines
102+
* @{
103+
*/
104+
105+
/************************* Miscellaneous Configuration ************************/
106+
/*!< Uncomment the following line if you need to relocate your vector Table in
107+
Internal SRAM. */
108+
/* #define VECT_TAB_SRAM */
109+
#ifndef VECT_TAB_OFFSET
110+
#define VECT_TAB_OFFSET 0x00UL /*!< Vector Table base offset field.
111+
This value must be a multiple of 0x200. */
112+
#endif
113+
/******************************************************************************/
114+
/**
115+
* @}
116+
*/
117+
118+
/** @addtogroup STM32G4xx_System_Private_Macros
119+
* @{
120+
*/
121+
122+
/**
123+
* @}
124+
*/
125+
126+
/** @addtogroup STM32G4xx_System_Private_Variables
127+
* @{
128+
*/
129+
/* The SystemCoreClock variable is updated in three ways:
130+
1) by calling CMSIS function SystemCoreClockUpdate()
131+
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
132+
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
133+
Note: If you use this function to configure the system clock; then there
134+
is no need to call the 2 first functions listed above, since SystemCoreClock
135+
variable is updated automatically.
136+
*/
137+
uint32_t SystemCoreClock = HSI_VALUE;
138+
139+
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
140+
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
141+
142+
/**
143+
* @}
144+
*/
145+
146+
/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
147+
* @{
148+
*/
149+
150+
/**
151+
* @}
152+
*/
153+
154+
/** @addtogroup STM32G4xx_System_Private_Functions
155+
* @{
156+
*/
157+
158+
/**
159+
* @brief Setup the microcontroller system.
160+
* @param None
161+
* @retval None
162+
*/
163+
164+
void SystemInit(void)
165+
{
166+
/* FPU settings ------------------------------------------------------------*/
167+
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
168+
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
169+
#endif
170+
171+
/* Configure the Vector Table location add offset address ------------------*/
172+
#ifdef VECT_TAB_SRAM
173+
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
174+
#else
175+
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
176+
#endif
177+
}
178+
179+
/**
180+
* @brief Update SystemCoreClock variable according to Clock Register Values.
181+
* The SystemCoreClock variable contains the core clock (HCLK), it can
182+
* be used by the user application to setup the SysTick timer or configure
183+
* other parameters.
184+
*
185+
* @note Each time the core clock (HCLK) changes, this function must be called
186+
* to update SystemCoreClock variable value. Otherwise, any configuration
187+
* based on this variable will be incorrect.
188+
*
189+
* @note - The system frequency computed by this function is not the real
190+
* frequency in the chip. It is calculated based on the predefined
191+
* constant and the selected clock source:
192+
*
193+
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
194+
*
195+
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
196+
*
197+
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
198+
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
199+
*
200+
* (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
201+
* 16 MHz) but the real value may vary depending on the variations
202+
* in voltage and temperature.
203+
*
204+
* (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
205+
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
206+
* frequency of the crystal used. Otherwise, this function may
207+
* have wrong result.
208+
*
209+
* - The result of this function could be not correct when using fractional
210+
* value for HSE crystal.
211+
*
212+
* @param None
213+
* @retval None
214+
*/
215+
void SystemCoreClockUpdate(void)
216+
{
217+
uint32_t tmp, pllvco, pllr, pllsource, pllm;
218+
219+
/* Get SYSCLK source -------------------------------------------------------*/
220+
switch (RCC->CFGR & RCC_CFGR_SWS)
221+
{
222+
case 0x04: /* HSI used as system clock source */
223+
SystemCoreClock = HSI_VALUE;
224+
break;
225+
226+
case 0x08: /* HSE used as system clock source */
227+
SystemCoreClock = HSE_VALUE;
228+
break;
229+
230+
case 0x0C: /* PLL used as system clock source */
231+
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
232+
SYSCLK = PLL_VCO / PLLR
233+
*/
234+
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
235+
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
236+
if (pllsource == 0x02UL) /* HSI used as PLL clock source */
237+
{
238+
pllvco = (HSI_VALUE / pllm);
239+
}
240+
else /* HSE used as PLL clock source */
241+
{
242+
pllvco = (HSE_VALUE / pllm);
243+
}
244+
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
245+
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
246+
SystemCoreClock = pllvco/pllr;
247+
break;
248+
249+
default:
250+
break;
251+
}
252+
/* Compute HCLK clock frequency --------------------------------------------*/
253+
/* Get HCLK prescaler */
254+
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
255+
/* HCLK clock frequency */
256+
SystemCoreClock >>= tmp;
257+
}
258+
259+
260+
/**
261+
* @}
262+
*/
263+
264+
/**
265+
* @}
266+
*/
267+
268+
/**
269+
* @}
270+
*/
271+
272+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
273+

0 commit comments

Comments
 (0)