Added clocks for timers - timclk1 timclk2 (#301)

Added clocks for timers - timclk1 timclk2

Author: janodw

src/rcc.rs

@@ -687,6 +687,16 @@ impl CFGR {
 
         let pclk2: u32 = hclk / u32(ppre2);
 
+        // RM0394 Rev 4, page 188
+        // 6.2.14 Timer clock
+        //
+        // The timer clock frequencies are automatically defined by hardware. There are two cases:
+        // 1. If the APB prescaler equals 1, the timer clock frequencies are set to the same
+        // frequency as that of the APB domain.
+        // 2. Otherwise, they are set to twice (×2) the frequency of the APB domain.
+        let timclk1 = if ppre1 == 1 { pclk1 } else { 2 * pclk1 };
+        let timclk2 = if ppre2 == 1 { pclk2 } else { 2 * pclk2 };
+
         assert!(pclk2 <= sysclk);
 
         // adjust flash wait states
@@ -806,6 +816,8 @@ impl CFGR {
             ppre1,
             ppre2,
             sysclk: sysclk.Hz(),
+            timclk1: timclk1.Hz(),
+            timclk2: timclk2.Hz(),
             pll_source: pllconf.map(|_| pll_source),
         }
     }
@@ -903,6 +915,8 @@ pub struct Clocks {
     ppre1: u8,
     ppre2: u8,
     sysclk: Hertz,
+    timclk1: Hertz,
+    timclk2: Hertz,
     pll_source: Option<PllSource>,
 }
 
@@ -962,4 +976,14 @@ impl Clocks {
     pub fn sysclk(&self) -> Hertz {
         self.sysclk
     }
+
+    /// Returns the frequency for timers on APB1
+    pub fn timclk1(&self) -> Hertz {
+        self.timclk1
+    }
+
+    /// Returns the frequency for timers on APB2
+    pub fn timclk2(&self) -> Hertz {
+        self.timclk2
+    }
 }

src/timer.rs

@@ -69,7 +69,7 @@ use fugit::RateExtU32;
 
 /// Hardware timers
 pub struct Timer<TIM> {
-    clocks: Clocks,
+    clock: Hertz,
     tim: TIM,
     timeout: Hertz,
 }
@@ -81,7 +81,7 @@ pub enum Event {
 }
 
 macro_rules! hal {
-    ($($TIM:ident: ($tim:ident, $frname:ident, $apb:ident, $width:ident),)+) => {
+    ($($TIM:ident: ($tim:ident, $frname:ident, $apb:ident, $width:ident, $timclk:ident),)+) => {
         $(
             impl Periodic for Timer<$TIM> {}
 
@@ -98,7 +98,7 @@ macro_rules! hal {
                     self.pause();
 
                     self.timeout = timeout.into();
-                    let ticks = self.clocks.pclk1() / self.timeout; // TODO: Check pclk that timer is on.
+                    let ticks = self.clock / self.timeout; // TODO check pclk that timer is on
                     let psc = u16((ticks - 1) / (1 << 16)).unwrap();
 
                     self.tim.psc.write(|w| unsafe { w.psc().bits(psc) });
@@ -150,8 +150,10 @@ macro_rules! hal {
                     <$TIM>::enable(apb);
                     <$TIM>::reset(apb);
 
+                    let clock = clocks.$timclk();
+
                     let mut timer = Timer {
-                        clocks,
+                        clock,
                         tim,
                         timeout: 0.Hz(),
                     };
@@ -173,9 +175,11 @@ macro_rules! hal {
                     <$TIM>::enable(apb);
                     <$TIM>::reset(apb);
 
-                    let psc = clocks.pclk1() / frequency - 1;
+                    let clock = clocks.$timclk();
+
+                    let psc = clock / frequency - 1;
 
-                    debug_assert!(clocks.pclk1() >= frequency);
+                    debug_assert!(clock >= frequency);
                     debug_assert!(frequency.raw() > 0);
                     debug_assert!(psc <= core::u16::MAX.into());
 
@@ -206,7 +210,7 @@ macro_rules! hal {
                     });
 
                     Timer {
-                        clocks,
+                        clock,
                         tim,
                         timeout: frequency,
                     }
@@ -277,11 +281,11 @@ macro_rules! hal {
 }
 
 hal! {
-    TIM2:  (tim2, free_running_tim2, APB1R1, u32),
-    TIM6:  (tim6, free_running_tim6, APB1R1, u16),
-    //TIM7:  (tim7, free_running_tim7, APB1R1, u16),
-    TIM15: (tim15, free_running_tim15, APB2, u16),
-    TIM16: (tim16, free_running_tim16, APB2, u16),
+    TIM2:  (tim2, free_running_tim2, APB1R1, u32, timclk1),
+    TIM6:  (tim6, free_running_tim6, APB1R1, u16, timclk1),
+    //TIM7:  (tim7, free_running_tim7, APB1R1, u16, timclk1),
+    TIM15: (tim15, free_running_tim15, APB2, u16, timclk2),
+    TIM16: (tim16, free_running_tim16, APB2, u16, timclk2),
 }
 
 #[cfg(any(
@@ -305,7 +309,7 @@ hal! {
     // feature = "stm32l4s9",
 ))]
 hal! {
-    TIM3:  (tim3, free_running_tim3, APB1R1, u16),
+    TIM3:  (tim3, free_running_tim3, APB1R1, u16, timclk1),
 }
 
 #[cfg(not(any(
@@ -316,7 +320,7 @@ hal! {
     feature = "stm32l462",
 )))]
 hal! {
-    TIM7:  (tim7, free_running_tim7, APB1R1, u16),
+    TIM7:  (tim7, free_running_tim7, APB1R1, u16, timclk1),
 }
 
 #[cfg(any(
@@ -336,7 +340,7 @@ hal! {
     // feature = "stm32l4s9",
 ))]
 hal! {
-    TIM4:  (tim4, free_running_tim4, APB1R1, u16),
-    TIM5:  (tim5, free_running_tim5, APB1R1, u32),
-    TIM17: (tim17, free_running_tim17, APB2, u16),
+    TIM4:  (tim4, free_running_tim4, APB1R1, u16, timclk1),
+    TIM5:  (tim5, free_running_tim5, APB1R1, u32, timclk1),
+    TIM17: (tim17, free_running_tim17, APB2, u16, timclk2),
 }