i2c: Implement embedded_hal::i2c::I2c for I2CMasterDMA

Rationale - Blocking access is already exposed via the
I2CMasterDma::read + I2CMasterDma::write functions but the
embedded_hal::i2c::I2c trait is not implemented meaning it does not
integrate well with generic crates.

Author: shonrb

CHANGELOG.md

@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+ - Implement `embedded_hal::i2c::I2c` for `I2cMasterDma` [#838]
  - Back to `stm32f4`
  - Implement `Ptr`, `Sealed`, `Steal` for generic `Periph` [#834]
  - Unmacro `Adc` [#832]
@@ -23,6 +24,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 [#832]: https://github.com/stm32-rs/stm32f4xx-hal/pull/832
 [#833]: https://github.com/stm32-rs/stm32f4xx-hal/pull/833
 [#834]: https://github.com/stm32-rs/stm32f4xx-hal/pull/834
+[#838]: https://github.com/stm32-rs/stm32f4xx-hal/pull/838
 
 ## [v0.22.1] - 2024-11-03
 

src/i2c/dma.rs

@@ -6,6 +6,8 @@ use crate::dma::{
     traits::{Channel, DMASet, DmaFlagExt, PeriAddress, Stream, StreamISR},
     ChannelX, MemoryToPeripheral, PeripheralToMemory, Transfer,
 };
+use crate::hal::i2c;
+use crate::i2c::dma::i2c::{ErrorType, Operation};
 use crate::ReadFlags;
 
 use nb;
@@ -601,6 +603,36 @@ where
     }
 }
 
+impl<I2C, TX_TRANSFER, RX_TRANSFER> ErrorType for I2CMasterDma<I2C, TX_TRANSFER, RX_TRANSFER>
+where
+    I2C: Instance,
+    TX_TRANSFER: DMATransfer<&'static [u8]>,
+    RX_TRANSFER: DMATransfer<&'static mut [u8]>,
+{
+    type Error = super::Error;
+}
+
+impl<I2C, TX_TRANSFER, RX_TRANSFER> i2c::I2c for I2CMasterDma<I2C, TX_TRANSFER, RX_TRANSFER>
+where
+    I2C: Instance,
+    TX_TRANSFER: DMATransfer<&'static [u8]>,
+    RX_TRANSFER: DMATransfer<&'static mut [u8]>,
+{
+    fn transaction(
+        &mut self,
+        addr: u8,
+        operations: &mut [Operation<'_>],
+    ) -> Result<(), Self::Error> {
+        for operation in operations {
+            match operation {
+                Operation::Read(dest) => self.hal_i2c.read(addr, dest),
+                Operation::Write(data) => self.hal_i2c.write(addr, data),
+            }?;
+        }
+        Ok(())
+    }
+}
+
 impl<I2C, TX_STREAM, const TX_CH: u8> I2CMasterHandleIT
     for I2CMasterDma<I2C, TxDMA<I2C, TX_STREAM, TX_CH>, NoDMA>
 where