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Merge pull request #503 from stm32-rs/staging
stm32f1-staging
2 parents b66d849 + e3e62f3 commit 6b1690f

23 files changed

+493
-465
lines changed

‎CHANGELOG.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1414
Remove `RemapStruct`s. [#462]
1515
- Use independent `Spi` and `SpiSlave` structures instead of `OP` generic [#462]
1616
- Take `&Clocks` instead of `Clocks` [#498]
17+
- Temporary replace `stm32f1` with `stm32f1-staging`
1718

1819
### Changed
1920

‎Cargo.toml‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@ default-target = "x86_64-unknown-linux-gnu"
2121
cortex-m = "0.7.6"
2222
cortex-m-rt = "0.7.1"
2323
nb = "1.1"
24-
stm32f1 = "0.15.1"
2524
embedded-dma = "0.2.0"
2625
bxcan = "0.7"
2726
void = { default-features = false, version = "1.0.2" }
@@ -31,6 +30,11 @@ rtic-monotonic = { version = "1.0", optional = true }
3130
bitflags = "1.3.2"
3231
vcell = "0.1.3"
3332

33+
[dependencies.stm32f1]
34+
package = "stm32f1-staging"
35+
version = "0.16.0"
36+
features = ["atomics"]
37+
3438
[dependencies.embedded-hal-02]
3539
package = "embedded-hal"
3640
version = "0.2.7"
@@ -68,6 +72,8 @@ stm32f103 = ["stm32f1/stm32f103", "has-can", "stm32-usbd"]
6872
stm32f105 = ["stm32f1/stm32f107", "connectivity"]
6973
stm32f107 = ["stm32f1/stm32f107", "connectivity"]
7074

75+
defmt = ["stm32f1/defmt"]
76+
7177
# Devices with 64 or 128 Kb ROM
7278
medium = []
7379
# Devices with 256 or 512 Kb ROM

‎examples/blinky_rtcalarm_irq.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ fn RTCALARM() {
6666
cortex_m::interrupt::free(|cs| G_EXTI.borrow(cs).replace(None).unwrap())
6767
});
6868

69-
exti.pr.write(|w| w.pr17().set_bit());
69+
exti.pr().write(|w| w.pr17().clear_bit_by_one());
7070
rtc.set_alarm(rtc.current_time() + TOGGLE_INTERVAL_SECONDS);
7171

7272
let _ = led.toggle();
@@ -89,8 +89,8 @@ fn main() -> ! {
8989

9090
// Set up the EXTI (see notes in section 18.4.2 of reference manual)
9191
let exti = dp.EXTI;
92-
exti.ftsr.write(|w| w.tr17().set_bit());
93-
exti.imr.write(|w| w.mr17().set_bit());
92+
exti.ftsr().write(|w| w.tr17().set_bit());
93+
exti.imr().write(|w| w.mr17().set_bit());
9494

9595
cortex_m::interrupt::free(|cs| *G_EXTI.borrow(cs).borrow_mut() = Some(exti));
9696

‎src/adc.rs‎

Lines changed: 79 additions & 69 deletions
Large diffs are not rendered by default.

‎src/afio.rs‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ pub struct EVCR {
5757

5858
impl EVCR {
5959
pub fn evcr(&mut self) -> &afio::EVCR {
60-
unsafe { &(*AFIO::ptr()).evcr }
60+
unsafe { (*AFIO::ptr()).evcr() }
6161
}
6262
}
6363

@@ -78,7 +78,7 @@ pub struct MAPR {
7878

7979
impl MAPR {
8080
fn mapr(&mut self) -> &afio::MAPR {
81-
unsafe { &(*AFIO::ptr()).mapr }
81+
unsafe { (*AFIO::ptr()).mapr() }
8282
}
8383

8484
pub fn modify_mapr<F>(&mut self, mod_fn: F)
@@ -117,7 +117,7 @@ pub struct EXTICR1 {
117117

118118
impl EXTICR1 {
119119
pub fn exticr1(&mut self) -> &afio::EXTICR1 {
120-
unsafe { &(*AFIO::ptr()).exticr1 }
120+
unsafe { (*AFIO::ptr()).exticr1() }
121121
}
122122
}
123123

@@ -127,7 +127,7 @@ pub struct EXTICR2 {
127127

128128
impl EXTICR2 {
129129
pub fn exticr2(&mut self) -> &afio::EXTICR2 {
130-
unsafe { &(*AFIO::ptr()).exticr2 }
130+
unsafe { (*AFIO::ptr()).exticr2() }
131131
}
132132
}
133133

@@ -137,7 +137,7 @@ pub struct EXTICR3 {
137137

138138
impl EXTICR3 {
139139
pub fn exticr3(&mut self) -> &afio::EXTICR3 {
140-
unsafe { &(*AFIO::ptr()).exticr3 }
140+
unsafe { (*AFIO::ptr()).exticr3() }
141141
}
142142
}
143143

@@ -147,7 +147,7 @@ pub struct EXTICR4 {
147147

148148
impl EXTICR4 {
149149
pub fn exticr4(&mut self) -> &afio::EXTICR4 {
150-
unsafe { &(*AFIO::ptr()).exticr4 }
150+
unsafe { (*AFIO::ptr()).exticr4() }
151151
}
152152
}
153153

@@ -157,6 +157,6 @@ pub struct MAPR2 {
157157

158158
impl MAPR2 {
159159
pub fn mapr2(&mut self) -> &afio::MAPR2 {
160-
unsafe { &(*AFIO::ptr()).mapr2 }
160+
unsafe { (*AFIO::ptr()).mapr2() }
161161
}
162162
}

‎src/backup_domain.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,13 +25,13 @@ pub struct BackupDomain {
2525

2626
macro_rules! write_drx {
2727
($self:ident, $drx:ident, $idx:expr, $new:expr) => {
28-
$self._regs.$drx[$idx].write(|w| w.d().bits($new))
28+
$self._regs.$drx($idx).write(|w| w.d().set($new))
2929
};
3030
}
3131

3232
macro_rules! read_drx {
3333
($self:ident, $drx:ident, $idx:expr) => {
34-
$self._regs.$drx[$idx].read().d().bits()
34+
$self._regs.$drx($idx).read().d().bits()
3535
};
3636
}
3737

‎src/crc.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -26,15 +26,15 @@ pub struct Crc {
2626

2727
impl Crc {
2828
pub fn read(&self) -> u32 {
29-
self.crc.dr.read().bits()
29+
self.crc.dr().read().bits()
3030
}
3131

3232
pub fn write(&mut self, val: u32) {
33-
self.crc.dr.write(|w| w.dr().bits(val))
33+
self.crc.dr().write(|w| w.dr().set(val))
3434
}
3535

3636
pub fn reset(&self) {
37-
self.crc.cr.write(|w| w.reset().set_bit());
37+
self.crc.cr().write(|w| w.reset().set_bit());
3838
// calling CRC::dr::write() just after CRC::cr::reset() will not work as expected, and
3939
// inserting single nop() seems to solve the problem.
4040
cortex_m::asm::nop();

‎src/dac.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -66,19 +66,19 @@ macro_rules! dac {
6666
impl DacPin for $CX {
6767
fn enable(&mut self) {
6868
let dac = unsafe { &(*DAC::ptr()) };
69-
dac.cr.modify(|_, w| w.$en().set_bit());
69+
dac.cr().modify(|_, w| w.$en().set_bit());
7070
}
7171
}
7272

7373
impl DacOut<u16> for $CX {
7474
fn set_value(&mut self, val: u16) {
7575
let dac = unsafe { &(*DAC::ptr()) };
76-
dac.$dhrx.write(|w| unsafe { w.bits(val as u32) });
76+
dac.$dhrx().write(|w| unsafe { w.bits(val as u32) });
7777
}
7878

7979
fn get_value(&mut self) -> u16 {
8080
let dac = unsafe { &(*DAC::ptr()) };
81-
dac.$dac_dor.read().bits() as u16
81+
dac.$dac_dor().read().bits() as u16
8282
}
8383
}
8484
};

‎src/dma.rs‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -144,32 +144,32 @@ macro_rules! dma {
144144
///
145145
/// `inc` indicates whether the address will be incremented after every byte transfer
146146
pub fn set_peripheral_address(&mut self, address: u32, inc: bool) {
147-
self.ch().par.write(|w| unsafe { w.pa().bits(address) } );
148-
self.ch().cr.modify(|_, w| w.pinc().bit(inc) );
147+
self.ch().par().write(|w| unsafe { w.pa().bits(address) } );
148+
self.ch().cr().modify(|_, w| w.pinc().bit(inc) );
149149
}
150150

151151
/// `address` where from/to data will be read/write
152152
///
153153
/// `inc` indicates whether the address will be incremented after every byte transfer
154154
pub fn set_memory_address(&mut self, address: u32, inc: bool) {
155-
self.ch().mar.write(|w| unsafe { w.ma().bits(address) } );
156-
self.ch().cr.modify(|_, w| w.minc().bit(inc) );
155+
self.ch().mar().write(|w| unsafe { w.ma().bits(address) } );
156+
self.ch().cr().modify(|_, w| w.minc().bit(inc) );
157157
}
158158

159159
/// Number of bytes to transfer
160160
pub fn set_transfer_length(&mut self, len: usize) {
161-
self.ch().ndtr.write(|w| w.ndt().bits(u16::try_from(len).unwrap()));
161+
self.ch().ndtr().write(|w| w.ndt().set(u16::try_from(len).unwrap()));
162162
}
163163

164164
/// Starts the DMA transfer
165165
pub fn start(&mut self) {
166-
self.ch().cr.modify(|_, w| w.en().set_bit() );
166+
self.ch().cr().modify(|_, w| w.en().set_bit() );
167167
}
168168

169169
/// Stops the DMA transfer
170170
pub fn stop(&mut self) {
171171
self.ifcr().write(|w| w.$cgifX().set_bit());
172-
self.ch().cr.modify(|_, w| w.en().clear_bit() );
172+
self.ch().cr().modify(|_, w| w.en().clear_bit() );
173173
}
174174

175175
/// Returns `true` if there's a transfer in progress
@@ -181,40 +181,40 @@ macro_rules! dma {
181181
impl $CX {
182182
pub fn listen(&mut self, event: Event) {
183183
match event {
184-
Event::HalfTransfer => self.ch().cr.modify(|_, w| w.htie().set_bit()),
184+
Event::HalfTransfer => self.ch().cr().modify(|_, w| w.htie().set_bit()),
185185
Event::TransferComplete => {
186-
self.ch().cr.modify(|_, w| w.tcie().set_bit())
186+
self.ch().cr().modify(|_, w| w.tcie().set_bit())
187187
}
188188
}
189189
}
190190

191191
pub fn unlisten(&mut self, event: Event) {
192192
match event {
193193
Event::HalfTransfer => {
194-
self.ch().cr.modify(|_, w| w.htie().clear_bit())
194+
self.ch().cr().modify(|_, w| w.htie().clear_bit())
195195
},
196196
Event::TransferComplete => {
197-
self.ch().cr.modify(|_, w| w.tcie().clear_bit())
197+
self.ch().cr().modify(|_, w| w.tcie().clear_bit())
198198
}
199199
}
200200
}
201201

202202
pub fn ch(&mut self) -> &dma1::CH {
203-
unsafe { &(*$DMAX::ptr()).$chX }
203+
unsafe { (*$DMAX::ptr()).$chX() }
204204
}
205205

206206
pub fn isr(&self) -> dma1::isr::R {
207207
// NOTE(unsafe) atomic read with no side effects
208-
unsafe { (*$DMAX::ptr()).isr.read() }
208+
unsafe { (*$DMAX::ptr()).isr().read() }
209209
}
210210

211211
pub fn ifcr(&self) -> &dma1::IFCR {
212-
unsafe { &(*$DMAX::ptr()).ifcr }
212+
unsafe { &(*$DMAX::ptr()).ifcr() }
213213
}
214214

215215
pub fn get_ndtr(&self) -> u32 {
216216
// NOTE(unsafe) atomic read with no side effects
217-
unsafe { &(*$DMAX::ptr())}.$chX.ndtr.read().bits()
217+
unsafe { &(*$DMAX::ptr())}.$chX().ndtr().read().bits()
218218
}
219219
}
220220

@@ -453,7 +453,7 @@ macro_rules! dma {
453453

454454
// reset the DMA control registers (stops all on-going transfers)
455455
$(
456-
self.$chX.cr.reset();
456+
self.$chX().cr().reset();
457457
)+
458458

459459
Channels((), $($CX { _0: () }),+)

‎src/flash.rs‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -367,7 +367,7 @@ pub struct ACR {
367367
impl ACR {
368368
pub(crate) fn acr(&mut self) -> &flash::ACR {
369369
// NOTE(unsafe) this proxy grants exclusive access to this register
370-
unsafe { &(*FLASH::ptr()).acr }
370+
unsafe { (*FLASH::ptr()).acr() }
371371
}
372372
}
373373

@@ -380,7 +380,7 @@ pub struct AR {
380380
impl AR {
381381
pub(crate) fn ar(&mut self) -> &flash::AR {
382382
// NOTE(unsafe) this proxy grants exclusive access to this register
383-
unsafe { &(*FLASH::ptr()).ar }
383+
unsafe { (*FLASH::ptr()).ar() }
384384
}
385385
}
386386

@@ -393,7 +393,7 @@ pub struct CR {
393393
impl CR {
394394
pub(crate) fn cr(&mut self) -> &flash::CR {
395395
// NOTE(unsafe) this proxy grants exclusive access to this register
396-
unsafe { &(*FLASH::ptr()).cr }
396+
unsafe { (*FLASH::ptr()).cr() }
397397
}
398398
}
399399

@@ -406,7 +406,7 @@ pub struct KEYR {
406406
impl KEYR {
407407
pub(crate) fn keyr(&mut self) -> &flash::KEYR {
408408
// NOTE(unsafe) this proxy grants exclusive access to this register
409-
unsafe { &(*FLASH::ptr()).keyr }
409+
unsafe { (*FLASH::ptr()).keyr() }
410410
}
411411
}
412412

@@ -419,7 +419,7 @@ pub struct OBR {
419419
impl OBR {
420420
pub(crate) fn obr(&mut self) -> &flash::OBR {
421421
// NOTE(unsafe) this proxy grants exclusive access to this register
422-
unsafe { &(*FLASH::ptr()).obr }
422+
unsafe { (*FLASH::ptr()).obr() }
423423
}
424424
}
425425

@@ -432,7 +432,7 @@ pub struct OPTKEYR {
432432
impl OPTKEYR {
433433
pub(crate) fn optkeyr(&mut self) -> &flash::OPTKEYR {
434434
// NOTE(unsafe) this proxy grants exclusive access to this register
435-
unsafe { &(*FLASH::ptr()).optkeyr }
435+
unsafe { (*FLASH::ptr()).optkeyr() }
436436
}
437437
}
438438

@@ -445,7 +445,7 @@ pub struct SR {
445445
impl SR {
446446
pub(crate) fn sr(&mut self) -> &flash::SR {
447447
// NOTE(unsafe) this proxy grants exclusive access to this register
448-
unsafe { &(*FLASH::ptr()).sr }
448+
unsafe { (*FLASH::ptr()).sr() }
449449
}
450450
}
451451

@@ -458,6 +458,6 @@ pub struct WRPR {
458458
impl WRPR {
459459
pub(crate) fn wrpr(&mut self) -> &flash::WRPR {
460460
// NOTE(unsafe) this proxy grants exclusive access to this register
461-
unsafe { &(*FLASH::ptr()).wrpr }
461+
unsafe { (*FLASH::ptr()).wrpr() }
462462
}
463463
}

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