diff --git a/patch/armhf_secondary_boot_online.patch b/patch/0001-armhf_secondary_boot_online.patch similarity index 100% rename from patch/armhf_secondary_boot_online.patch rename to patch/0001-armhf_secondary_boot_online.patch diff --git a/patch/0001-dt-bindings-marvell-Document-the-AC5-AC5X-compatible.patch b/patch/0001-dt-bindings-marvell-Document-the-AC5-AC5X-compatible.patch deleted file mode 100644 index 879f3f76c..000000000 --- a/patch/0001-dt-bindings-marvell-Document-the-AC5-AC5X-compatible.patch +++ /dev/null @@ -1,80 +0,0 @@ -From: Chris Packham -Date: Tue, 5 Jul 2022 22:09:19 +0300 -dt-bindings: marvell: Document the AC5/AC5X compatibles - -Describe the compatible properties for the Marvell Alleycat5/5X switches -with integrated CPUs. - -Alleycat5: -* 98DX2538: 24x1G + 2x10G + 2x10G Stack -* 98DX2535: 24x1G + 4x1G Stack -* 98DX2532: 8x1G + 2x10G + 2x1G Stack -* 98DX2531: 8x1G + 4x1G Stack -* 98DX2528: 24x1G + 2x10G + 2x10G Stack -* 98DX2525: 24x1G + 4x1G Stack -* 98DX2522: 8x1G + 2x10G + 2x1G Stack -* 98DX2521: 8x1G + 4x1G Stack -* 98DX2518: 24x1G + 2x10G + 2x10G Stack -* 98DX2515: 24x1G + 4x1G Stack -* 98DX2512: 8x1G + 2x10G + 2x1G Stack -* 98DX2511: 8x1G + 4x1G Stack - -Alleycat5X: -* 98DX3500: 24x1G + 6x25G -* 98DX3501: 16x1G + 6x10G -* 98DX3510: 48x1G + 6x25G -* 98DX3520: 24x2.5G + 6x25G -* 98DX3530: 48x2.5G + 6x25G -* 98DX3540: 12x5G/6x10G + 6x25G -* 98DX3550: 24x5G/12x10G + 6x25G - -Signed-off-by: Chris Packham -Signed-off-by: Vadym Kochan -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Gregory CLEMENT ---- - .../bindings/arm/marvell/marvell,ac5.yaml | 32 +++++++++++++++++++ - 1 file changed, 32 insertions(+) - create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml - -diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml -new file mode 100644 -index 000000000..8960fb8b2 ---- /dev/null -+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml -@@ -0,0 +1,32 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/arm/marvell/marvell,ac5.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Marvell Alleycat5/5X Platforms -+ -+maintainers: -+ - Chris Packham -+ -+properties: -+ $nodename: -+ const: '/' -+ compatible: -+ oneOf: -+ - description: Alleycat5 (98DX25xx) Reference Design -+ items: -+ - enum: -+ - marvell,rd-ac5 -+ - const: marvell,ac5 -+ -+ - description: Alleycat5X (98DX35xx) Reference Design -+ items: -+ - enum: -+ - marvell,rd-ac5x -+ - const: marvell,ac5x -+ - const: marvell,ac5 -+ -+additionalProperties: true -+ -+... --- -2.25.1 - diff --git a/patch/0006-arm64-dts-Update-cache-properties-for-marvell.patch b/patch/0002-arm64-dts-Update-cache-properties-for-marvell.patch similarity index 100% rename from patch/0006-arm64-dts-Update-cache-properties-for-marvell.patch rename to patch/0002-arm64-dts-Update-cache-properties-for-marvell.patch diff --git a/patch/0002-dt-bindings-net-mvneta-Add-marvell-armada-ac5-neta.patch b/patch/0002-dt-bindings-net-mvneta-Add-marvell-armada-ac5-neta.patch deleted file mode 100644 index 0a9c47f84..000000000 --- a/patch/0002-dt-bindings-net-mvneta-Add-marvell-armada-ac5-neta.patch +++ /dev/null @@ -1,30 +0,0 @@ -From: Chris Packham -Date: Wed, 16 Mar 2022 10:52:06 +1300 -dt-bindings: net: mvneta: Add marvell,armada-ac5-neta - -The out of band port on the 98DX2530 SoC is similar to the armada-3700 -except it requires a slightly different MBUS window configuration. Add a -new compatible string so this difference can be accounted for. - -Signed-off-by: Chris Packham -Reviewed-by: Andrew Lunn -Signed-off-by: Paolo Abeni ---- - .../devicetree/bindings/net/marvell-armada-370-neta.txt | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt -index 691f886cf..2bf31572b 100644 ---- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt -+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt -@@ -5,6 +5,7 @@ Required properties: - "marvell,armada-370-neta" - "marvell,armada-xp-neta" - "marvell,armada-3700-neta" -+ "marvell,armada-ac5-neta" - - reg: address and length of the register set for the device. - - interrupts: interrupt for the device - - phy: See ethernet.txt file in the same directory. --- -2.25.1 - diff --git a/patch/0003-arm64-dts-marvell-Add-Armada-98DX2530-SoC-and-RD-AC5.patch b/patch/0003-arm64-dts-marvell-Add-Armada-98DX2530-SoC-and-RD-AC5.patch deleted file mode 100644 index bb6e11f22..000000000 --- a/patch/0003-arm64-dts-marvell-Add-Armada-98DX2530-SoC-and-RD-AC5.patch +++ /dev/null @@ -1,467 +0,0 @@ -From: Chris Packham -Date: Tue, 5 Jul 2022 22:09:20 +0300 -arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board - -The 98DX2530 SoC is the Control and Management CPU integrated into -the Marvell 98DX25xx and 98DX35xx series of switch chip (internally -referred to as AlleyCat5 and AlleyCat5X). - -These files have been taken from the Marvell SDK and lightly cleaned -up with the License and copyright retained. - -gregory.clement: use specific cpu type: cortex-a55 instead of armv8 in -cpu nodes, armv8 being reserved for the arm virtual models that are -not meant to implement a particular CPU type. - -Signed-off-by: Chris Packham -Signed-off-by: Vadym Kochan -Signed-off-by: Gregory CLEMENT ---- - arch/arm64/boot/dts/marvell/Makefile | 1 + - arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 291 ++++++++++++++++++ - .../boot/dts/marvell/ac5-98dx35xx-rd.dts | 101 ++++++ - arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi | 17 + - 4 files changed, 410 insertions(+) - create mode 100644 arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi - create mode 100644 arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts - create mode 100644 arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi - -diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile -index 3e5f2e7a0..5e9c34d1e 100644 ---- a/arch/arm64/boot/dts/marvell/Makefile -+++ b/arch/arm64/boot/dts/marvell/Makefile -@@ -16,3 +16,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb - dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb - dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb - dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb -+dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb -diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -new file mode 100644 -index 000000000..80b44c7df ---- /dev/null -+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -@@ -0,0 +1,291 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree For AC5. -+ * -+ * Copyright (C) 2021 Marvell -+ * Copyright (C) 2022 Allied Telesis Labs -+ */ -+ -+#include -+#include -+ -+/ { -+ model = "Marvell AC5 SoC"; -+ compatible = "marvell,ac5"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ cpu-map { -+ cluster0 { -+ core0 { -+ cpu = <&cpu0>; -+ }; -+ core1 { -+ cpu = <&cpu1>; -+ }; -+ }; -+ }; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a55"; -+ reg = <0x0 0x0>; -+ enable-method = "psci"; -+ next-level-cache = <&l2>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a55"; -+ reg = <0x0 0x100>; -+ enable-method = "psci"; -+ next-level-cache = <&l2>; -+ }; -+ -+ l2: l2-cache { -+ compatible = "cache"; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-0.2"; -+ method = "smc"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = ; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ dma-ranges; -+ -+ internal-regs@7f000000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "simple-bus"; -+ /* 16M internal register @ 0x7f00_0000 */ -+ ranges = <0x0 0x0 0x7f000000 0x1000000>; -+ dma-coherent; -+ -+ uart0: serial@12000 { -+ compatible = "snps,dw-apb-uart"; -+ reg = <0x12000 0x100>; -+ reg-shift = <2>; -+ interrupts = ; -+ reg-io-width = <1>; -+ clocks = <&cnm_clock>; -+ status = "okay"; -+ }; -+ -+ mdio: mdio@22004 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "marvell,orion-mdio"; -+ reg = <0x22004 0x4>; -+ clocks = <&cnm_clock>; -+ }; -+ -+ i2c0: i2c@11000{ -+ compatible = "marvell,mv78230-i2c"; -+ reg = <0x11000 0x20>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ clocks = <&cnm_clock>; -+ clock-names = "core"; -+ interrupts = ; -+ clock-frequency=<100000>; -+ -+ pinctrl-names = "default", "gpio"; -+ pinctrl-0 = <&i2c0_pins>; -+ pinctrl-1 = <&i2c0_gpio>; -+ scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; -+ sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@11100{ -+ compatible = "marvell,mv78230-i2c"; -+ reg = <0x11100 0x20>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ clocks = <&cnm_clock>; -+ clock-names = "core"; -+ interrupts = ; -+ clock-frequency=<100000>; -+ -+ pinctrl-names = "default", "gpio"; -+ pinctrl-0 = <&i2c1_pins>; -+ pinctrl-1 = <&i2c1_gpio>; -+ scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; -+ sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; -+ status = "disabled"; -+ }; -+ -+ gpio0: gpio@18100 { -+ compatible = "marvell,orion-gpio"; -+ reg = <0x18100 0x40>; -+ ngpios = <32>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-ranges = <&pinctrl0 0 0 32>; -+ marvell,pwm-offset = <0x1f0>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ gpio1: gpio@18140 { -+ reg = <0x18140 0x40>; -+ compatible = "marvell,orion-gpio"; -+ ngpios = <14>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-ranges = <&pinctrl0 0 32 14>; -+ marvell,pwm-offset = <0x1f0>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ interrupts = , -+ ; -+ }; -+ }; -+ -+ /* -+ * Dedicated section for devices behind 32bit controllers so we -+ * can configure specific DMA mapping for them -+ */ -+ behind-32bit-controller@7f000000 { -+ compatible = "simple-bus"; -+ #address-cells = <0x2>; -+ #size-cells = <0x2>; -+ ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; -+ /* Host phy ram starts at 0x200M */ -+ dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>; -+ dma-coherent; -+ -+ eth0: ethernet@20000 { -+ compatible = "marvell,armada-ac5-neta"; -+ reg = <0x0 0x20000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cnm_clock>; -+ phy-mode = "sgmii"; -+ status = "disabled"; -+ }; -+ -+ eth1: ethernet@24000 { -+ compatible = "marvell,armada-ac5-neta"; -+ reg = <0x0 0x24000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cnm_clock>; -+ phy-mode = "sgmii"; -+ status = "disabled"; -+ }; -+ -+ usb0: usb@80000 { -+ compatible = "marvell,orion-ehci"; -+ reg = <0x0 0x80000 0x0 0x500>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ usb1: usb@a0000 { -+ compatible = "marvell,orion-ehci"; -+ reg = <0x0 0xa0000 0x0 0x500>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ }; -+ -+ pinctrl0: pinctrl@80020100 { -+ compatible = "marvell,ac5-pinctrl"; -+ reg = <0 0x80020100 0 0x20>; -+ -+ i2c0_pins: i2c0-pins { -+ marvell,pins = "mpp26", "mpp27"; -+ marvell,function = "i2c0"; -+ }; -+ -+ i2c0_gpio: i2c0-gpio-pins { -+ marvell,pins = "mpp26", "mpp27"; -+ marvell,function = "gpio"; -+ }; -+ -+ i2c1_pins: i2c1-pins { -+ marvell,pins = "mpp20", "mpp21"; -+ marvell,function = "i2c1"; -+ }; -+ -+ i2c1_gpio: i2c1-gpio-pins { -+ marvell,pins = "mpp20", "mpp21"; -+ marvell,function = "i2c1"; -+ }; -+ }; -+ -+ spi0: spi@805a0000 { -+ compatible = "marvell,armada-3700-spi"; -+ reg = <0x0 0x805a0000 0x0 0x50>; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ clocks = <&spi_clock>; -+ interrupts = ; -+ num-cs = <1>; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@805a8000 { -+ compatible = "marvell,armada-3700-spi"; -+ reg = <0x0 0x805a8000 0x0 0x50>; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ clocks = <&spi_clock>; -+ interrupts = ; -+ num-cs = <1>; -+ status = "disabled"; -+ }; -+ -+ gic: interrupt-controller@80600000 { -+ compatible = "arm,gic-v3"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ -+ <0x0 0x80660000 0x0 0x40000>; /* GICR */ -+ interrupts = ; -+ }; -+ }; -+ -+ clocks { -+ cnm_clock: cnm-clock { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <328000000>; -+ }; -+ -+ spi_clock: spi-clock { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts b/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts -new file mode 100644 -index 000000000..f0ebdb84e ---- /dev/null -+++ b/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts -@@ -0,0 +1,101 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree For RD-AC5X. -+ * -+ * Copyright (C) 2021 Marvell -+ * Copyright (C) 2022 Allied Telesis Labs -+ */ -+/* -+ * Device Tree file for Marvell Alleycat 5X development board -+ * This board file supports the B configuration of the board -+ */ -+ -+/dts-v1/; -+ -+#include "ac5-98dx35xx.dtsi" -+ -+/ { -+ model = "Marvell RD-AC5X Board"; -+ compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5"; -+ -+ aliases { -+ serial0 = &uart0; -+ spiflash0 = &spiflash0; -+ gpio0 = &gpio0; -+ gpio1 = &gpio1; -+ ethernet0 = ð0; -+ ethernet1 = ð1; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x2 0x00000000 0x0 0x40000000>; -+ }; -+ -+ usb1phy: usb-phy { -+ compatible = "usb-nop-xceiv"; -+ #phy-cells = <0>; -+ }; -+}; -+ -+&mdio { -+ phy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+}; -+ -+&i2c0 { -+ status = "okay"; -+}; -+ -+&i2c1 { -+ status = "okay"; -+}; -+ -+ð0 { -+ status = "okay"; -+ phy-handle = <&phy0>; -+}; -+ -+/* USB0 is a host USB */ -+&usb0 { -+ status = "okay"; -+}; -+ -+/* USB1 is a peripheral USB */ -+&usb1 { -+ status = "okay"; -+ phys = <&usb1phy>; -+ phy-names = "usb-phy"; -+ dr_mode = "peripheral"; -+}; -+ -+&spi0 { -+ status = "okay"; -+ -+ spiflash0: flash@0 { -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <50000000>; -+ spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ -+ spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ -+ reg = <0>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "spi_flash_part0"; -+ reg = <0x0 0x800000>; -+ }; -+ -+ parition@1 { -+ label = "spi_flash_part1"; -+ reg = <0x800000 0x700000>; -+ }; -+ -+ parition@2 { -+ label = "spi_flash_part2"; -+ reg = <0xF00000 0x100000>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi -new file mode 100644 -index 000000000..2ab72f854 ---- /dev/null -+++ b/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi -@@ -0,0 +1,17 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree For AC5X. -+ * -+ * Copyright (C) 2022 Allied Telesis Labs -+ */ -+ -+#include "ac5-98dx25xx.dtsi" -+ -+/ { -+ model = "Marvell AC5X SoC"; -+ compatible = "marvell,ac5x", "marvell,ac5"; -+}; -+ -+&cnm_clock { -+ clock-frequency = <325000000>; -+}; --- -2.25.1 - diff --git a/patch/0003-dt-bindings-ac5-Add-mmc-and-usb-properties.patch b/patch/0003-dt-bindings-ac5-Add-mmc-and-usb-properties.patch new file mode 100644 index 000000000..84d86e8d4 --- /dev/null +++ b/patch/0003-dt-bindings-ac5-Add-mmc-and-usb-properties.patch @@ -0,0 +1,62 @@ +From: Keshav Gupta +Date: Thu, 5 Oct 2023 05:48:50 +0000 +Subject: [PATCH] dt-bindings: ac5: Add mmc and usb properties + +Describe compatible string in Marvell Xenon SDHCI Controller for mmc. +Also documents compatible string for ac5 in ehci-orion. + +Signed-off-by: Noam Liron +--- + .../bindings/mmc/marvell,xenon-sdhci.yaml | 19 +++++++++++++++++++ + .../devicetree/bindings/usb/ehci-orion.txt | 1 + + 2 files changed, 20 insertions(+) + +diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml +index 3ee758886..459a71c1c 100644 +--- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml +@@ -33,6 +33,7 @@ properties: + - items: + - const: marvell,armada-3700-sdhci + - const: marvell,sdhci-xenon ++ - const: marvell,ac5-sdhci + + reg: + minItems: 1 +@@ -275,3 +276,21 @@ examples: + + marvell,pad-type = "sd"; + }; ++ ++ //For eMMC with compatible "marvell,ac5-sdhci": ++ mmc@805c0000 { ++ compatible = "marvell,ac5-sdhci"; ++ reg = <0x0 0x805c0000>; ++ reg-names = "ctrl"; ++ interrupts = ; ++ clocks = <&core_clock>; ++ clock-names = "core"; ++ status = "okay"; ++ bus-width = <8>; ++ /*marvell,xenon-phy-slow-mode;*/ ++ non-removable; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ }; ++ +diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt +index 2855bae79..83e4d8992 100644 +--- a/Documentation/devicetree/bindings/usb/ehci-orion.txt ++++ b/Documentation/devicetree/bindings/usb/ehci-orion.txt +@@ -4,6 +4,7 @@ Required properties: + - compatible: must be one of the following + "marvell,orion-ehci" + "marvell,armada-3700-ehci" ++ "marvell,ac5-ehci" + - reg: physical base address of the controller and length of memory mapped + region. + - interrupts: The EHCI interrupt +-- +2.25.1 + diff --git a/patch/0004-arm64-dts-marvell-Add-UART1-3-for-AC5-AC5X.patch b/patch/0004-arm64-dts-marvell-Add-UART1-3-for-AC5-AC5X.patch deleted file mode 100644 index 6e24a86c8..000000000 --- a/patch/0004-arm64-dts-marvell-Add-UART1-3-for-AC5-AC5X.patch +++ /dev/null @@ -1,57 +0,0 @@ -From: Chris Packham -Date: Wed, 3 Aug 2022 13:16:23 +1200 -arm64: dts: marvell: Add UART1-3 for AC5/AC5X - -The AC5/AC5X SoC has 4 UART blocks. Add the additional UART1-3 blocks to -the base dtsi file. - -Signed-off-by: Chris Packham -Signed-off-by: Gregory CLEMENT ---- - arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 30 +++++++++++++++++++ - 1 file changed, 30 insertions(+) - -diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -index 80b44c7df..914fcf9e2 100644 ---- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -@@ -95,6 +95,36 @@ uart0: serial@12000 { - status = "okay"; - }; - -+ uart1: serial@12100 { -+ compatible = "snps,dw-apb-uart"; -+ reg = <0x11000 0x100>; -+ reg-shift = <2>; -+ interrupts = ; -+ reg-io-width = <1>; -+ clocks = <&cnm_clock>; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@12200 { -+ compatible = "snps,dw-apb-uart"; -+ reg = <0x12200 0x100>; -+ reg-shift = <2>; -+ interrupts = ; -+ reg-io-width = <1>; -+ clocks = <&cnm_clock>; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@12300 { -+ compatible = "snps,dw-apb-uart"; -+ reg = <0x12300 0x100>; -+ reg-shift = <2>; -+ interrupts = ; -+ reg-io-width = <1>; -+ clocks = <&cnm_clock>; -+ status = "disabled"; -+ }; -+ - mdio: mdio@22004 { - #address-cells = <1>; - #size-cells = <0>; --- -2.25.1 - diff --git a/patch/0014-dts-ac5-marvell-Add-switching-mmc-watchdog-node.patch b/patch/0004-dts-ac5-marvell-Add-switching-mmc-watchdog-node.patch similarity index 100% rename from patch/0014-dts-ac5-marvell-Add-switching-mmc-watchdog-node.patch rename to patch/0004-dts-ac5-marvell-Add-switching-mmc-watchdog-node.patch diff --git a/patch/0015-ac5-marvell-Add-watchdog-support.patch b/patch/0005-ac5-marvell-Add-watchdog-support.patch similarity index 100% rename from patch/0015-ac5-marvell-Add-watchdog-support.patch rename to patch/0005-ac5-marvell-Add-watchdog-support.patch diff --git a/patch/0005-arm64-dts-marvell-98dx25xx-Fix-i2c-gpios-property.patch b/patch/0005-arm64-dts-marvell-98dx25xx-Fix-i2c-gpios-property.patch deleted file mode 100644 index fc5cf48ab..000000000 --- a/patch/0005-arm64-dts-marvell-98dx25xx-Fix-i2c-gpios-property.patch +++ /dev/null @@ -1,43 +0,0 @@ -From: Chris Packham -Date: Thu, 1 Sep 2022 14:28:08 +1200 -arm64: dts: marvell: 98dx25xx: Fix i2c gpios property - -Use the correct names for scl-gpios and sda-gpios so that the generic -i2c recovery code will find them. While we're here set the -GPIO_OPEN_DRAIN flag on the gpios. - -Signed-off-by: Chris Packham -Signed-off-by: Gregory CLEMENT ---- - arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -index 914fcf9e2..44ed6f963 100644 ---- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -@@ -147,8 +147,8 @@ i2c0: i2c@11000{ - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c0_pins>; - pinctrl-1 = <&i2c0_gpio>; -- scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; -- sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; -+ scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; - }; - -@@ -166,8 +166,8 @@ i2c1: i2c@11100{ - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c1_pins>; - pinctrl-1 = <&i2c1_gpio>; -- scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; -- sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; -+ scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; - }; - --- -2.25.1 - diff --git a/patch/0006-ac5-marvell-Add-support-for-emmc.patch b/patch/0006-ac5-marvell-Add-support-for-emmc.patch new file mode 100644 index 000000000..6680d1f2e --- /dev/null +++ b/patch/0006-ac5-marvell-Add-support-for-emmc.patch @@ -0,0 +1,76 @@ +From: Keshav Gupta +Date: Tue, 10 Oct 2023 06:57:22 +0000 +Subject: [PATCH] ac5: marvell: Add support for emmc + +This patch adds ac5-sdhci compatible checks in Marvell Xenon SDHCI +Controller for emmc support in 98DX25xx SoC. + +Tested-by: Raz Adashi +Reviewed-by: Raz Adashi +Signed-off-by: Noam Liron +--- + drivers/mmc/host/sdhci-xenon.c | 12 ++++++++++++ + drivers/mmc/host/sdhci-xenon.h | 3 ++- + 2 files changed, 14 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c +index 08e838400..d885752dc 100644 +--- a/drivers/mmc/host/sdhci-xenon.c ++++ b/drivers/mmc/host/sdhci-xenon.c +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + + #include "sdhci-pltfm.h" + #include "sdhci-xenon.h" +@@ -422,6 +423,8 @@ static int xenon_probe_params(struct platform_device *pdev) + struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); + u32 sdhc_id, nr_sdhc; + u32 tuning_count; ++ struct sysinfo si; ++ struct device_node *np = pdev->dev.of_node; + + /* Disable HS200 on Armada AP806 */ + if (priv->hw_version == XENON_AP806) +@@ -450,6 +453,14 @@ static int xenon_probe_params(struct platform_device *pdev) + } + priv->tuning_count = tuning_count; + ++ si_meminfo(&si); ++ if (of_device_is_compatible(np, "marvell,ac5-sdhci") && ++ ((si.totalram * si.mem_unit) > 0x80000000 /*2G*/)) { ++ host->quirks |= SDHCI_QUIRK_BROKEN_DMA; ++ host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; ++ dev_info(mmc_dev(mmc), "Disabling DMA because of 2GB DMA access limit.\n"); ++ } ++ + return xenon_phy_parse_params(dev, host); + } + +@@ -682,6 +693,7 @@ static const struct of_device_id sdhci_xenon_dt_ids[] = { + { .compatible = "marvell,armada-ap807-sdhci", .data = (void *)XENON_AP807}, + { .compatible = "marvell,armada-cp110-sdhci", .data = (void *)XENON_CP110}, + { .compatible = "marvell,armada-3700-sdhci", .data = (void *)XENON_A3700}, ++ { .compatible = "marvell,ac5-sdhci", .data = (void *)XENON_AC5}, + {} + }; + MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids); +diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h +index 3e9c6c908..0460d97aa 100644 +--- a/drivers/mmc/host/sdhci-xenon.h ++++ b/drivers/mmc/host/sdhci-xenon.h +@@ -57,7 +57,8 @@ enum xenon_variant { + XENON_A3700, + XENON_AP806, + XENON_AP807, +- XENON_CP110 ++ XENON_CP110, ++ XENON_AC5 + }; + + struct xenon_priv { +-- +2.25.1 + diff --git a/patch/0007-arm64-dts-marvell-AC5-AC5X-Fix-address-for-UART1.patch b/patch/0007-arm64-dts-marvell-AC5-AC5X-Fix-address-for-UART1.patch deleted file mode 100644 index 5981a009c..000000000 --- a/patch/0007-arm64-dts-marvell-AC5-AC5X-Fix-address-for-UART1.patch +++ /dev/null @@ -1,29 +0,0 @@ -From: Chris Packham -Date: Thu, 15 Dec 2022 15:54:02 +1300 -arm64: dts: marvell: AC5/AC5X: Fix address for UART1 - -The correct address offset is 0x12100. - -Fixes: 31be791e26cf ("arm64: dts: marvell: Add UART1-3 for AC5/AC5X") -Signed-off-by: Chris Packham -Signed-off-by: Gregory CLEMENT ---- - arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -index 7308f7b6b..8bce64069 100644 ---- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi -@@ -98,7 +98,7 @@ uart0: serial@12000 { - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; -- reg = <0x11000 0x100>; -+ reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; --- -2.25.1 - diff --git a/patch/0017-usb-ehci-Add-support-for-ac5.patch b/patch/0007-usb-ehci-Add-support-for-ac5.patch similarity index 100% rename from patch/0017-usb-ehci-Add-support-for-ac5.patch rename to patch/0007-usb-ehci-Add-support-for-ac5.patch diff --git a/patch/0008-mtd-rawnand-marvell-Add-missing-layouts.patch b/patch/0008-mtd-rawnand-marvell-Add-missing-layouts.patch deleted file mode 100644 index 8c46523d8..000000000 --- a/patch/0008-mtd-rawnand-marvell-Add-missing-layouts.patch +++ /dev/null @@ -1,44 +0,0 @@ -From: Aviram Dali -Date: Fri, 16 Dec 2022 18:27:15 +0200 -mtd: rawnand: marvell: Add missing layouts - -Missing layouts were added to the driver to support NAND flashes -with ECC layouts of 12 or 16 with page sized of 2048, 4096 or 8192. - -Usually theses are rare layouts, but in Marvell AC5 driver, the ECC -level is set according to the spare area, so we may use these layouts -more frequently. - -Signed-off-by: Aviram Dali -Signed-off-by: Vadym Kochan -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20221216162715.3230766-1-vadym.kochan@plvision.eu ---- - drivers/mtd/nand/raw/marvell_nand.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c -index d00c916f1..241de3912 100644 ---- a/drivers/mtd/nand/raw/marvell_nand.c -+++ b/drivers/mtd/nand/raw/marvell_nand.c -@@ -287,10 +287,17 @@ static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = { - MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0), - MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0), - MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,32, 30), -+ MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,64, 30), -+ MARVELL_LAYOUT( 2048, 512, 12, 3, 2, 704, 0, 30,640, 0, 30), -+ MARVELL_LAYOUT( 2048, 512, 16, 5, 4, 512, 0, 30, 0, 32, 30), - MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0), - MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30), -+ MARVELL_LAYOUT( 4096, 512, 12, 6, 5, 704, 0, 30,576, 32, 30), -+ MARVELL_LAYOUT( 4096, 512, 16, 9, 8, 512, 0, 30, 0, 32, 30), - MARVELL_LAYOUT( 8192, 512, 4, 4, 4, 2048, 0, 30, 0, 0, 0), - MARVELL_LAYOUT( 8192, 512, 8, 9, 8, 1024, 0, 30, 0, 160, 30), -+ MARVELL_LAYOUT( 8192, 512, 12, 12, 11, 704, 0, 30,448, 64, 30), -+ MARVELL_LAYOUT( 8192, 512, 16, 17, 16, 512, 0, 30, 0, 32, 30), - }; - - /** --- -2.25.1 - diff --git a/patch/0018-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch b/patch/0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch similarity index 82% rename from patch/0018-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch rename to patch/0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch index 51378bc87..393c73a76 100644 --- a/patch/0018-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch +++ b/patch/0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch @@ -1,6 +1,7 @@ -From: Pavan Naregundi -Date: Fri, 10 Mar 2023 00:41:54 +0000 -mv6xxx: Fix i2c lock due to arb-loss +From 1c7573db2c31e4b30662554d230325ffcbb884e1 Mon Sep 17 00:00:00 2001 +From: Keshav Gupta +Date: Mon, 16 Oct 2023 15:14:03 +0000 +Subject: [PATCH] mv6xxx: Fix i2c lock due to arb-loss Some i2c slaves, mainly SFPs, might cause the bus to lost arbitration while slave is in the middle of responding. @@ -12,11 +13,11 @@ Tested-by: Raz Adashi Reviewed-by: Raz Adashi Signed-off-by: Noam Liron --- - drivers/i2c/busses/i2c-mv64xxx.c | 82 ++++++++++++++++++++++++++++++++ - 1 file changed, 82 insertions(+) + drivers/i2c/busses/i2c-mv64xxx.c | 81 ++++++++++++++++++++++++++++++++ + 1 file changed, 81 insertions(+) diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c -index e0e45fc19..804cd227b 100644 +index 878c076eb..180c32cf9 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c @@ -9,6 +9,8 @@ @@ -28,7 +29,7 @@ index e0e45fc19..804cd227b 100644 #include #include #include -@@ -25,6 +27,7 @@ +@@ -27,6 +29,7 @@ #include #include #include @@ -36,7 +37,7 @@ index e0e45fc19..804cd227b 100644 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1) #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7) -@@ -103,6 +106,7 @@ enum { +@@ -105,6 +108,7 @@ enum { MV64XXX_I2C_ACTION_RCV_DATA, MV64XXX_I2C_ACTION_RCV_DATA_STOP, MV64XXX_I2C_ACTION_SEND_STOP, @@ -44,11 +45,10 @@ index e0e45fc19..804cd227b 100644 }; struct mv64xxx_i2c_regs { -@@ -147,6 +151,12 @@ struct mv64xxx_i2c_data { - bool irq_clear_inverted; - /* Clk div is 2 to the power n, not 2 to the power n + 1 */ +@@ -151,6 +155,11 @@ struct mv64xxx_i2c_data { bool clk_n_base_0; -+ + struct i2c_bus_recovery_info rinfo; + bool atomic; + /* I2C mpp states & gpios needed for ARB lost recovery */ + int scl_gpio, sda_gpio; + bool arb_lost_reovery_ena; @@ -57,7 +57,7 @@ index e0e45fc19..804cd227b 100644 }; static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = { -@@ -308,6 +318,11 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) +@@ -319,6 +328,11 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) drv_data->state = MV64XXX_I2C_STATE_IDLE; break; @@ -69,7 +69,7 @@ index e0e45fc19..804cd227b 100644 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ -@@ -345,6 +360,9 @@ static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data) +@@ -357,6 +371,9 @@ static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data) static void mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) { @@ -79,7 +79,7 @@ index e0e45fc19..804cd227b 100644 switch(drv_data->action) { case MV64XXX_I2C_ACTION_SEND_RESTART: /* We should only get here if we have further messages */ -@@ -398,6 +416,46 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) +@@ -410,6 +427,46 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) drv_data->reg_base + drv_data->reg_offsets.control); break; @@ -108,9 +108,9 @@ index e0e45fc19..804cd227b 100644 + gpio_set_value(drv_data->scl_gpio, 0); + }; + -+ devm_gpio_free(drv_data->adapter.dev.parent, ++ devm_gpiod_put(drv_data->adapter.dev.parent, + drv_data->scl_gpio); -+ devm_gpio_free(drv_data->adapter.dev.parent, ++ devm_gpiod_put(drv_data->adapter.dev.parent, + drv_data->sda_gpio); + } + @@ -126,7 +126,7 @@ index e0e45fc19..804cd227b 100644 case MV64XXX_I2C_ACTION_RCV_DATA_STOP: drv_data->msg->buf[drv_data->byte_posn++] = readl(drv_data->reg_base + drv_data->reg_offsets.data); -@@ -875,6 +933,7 @@ mv64xxx_i2c_probe(struct platform_device *pd) +@@ -986,6 +1043,7 @@ mv64xxx_i2c_probe(struct platform_device *pd) { struct mv64xxx_i2c_data *drv_data; struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev); @@ -134,9 +134,9 @@ index e0e45fc19..804cd227b 100644 int rc; if ((!pdata && !pd->dev.of_node)) -@@ -926,6 +985,29 @@ mv64xxx_i2c_probe(struct platform_device *pd) - goto exit_reset; - } +@@ -1041,6 +1099,29 @@ mv64xxx_i2c_probe(struct platform_device *pd) + if (rc == -EPROBE_DEFER) + return rc; + drv_data->arb_lost_reovery_ena = false; + pc = devm_pinctrl_get(&pd->dev); diff --git a/patch/0019-dt-bindings-marvell-Add-ARMADA-7K-properties.patch b/patch/0009-dt-bindings-marvell-Add-ARMADA-7K-properties.patch similarity index 100% rename from patch/0019-dt-bindings-marvell-Add-ARMADA-7K-properties.patch rename to patch/0009-dt-bindings-marvell-Add-ARMADA-7K-properties.patch diff --git a/patch/0009-pinctrl-mvebu-Add-driver-for-98DX2530-SoC.patch b/patch/0009-pinctrl-mvebu-Add-driver-for-98DX2530-SoC.patch deleted file mode 100644 index 454b45880..000000000 --- a/patch/0009-pinctrl-mvebu-Add-driver-for-98DX2530-SoC.patch +++ /dev/null @@ -1,313 +0,0 @@ -From: Chris Packham -Date: Fri, 15 Apr 2022 11:30:53 +1200 -pinctrl: mvebu: Add driver for 98DX2530 SoC - -This pinctrl driver supports the 98DX25xx and 98DX35xx family of chips -from Marvell. It is based on the Marvell SDK with additions for various -(non-gpio) pin configurations based on the datasheet. - -Signed-off-by: Chris Packham -Reviewed-by: Andrew Lunn -Link: https://lore.kernel.org/r/20220414233055.586962-3-chris.packham@alliedtelesis.co.nz -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mvebu/Kconfig | 4 + - drivers/pinctrl/mvebu/Makefile | 1 + - drivers/pinctrl/mvebu/pinctrl-ac5.c | 261 ++++++++++++++++++++++++++++ - 3 files changed, 266 insertions(+) - create mode 100644 drivers/pinctrl/mvebu/pinctrl-ac5.c - -diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig -index 0d12894d3..aa5883f09 100644 ---- a/drivers/pinctrl/mvebu/Kconfig -+++ b/drivers/pinctrl/mvebu/Kconfig -@@ -45,6 +45,10 @@ config PINCTRL_ORION - bool - select PINCTRL_MVEBU - -+config PINCTRL_AC5 -+ bool -+ select PINCTRL_MVEBU -+ - config PINCTRL_ARMADA_37XX - bool - select GENERIC_PINCONF -diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile -index cd082dca4..23458ab17 100644 ---- a/drivers/pinctrl/mvebu/Makefile -+++ b/drivers/pinctrl/mvebu/Makefile -@@ -11,3 +11,4 @@ obj-$(CONFIG_PINCTRL_ARMADA_CP110) += pinctrl-armada-cp110.o - obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o - obj-$(CONFIG_PINCTRL_ARMADA_37XX) += pinctrl-armada-37xx.o - obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o -+obj-$(CONFIG_PINCTRL_AC5) += pinctrl-ac5.o -diff --git a/drivers/pinctrl/mvebu/pinctrl-ac5.c b/drivers/pinctrl/mvebu/pinctrl-ac5.c -new file mode 100644 -index 000000000..292633e61 ---- /dev/null -+++ b/drivers/pinctrl/mvebu/pinctrl-ac5.c -@@ -0,0 +1,261 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Marvell ac5 pinctrl driver based on mvebu pinctrl core -+ * -+ * Copyright (C) 2021 Marvell -+ * -+ * Noam Liron -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pinctrl-mvebu.h" -+ -+static struct mvebu_mpp_mode ac5_mpp_modes[] = { -+ MPP_MODE(0, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "d0"), -+ MPP_FUNCTION(2, "nand", "io4")), -+ MPP_MODE(1, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "d1"), -+ MPP_FUNCTION(2, "nand", "io3")), -+ MPP_MODE(2, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "d2"), -+ MPP_FUNCTION(2, "nand", "io2")), -+ MPP_MODE(3, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "d3"), -+ MPP_FUNCTION(2, "nand", "io7")), -+ MPP_MODE(4, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "d4"), -+ MPP_FUNCTION(2, "nand", "io6"), -+ MPP_FUNCTION(3, "uart3", "txd"), -+ MPP_FUNCTION(4, "uart2", "txd")), -+ MPP_MODE(5, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "d5"), -+ MPP_FUNCTION(2, "nand", "io5"), -+ MPP_FUNCTION(3, "uart3", "rxd"), -+ MPP_FUNCTION(4, "uart2", "rxd")), -+ MPP_MODE(6, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "d6"), -+ MPP_FUNCTION(2, "nand", "io0"), -+ MPP_FUNCTION(3, "i2c1", "sck")), -+ MPP_MODE(7, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "d7"), -+ MPP_FUNCTION(2, "nand", "io1"), -+ MPP_FUNCTION(3, "i2c1", "sda")), -+ MPP_MODE(8, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "clk"), -+ MPP_FUNCTION(2, "nand", "wen")), -+ MPP_MODE(9, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "cmd"), -+ MPP_FUNCTION(2, "nand", "ale")), -+ MPP_MODE(10, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "ds"), -+ MPP_FUNCTION(2, "nand", "cle")), -+ MPP_MODE(11, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "sdio", "rst"), -+ MPP_FUNCTION(2, "nand", "cen")), -+ MPP_MODE(12, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "spi0", "clk")), -+ MPP_MODE(13, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "spi0", "csn")), -+ MPP_MODE(14, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "spi0", "mosi")), -+ MPP_MODE(15, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "spi0", "miso")), -+ MPP_MODE(16, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "spi0", "wpn"), -+ MPP_FUNCTION(2, "nand", "ren"), -+ MPP_FUNCTION(3, "uart1", "txd")), -+ MPP_MODE(17, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "spi0", "hold"), -+ MPP_FUNCTION(2, "nand", "rb"), -+ MPP_FUNCTION(3, "uart1", "rxd")), -+ MPP_MODE(18, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "tsen_int", NULL), -+ MPP_FUNCTION(2, "uart2", "rxd"), -+ MPP_FUNCTION(3, "wd_int", NULL)), -+ MPP_MODE(19, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "dev_init_done", NULL), -+ MPP_FUNCTION(2, "uart2", "txd")), -+ MPP_MODE(20, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(2, "i2c1", "sck"), -+ MPP_FUNCTION(3, "spi1", "clk"), -+ MPP_FUNCTION(4, "uart3", "txd")), -+ MPP_MODE(21, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(2, "i2c1", "sda"), -+ MPP_FUNCTION(3, "spi1", "csn"), -+ MPP_FUNCTION(4, "uart3", "rxd")), -+ MPP_MODE(22, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(3, "spi1", "mosi")), -+ MPP_MODE(23, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(3, "spi1", "miso")), -+ MPP_MODE(24, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "wd_int", NULL), -+ MPP_FUNCTION(2, "uart2", "txd"), -+ MPP_FUNCTION(3, "uartsd", "txd")), -+ MPP_MODE(25, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "int_out", NULL), -+ MPP_FUNCTION(2, "uart2", "rxd"), -+ MPP_FUNCTION(3, "uartsd", "rxd")), -+ MPP_MODE(26, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "i2c0", "sck"), -+ MPP_FUNCTION(2, "ptp", "clk1"), -+ MPP_FUNCTION(3, "uart3", "txd")), -+ MPP_MODE(27, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "i2c0", "sda"), -+ MPP_FUNCTION(2, "ptp", "pulse"), -+ MPP_FUNCTION(3, "uart3", "rxd")), -+ MPP_MODE(28, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "xg", "mdio"), -+ MPP_FUNCTION(2, "ge", "mdio"), -+ MPP_FUNCTION(3, "uart3", "txd")), -+ MPP_MODE(29, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "xg", "mdio"), -+ MPP_FUNCTION(2, "ge", "mdio"), -+ MPP_FUNCTION(3, "uart3", "rxd")), -+ MPP_MODE(30, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "xg", "mdio"), -+ MPP_FUNCTION(2, "ge", "mdio"), -+ MPP_FUNCTION(3, "ge", "mdio")), -+ MPP_MODE(31, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "xg", "mdio"), -+ MPP_FUNCTION(2, "ge", "mdio"), -+ MPP_FUNCTION(3, "ge", "mdio")), -+ MPP_MODE(32, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "uart0", "txd")), -+ MPP_MODE(33, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "uart0", "rxd"), -+ MPP_FUNCTION(2, "ptp", "clk1"), -+ MPP_FUNCTION(3, "ptp", "pulse")), -+ MPP_MODE(34, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "ge", "mdio"), -+ MPP_FUNCTION(2, "uart3", "rxd")), -+ MPP_MODE(35, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "ge", "mdio"), -+ MPP_FUNCTION(2, "uart3", "txd"), -+ MPP_FUNCTION(3, "pcie", "rstoutn")), -+ MPP_MODE(36, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "ptp", "clk0_tp"), -+ MPP_FUNCTION(2, "ptp", "clk1_tp")), -+ MPP_MODE(37, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "ptp", "pulse_tp"), -+ MPP_FUNCTION(2, "wd_int", NULL)), -+ MPP_MODE(38, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "synce", "clk_out0")), -+ MPP_MODE(39, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "synce", "clk_out1")), -+ MPP_MODE(40, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "ptp", "pclk_out0"), -+ MPP_FUNCTION(2, "ptp", "pclk_out1")), -+ MPP_MODE(41, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "ptp", "ref_clk"), -+ MPP_FUNCTION(2, "ptp", "clk1"), -+ MPP_FUNCTION(3, "ptp", "pulse"), -+ MPP_FUNCTION(4, "uart2", "txd"), -+ MPP_FUNCTION(5, "i2c1", "sck")), -+ MPP_MODE(42, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "ptp", "clk0"), -+ MPP_FUNCTION(2, "ptp", "clk1"), -+ MPP_FUNCTION(3, "ptp", "pulse"), -+ MPP_FUNCTION(4, "uart2", "rxd"), -+ MPP_FUNCTION(5, "i2c1", "sda")), -+ MPP_MODE(43, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "led", "clk")), -+ MPP_MODE(44, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "led", "stb")), -+ MPP_MODE(45, -+ MPP_FUNCTION(0, "gpio", NULL), -+ MPP_FUNCTION(1, "led", "data")), -+}; -+ -+static struct mvebu_pinctrl_soc_info ac5_pinctrl_info; -+ -+static const struct of_device_id ac5_pinctrl_of_match[] = { -+ { -+ .compatible = "marvell,ac5-pinctrl", -+ }, -+ { }, -+}; -+ -+static const struct mvebu_mpp_ctrl ac5_mpp_controls[] = { -+ MPP_FUNC_CTRL(0, 45, NULL, mvebu_mmio_mpp_ctrl), }; -+ -+static struct pinctrl_gpio_range ac5_mpp_gpio_ranges[] = { -+ MPP_GPIO_RANGE(0, 0, 0, 46), }; -+ -+static int ac5_pinctrl_probe(struct platform_device *pdev) -+{ -+ struct mvebu_pinctrl_soc_info *soc = &ac5_pinctrl_info; -+ -+ soc->variant = 0; /* no variants for ac5 */ -+ soc->controls = ac5_mpp_controls; -+ soc->ncontrols = ARRAY_SIZE(ac5_mpp_controls); -+ soc->gpioranges = ac5_mpp_gpio_ranges; -+ soc->ngpioranges = ARRAY_SIZE(ac5_mpp_gpio_ranges); -+ soc->modes = ac5_mpp_modes; -+ soc->nmodes = ac5_mpp_controls[0].npins; -+ -+ pdev->dev.platform_data = soc; -+ -+ return mvebu_pinctrl_simple_mmio_probe(pdev); -+} -+ -+static struct platform_driver ac5_pinctrl_driver = { -+ .driver = { -+ .name = "ac5-pinctrl", -+ .of_match_table = of_match_ptr(ac5_pinctrl_of_match), -+ }, -+ .probe = ac5_pinctrl_probe, -+}; -+builtin_platform_driver(ac5_pinctrl_driver); --- -2.25.1 - diff --git a/patch/0010-arm64-marvell-Enable-the-98DX2530-pinctrl-driver.patch b/patch/0010-arm64-marvell-Enable-the-98DX2530-pinctrl-driver.patch deleted file mode 100644 index 872b843de..000000000 --- a/patch/0010-arm64-marvell-Enable-the-98DX2530-pinctrl-driver.patch +++ /dev/null @@ -1,36 +0,0 @@ -From: Chris Packham -Date: Tue, 5 Jul 2022 22:09:21 +0300 -arm64: marvell: Enable the 98DX2530 pinctrl driver - -This commit makes sure the drivers for the 98DX2530 pin controller is -enabled. - -Signed-off-by: Chris Packham -Reviewed-by: Andrew Lunn -Signed-off-by: Vadym Kochan -Signed-off-by: Gregory CLEMENT ---- - arch/arm64/Kconfig.platforms | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms -index 889e78f40..02e197936 100644 ---- a/arch/arm64/Kconfig.platforms -+++ b/arch/arm64/Kconfig.platforms -@@ -179,11 +179,13 @@ config ARCH_MVEBU - select PINCTRL_ARMADA_37XX - select PINCTRL_ARMADA_AP806 - select PINCTRL_ARMADA_CP110 -+ select PINCTRL_AC5 - help - This enables support for Marvell EBU familly, including: - - Armada 3700 SoC Family - - Armada 7K SoC Family - - Armada 8K SoC Family -+ - 98DX2530 SoC Family - - config ARCH_MXC - bool "ARMv8 based NXP i.MX SoC family" --- -2.25.1 - diff --git a/patch/0020-dts-marvell-Add-support-for-7020-comexpress.patch b/patch/0010-dts-marvell-Add-support-for-7020-comexpress.patch similarity index 92% rename from patch/0020-dts-marvell-Add-support-for-7020-comexpress.patch rename to patch/0010-dts-marvell-Add-support-for-7020-comexpress.patch index 31ed7f534..22c427f63 100644 --- a/patch/0020-dts-marvell-Add-support-for-7020-comexpress.patch +++ b/patch/0010-dts-marvell-Add-support-for-7020-comexpress.patch @@ -1,8 +1,8 @@ -From: Pavan Naregundi -Date: Tue, 7 Mar 2023 15:18:44 +0000 -dts: marvell: Add support for 7020 comexpress +From: Keshav Gupta +Date: Wed, 4 Oct 2023 06:46:29 +0000 +Subject: [PATCH] dts: marvell: Add support for 7020 comexpress -This change adds device tree file for Marvell Armada 7020 ComExpress +This change adds device tree file for Marvell Armada 7020 ComExpress development board. The Armada 7020(7K family) composed of: @@ -26,12 +26,12 @@ Reviewed-by: Raz Adashi create mode 100644 arch/arm64/boot/dts/marvell/armada-7020-comexpress.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile -index 5e9c34d1e..6873ad448 100644 +index 058237681..49f274add 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile -@@ -17,3 +17,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb - dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb - dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb +@@ -26,3 +26,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-7020-comexpress.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dts b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dts diff --git a/patch/0021-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch b/patch/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch similarity index 89% rename from patch/0021-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch rename to patch/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch index 3f51074e4..e566a286b 100644 --- a/patch/0021-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch +++ b/patch/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch @@ -1,10 +1,9 @@ -From 79de58e232cf5880a8ff68f15091febfc6c8fb3b Mon Sep 17 00:00:00 2001 From: Natarajan Subbiramani -Date: Tue, 13 Jun 2023 17:04:23 +0000 +Date: Tue, 10 Oct 2023 09:31:48 +0000 Subject: [PATCH] arm64: dts: marvell: Add Nokia 7215-IXS-A1 board -This dts is derived from Marvell RD-AC5X board to -create platform specific dts for Nokia 7215-IXS-A1 +This dts is derived from Marvell RD-AC5X board to +create platform specific dts for Nokia 7215-IXS-A1 Signed-off-by: Natarajan Subbiramani Tested-by: Natarajan Subbiramani @@ -130,11 +129,11 @@ index 000000000..8c10c5415 + }; +}; diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile -index 6873ad448..b53edc9b7 100644 +index 49f274add..310b57e47 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile -@@ -18,3 +18,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb - dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb +@@ -27,3 +27,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7020-comexpress.dtb +dtb-$(CONFIG_ARCH_MVEBU) += 7215-ixs-a1.dtb diff --git a/patch/0011-net-mvneta-Add-support-for-98DX2530-Ethernet-port.patch b/patch/0011-net-mvneta-Add-support-for-98DX2530-Ethernet-port.patch deleted file mode 100644 index 16675a0fd..000000000 --- a/patch/0011-net-mvneta-Add-support-for-98DX2530-Ethernet-port.patch +++ /dev/null @@ -1,69 +0,0 @@ -From: Chris Packham -Date: Wed, 16 Mar 2022 10:52:07 +1300 -net: mvneta: Add support for 98DX2530 Ethernet port - -The 98DX2530 SoC is similar to the Armada 3700 except it needs a -different MBUS window configuration. Add a new compatible string to -identify this device and the required MBUS window configuration. - -Signed-off-by: Chris Packham -Reviewed-by: Andrew Lunn -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/marvell/mvneta.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c -index 74e266c0b..81f42ae08 100644 ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -75,6 +75,8 @@ - #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) - #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) - #define MVNETA_BASE_ADDR_ENABLE 0x2290 -+#define MVNETA_AC5_CNM_DDR_TARGET 0x2 -+#define MVNETA_AC5_CNM_DDR_ATTR 0xb - #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 - #define MVNETA_PORT_CONFIG 0x2400 - #define MVNETA_UNI_PROMISC_MODE BIT(0) -@@ -513,6 +515,7 @@ struct mvneta_port { - - /* Flags for special SoC configurations */ - bool neta_armada3700; -+ bool neta_ac5; - u16 rx_offset_correction; - const struct mbus_dram_target_info *dram_target_info; - }; -@@ -5025,6 +5028,10 @@ static void mvneta_conf_mbus_windows(struct mvneta_port *pp, - win_protect |= 3 << (2 * i); - } - } else { -+ if (pp->neta_ac5) -+ mvreg_write(pp, MVNETA_WIN_BASE(0), -+ (MVNETA_AC5_CNM_DDR_ATTR << 8) | -+ MVNETA_AC5_CNM_DDR_TARGET); - /* For Armada3700 open default 4GB Mbus window, leaving - * arbitration of target/attribute to a different layer - * of configuration. -@@ -5123,6 +5130,10 @@ static int mvneta_probe(struct platform_device *pdev) - /* Get special SoC configurations */ - if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) - pp->neta_armada3700 = true; -+ if (of_device_is_compatible(dn, "marvell,armada-ac5-neta")) { -+ pp->neta_armada3700 = true; -+ pp->neta_ac5 = true; -+ } - - pp->clk = devm_clk_get(&pdev->dev, "core"); - if (IS_ERR(pp->clk)) -@@ -5444,6 +5455,7 @@ static const struct of_device_id mvneta_match[] = { - { .compatible = "marvell,armada-370-neta" }, - { .compatible = "marvell,armada-xp-neta" }, - { .compatible = "marvell,armada-3700-neta" }, -+ { .compatible = "marvell,armada-ac5-neta" }, - { } - }; - MODULE_DEVICE_TABLE(of, mvneta_match); --- -2.25.1 - diff --git a/patch/0012-spi-a3700-Support-big-endianness-for-AC5-SPI-driver.patch b/patch/0012-spi-a3700-Support-big-endianness-for-AC5-SPI-driver.patch deleted file mode 100644 index b53e5ac2e..000000000 --- a/patch/0012-spi-a3700-Support-big-endianness-for-AC5-SPI-driver.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: Noam -Date: Tue, 26 Jul 2022 16:00:37 +0300 -spi: a3700: Support big endianness for AC5 SPI driver - -Fix wrong endianness in a3700_spi_fifo_read() and a3700_spi_fifo_write(). - -Signed-off-by: Noam -Tested-by: Raz Adashi -Reviewed-by: Raz Adashi -Signed-off-by: Vadym Kochan -Link: https://lore.kernel.org/r/20220726130038.20995-1-vadym.kochan@plvision.eu -Signed-off-by: Mark Brown ---- - drivers/spi/spi-armada-3700.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c -index d8cc4b270..9df9fc40b 100644 ---- a/drivers/spi/spi-armada-3700.c -+++ b/drivers/spi/spi-armada-3700.c -@@ -497,7 +497,7 @@ static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) - - while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { - val = *(u32 *)a3700_spi->tx_buf; -- spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); -+ spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, cpu_to_le32(val)); - a3700_spi->buf_len -= 4; - a3700_spi->tx_buf += 4; - } -@@ -519,7 +519,7 @@ static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) - while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { - val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); - if (a3700_spi->buf_len >= 4) { -- -+ val = le32_to_cpu(val); - memcpy(a3700_spi->rx_buf, &val, 4); - - a3700_spi->buf_len -= 4; --- -2.25.1 - diff --git a/patch/0013-dt-bindings-ac5-Add-mmc-and-usb-properties.patch b/patch/0013-dt-bindings-ac5-Add-mmc-and-usb-properties.patch deleted file mode 100644 index cbd535907..000000000 --- a/patch/0013-dt-bindings-ac5-Add-mmc-and-usb-properties.patch +++ /dev/null @@ -1,72 +0,0 @@ -From: Pavan Naregundi -Date: Tue, 14 Mar 2023 06:10:59 +0000 -dt-bindings: ac5: Add mmc and usb properties - -Describe compatible string in Marvell Xenon SDHCI Controller for mmc. -Also documents compatible string for ac5 in ehci-orion. - -Signed-off-by: Noam Liron ---- - .../bindings/mmc/marvell,xenon-sdhci.txt | 22 +++++++++++++++++++ - .../devicetree/bindings/usb/ehci-orion.txt | 1 + - 2 files changed, 23 insertions(+) - -diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt -index ed1456f5c..c5a4aebcd 100644 ---- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt -+++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt -@@ -13,6 +13,7 @@ Required Properties: - Must provide a second register area and marvell,pad-type. - - "marvell,armada-ap806-sdhci": For controllers on Armada AP806. - - "marvell,armada-cp110-sdhci": For controllers on Armada CP110. -+ - "marvell,ac5-sdhci": For CnM on AC5, AC5X and derived. - - - clocks: - Array of clocks required for SDHC. -@@ -32,6 +33,9 @@ Required Properties: - in below. - Please also check property marvell,pad-type in below. - -+ * For "marvell,ac5-sdhci", one register area. -+ (reg-names "ctrl"). -+ - * For other compatible strings, one register area for Xenon IP. - - Optional Properties: -@@ -170,3 +174,21 @@ Example: - - marvell,pad-type = "sd"; - }; -+ -+ -+- For eMMC with compatible "marvell,ac5-sdhci": -+ sdhci0: sdhci@805c0000 { -+ compatible = "marvell,ac5-sdhci"; -+ reg = <0x0 0x805c0000>; -+ reg-names = "ctrl"; -+ interrupts = ; -+ clocks = <&core_clock>; -+ clock-names = "core"; -+ status = "okay"; -+ bus-width = <8>; -+ /*marvell,xenon-phy-slow-mode;*/ -+ non-removable; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ }; -diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt -index 2855bae79..83e4d8992 100644 ---- a/Documentation/devicetree/bindings/usb/ehci-orion.txt -+++ b/Documentation/devicetree/bindings/usb/ehci-orion.txt -@@ -4,6 +4,7 @@ Required properties: - - compatible: must be one of the following - "marvell,orion-ehci" - "marvell,armada-3700-ehci" -+ "marvell,ac5-ehci" - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: The EHCI interrupt --- -2.25.1 - diff --git a/patch/0016-ac5-marvell-Add-support-for-emmc.patch b/patch/0016-ac5-marvell-Add-support-for-emmc.patch deleted file mode 100644 index f82df8d5b..000000000 --- a/patch/0016-ac5-marvell-Add-support-for-emmc.patch +++ /dev/null @@ -1,61 +0,0 @@ -From: Pavan Naregundi -Date: Fri, 10 Mar 2023 00:45:47 +0000 -ac5: marvell: Add support for emmc - -This patch adds ac5-sdhci compatible checks in Marvell Xenon SDHCI -Controller for emmc support in 98DX25xx SoC. - -Tested-by: Raz Adashi -Reviewed-by: Raz Adashi -Signed-off-by: Noam Liron ---- - drivers/mmc/host/sdhci-xenon.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c -index d509198c0..1ed5f3171 100644 ---- a/drivers/mmc/host/sdhci-xenon.c -+++ b/drivers/mmc/host/sdhci-xenon.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - - #include "sdhci-pltfm.h" - #include "sdhci-xenon.h" -@@ -411,6 +412,7 @@ static int xenon_probe_dt(struct platform_device *pdev) - struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); - u32 sdhc_id, nr_sdhc; - u32 tuning_count; -+ struct sysinfo si; - - /* Disable HS200 on Armada AP806 */ - if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci")) -@@ -439,6 +441,15 @@ static int xenon_probe_dt(struct platform_device *pdev) - } - priv->tuning_count = tuning_count; - -+ si_meminfo(&si); -+ -+ if (of_device_is_compatible(np, "marvell,ac5-sdhci") && -+ ((si.totalram * si.mem_unit) > 0x80000000 /*2G*/)) { -+ host->quirks |= SDHCI_QUIRK_BROKEN_DMA; -+ host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; -+ dev_info(mmc_dev(mmc), "Disabling DMA because of 2GB DMA access limit.\n"); -+ } -+ - return xenon_phy_parse_dt(np, host); - } - -@@ -665,6 +676,7 @@ static const struct of_device_id sdhci_xenon_dt_ids[] = { - { .compatible = "marvell,armada-ap806-sdhci",}, - { .compatible = "marvell,armada-cp110-sdhci",}, - { .compatible = "marvell,armada-3700-sdhci",}, -+ { .compatible = "marvell,ac5-sdhci",}, - {} - }; - MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids); --- -2.25.1 - diff --git a/patch/series b/patch/series index bcede89c6..bae31c662 100755 --- a/patch/series +++ b/patch/series @@ -200,29 +200,18 @@ cisco-npu-disable-other-bars.patch 0003-psample-define-the-macro-PSAMPLE_MD_EXTENDED_ATTR.patch # -# Marvell platform patches for 5.10 -armhf_secondary_boot_online.patch -#0001-dt-bindings-marvell-Document-the-AC5-AC5X-compatible.patch # Upstreamed -#0002-dt-bindings-net-mvneta-Add-marvell-armada-ac5-neta.patch # Upstreamed -#0003-arm64-dts-marvell-Add-Armada-98DX2530-SoC-and-RD-AC5.patch # Upstreamed -#0004-arm64-dts-marvell-Add-UART1-3-for-AC5-AC5X.patch # Upstreamed -#0005-arm64-dts-marvell-98dx25xx-Fix-i2c-gpios-property.patch # Upstreamed -0006-arm64-dts-Update-cache-properties-for-marvell.patch -#0007-arm64-dts-marvell-AC5-AC5X-Fix-address-for-UART1.patch # Upstreamed -#0008-mtd-rawnand-marvell-Add-missing-layouts.patch # Upstreamed -#0009-pinctrl-mvebu-Add-driver-for-98DX2530-SoC.patch # Upstreamed -#0010-arm64-marvell-Enable-the-98DX2530-pinctrl-driver.patch # Upstreamed -#0011-net-mvneta-Add-support-for-98DX2530-Ethernet-port.patch # Upstreamed -#0012-spi-a3700-Support-big-endianness-for-AC5-SPI-driver.patch # Upstreamed -#0013-dt-bindings-ac5-Add-mmc-and-usb-properties.patch # TODO -0014-dts-ac5-marvell-Add-switching-mmc-watchdog-node.patch -0015-ac5-marvell-Add-watchdog-support.patch -#0016-ac5-marvell-Add-support-for-emmc.patch # TODO -0017-usb-ehci-Add-support-for-ac5.patch -#0018-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch # TODO -0019-dt-bindings-marvell-Add-ARMADA-7K-properties.patch -#0020-dts-marvell-Add-support-for-7020-comexpress.patch # TODO -#0021-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch # TODO +# Marvell platform patches for 6.1 kernel +0001-armhf_secondary_boot_online.patch +0002-arm64-dts-Update-cache-properties-for-marvell.patch +0003-dt-bindings-ac5-Add-mmc-and-usb-properties.patch +0004-dts-ac5-marvell-Add-switching-mmc-watchdog-node.patch +0005-ac5-marvell-Add-watchdog-support.patch +0006-ac5-marvell-Add-support-for-emmc.patch +0007-usb-ehci-Add-support-for-ac5.patch +0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch +0009-dt-bindings-marvell-Add-ARMADA-7K-properties.patch +0010-dts-marvell-Add-support-for-7020-comexpress.patch +0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch # amd-pensando elba support # TODO