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Merge pull request #60 from siliconcompiler/diff_io
Adding bidirectional IO cells
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‎lambdalib/iolib/rtl/la_iorxdiff.v‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
/*****************************************************************************
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* Function: IO differential receiver
3+
* Copyright: Lambda Project Authors. All rights Reserved.
4+
* License: MIT (see LICENSE file in Lambda repository)
5+
*
6+
* Docs:
7+
*
8+
* This is a generic cell that defines the standard interface of the lambda
9+
* differential IO receiver cell. It is only suitable for FPGA synthesis.
10+
*
11+
* ASIC specific libraries will need to use the TYPE field to select an
12+
* appropriate hardcoded physical cell based on the the process constraints
13+
* and library composition. For example, modern nodes will usually have
14+
* different IP cells for placing cells vertically or horizontally.
15+
*
16+
****************************************************************************/
17+
module la_iorxdiff
18+
#(
19+
parameter TYPE = "DEFAULT", // cell type
20+
parameter SIDE = "NO", // "NO", "SO", "EA", "WE"
21+
parameter CFGW = 16, // width of core config bus
22+
parameter RINGW = 8 // width of io ring
23+
)
24+
(// io pad signals
25+
inout padp, // differential pad input (positive)
26+
inout padn, // differential pad input (negative)
27+
inout vdd, // core supply
28+
inout vss, // core ground
29+
inout vddio, // io supply
30+
inout vssio, // io ground
31+
// core facing signals
32+
output zp, // digital output to core (positive)
33+
output zn, // digital output to core (negative)
34+
input ie, // input enable, 1 = active
35+
inout [RINGW-1:0] ioring, // generic io-ring interface
36+
input [ CFGW-1:0] cfg // generic config interface
37+
);
38+
39+
// gated differential non inverting buffer
40+
assign zp = padp & ~padn & ie;
41+
42+
// driving pseudo differential digital signal to core
43+
assign zn = ~zp;
44+
45+
endmodule

‎lambdalib/iolib/rtl/la_iotxdiff.v‎

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@@ -0,0 +1,42 @@
1+
/*****************************************************************************
2+
* Function: IO bi-directional transmitter
3+
* Copyright: Lambda Project Authors. All rights Reserved.
4+
* License: MIT (see LICENSE file in Lambda repository)
5+
*
6+
* Docs:
7+
*
8+
* This is a generic cell that defines the standard interface of the lambda
9+
* differential IO transmit cell. It is not generally synthesizable.
10+
*
11+
* ASIC specific libraries will need to use the TYPE field to select an
12+
* appropriate hardcoded physical cell based on the the process constraints
13+
* and library composition. For example, modern nodes will usually have
14+
* different IP cells for placing cells vertically or horizontally.
15+
*
16+
****************************************************************************/
17+
module la_iotxdiff
18+
#(
19+
parameter TYPE = "DEFAULT", // cell type
20+
parameter SIDE = "NO", // "NO", "SO", "EA", "WE"
21+
parameter CFGW = 16, // width of core config bus
22+
parameter RINGW = 8 // width of io ring
23+
)
24+
(// io pad signals
25+
inout padp, // differential pad output (positive)
26+
inout padn, // differential pad output (negative)
27+
inout vdd, // core supply
28+
inout vss, // core ground
29+
inout vddio, // io supply
30+
inout vssio, // io ground
31+
// core facing signals
32+
input a, // input from core
33+
input oe, // output enable, 1 = active
34+
inout [RINGW-1:0] ioring, // generic io-ring interface
35+
input [ CFGW-1:0] cfg // generic config interface
36+
);
37+
38+
// output driver with tr
39+
assign padp = oe ? a : 1'bz;
40+
assign padn = oe ? ~a : 1'bz;
41+
42+
endmodule

‎lambdalib/padring/rtl/la_iopadring.v‎

Lines changed: 122 additions & 117 deletions
Original file line numberDiff line numberDiff line change
@@ -43,55 +43,59 @@ module la_iopadring #( // global settings
4343
parameter WE_NSECTIONS = 1,
4444
parameter WE_CELLMAP = 0
4545
) ( // CONTINUOUS GROUND
46-
inout vss,
46+
inout vss,
4747
// NORTH
48-
inout [ NO_NPINS-1:0] no_pad, // pad
49-
inout [ NO_NPINS*3-1:0] no_aio, // analog inout
50-
output [ NO_NPINS-1:0] no_z, // output to core
51-
input [ NO_NPINS-1:0] no_a, // input from core
52-
input [ NO_NPINS-1:0] no_ie, // input enable, 1 = active
53-
input [ NO_NPINS-1:0] no_oe, // output enable, 1 = active
54-
input [ NO_NPINS*CFGW-1:0] no_cfg, // generic config interface
55-
inout [ NO_NSECTIONS-1:0] no_vdd, // core supply
56-
inout [ NO_NSECTIONS-1:0] no_vddio, // io/analog supply
57-
inout [ NO_NSECTIONS-1:0] no_vssio, // io/analog ground
58-
inout [NO_NSECTIONS*RINGW-1:0] no_ioring, // io ring
48+
inout [ NO_NPINS-1:0] no_pad, // pad
49+
inout [ NO_NPINS*3-1:0] no_aio, // analog inout
50+
output [ NO_NPINS-1:0] no_zp, // output to core (positive)
51+
output [ NO_NPINS-1:0] no_zn, // output to core (negative)
52+
input [ NO_NPINS-1:0] no_a, // input from core
53+
input [ NO_NPINS-1:0] no_ie, // input enable, 1 = active
54+
input [ NO_NPINS-1:0] no_oe, // output enable, 1 = active
55+
input [ NO_NPINS*CFGW-1:0] no_cfg, // generic config interface
56+
inout [ NO_NSECTIONS-1:0] no_vdd, // core supply
57+
inout [ NO_NSECTIONS-1:0] no_vddio, // io/analog supply
58+
inout [ NO_NSECTIONS-1:0] no_vssio, // io/analog ground
59+
inout [NO_NSECTIONS*RINGW-1:0] no_ioring, // io ring
5960
// EAST
60-
inout [ EA_NPINS-1:0] ea_pad,
61-
inout [ EA_NPINS*3-1:0] ea_aio,
62-
output [ EA_NPINS-1:0] ea_z,
63-
input [ EA_NPINS-1:0] ea_a,
64-
input [ EA_NPINS-1:0] ea_ie,
65-
input [ EA_NPINS-1:0] ea_oe,
66-
input [ EA_NPINS*CFGW-1:0] ea_cfg,
67-
inout [ EA_NSECTIONS-1:0] ea_vdd,
68-
inout [ EA_NSECTIONS-1:0] ea_vddio,
69-
inout [ EA_NSECTIONS-1:0] ea_vssio,
70-
inout [EA_NSECTIONS*RINGW-1:0] ea_ioring,
61+
inout [ EA_NPINS-1:0] ea_pad,
62+
inout [ EA_NPINS*3-1:0] ea_aio,
63+
output [ EA_NPINS-1:0] ea_zp,
64+
output [ EA_NPINS-1:0] ea_zn,
65+
input [ EA_NPINS-1:0] ea_a,
66+
input [ EA_NPINS-1:0] ea_ie,
67+
input [ EA_NPINS-1:0] ea_oe,
68+
input [ EA_NPINS*CFGW-1:0] ea_cfg,
69+
inout [ EA_NSECTIONS-1:0] ea_vdd,
70+
inout [ EA_NSECTIONS-1:0] ea_vddio,
71+
inout [ EA_NSECTIONS-1:0] ea_vssio,
72+
inout [EA_NSECTIONS*RINGW-1:0] ea_ioring,
7173
// SOUTH
72-
inout [ SO_NPINS-1:0] so_pad, // pad
73-
inout [ SO_NPINS*3-1:0] so_aio, // analog inout
74-
output [ SO_NPINS-1:0] so_z, // output to core
75-
input [ SO_NPINS-1:0] so_a, // input from core
76-
input [ SO_NPINS-1:0] so_ie, // input enable, 1 = active
77-
input [ SO_NPINS-1:0] so_oe, // output enable, 1 = active
78-
input [ SO_NPINS*CFGW-1:0] so_cfg, // generic config interface
79-
inout [ SO_NSECTIONS-1:0] so_vdd, // core supply
80-
inout [ SO_NSECTIONS-1:0] so_vddio, // io supply
81-
inout [ SO_NSECTIONS-1:0] so_vssio, // io ground
82-
inout [SO_NSECTIONS*RINGW-1:0] so_ioring, // io ring
74+
inout [ SO_NPINS-1:0] so_pad,
75+
inout [ SO_NPINS*3-1:0] so_aio,
76+
output [ SO_NPINS-1:0] so_zp,
77+
output [ SO_NPINS-1:0] so_zn,
78+
input [ SO_NPINS-1:0] so_a,
79+
input [ SO_NPINS-1:0] so_ie,
80+
input [ SO_NPINS-1:0] so_oe,
81+
input [ SO_NPINS*CFGW-1:0] so_cfg,
82+
inout [ SO_NSECTIONS-1:0] so_vdd,
83+
inout [ SO_NSECTIONS-1:0] so_vddio,
84+
inout [ SO_NSECTIONS-1:0] so_vssio,
85+
inout [SO_NSECTIONS*RINGW-1:0] so_ioring,
8386
// WEST
84-
inout [ WE_NPINS-1:0] we_pad,
85-
inout [ WE_NPINS*3-1:0] we_aio,
86-
output [ WE_NPINS-1:0] we_z,
87-
input [ WE_NPINS-1:0] we_a,
88-
input [ WE_NPINS-1:0] we_ie,
89-
input [ WE_NPINS-1:0] we_oe,
90-
input [ WE_NPINS*CFGW-1:0] we_cfg,
91-
inout [ WE_NSECTIONS-1:0] we_vdd,
92-
inout [ WE_NSECTIONS-1:0] we_vddio,
93-
inout [ WE_NSECTIONS-1:0] we_vssio,
94-
inout [WE_NSECTIONS*RINGW-1:0] we_ioring
87+
inout [ WE_NPINS-1:0] we_pad,
88+
inout [ WE_NPINS*3-1:0] we_aio,
89+
output [ WE_NPINS-1:0] we_zp,
90+
output [ WE_NPINS-1:0] we_zn,
91+
input [ WE_NPINS-1:0] we_a,
92+
input [ WE_NPINS-1:0] we_ie,
93+
input [ WE_NPINS-1:0] we_oe,
94+
input [ WE_NPINS*CFGW-1:0] we_cfg,
95+
inout [ WE_NSECTIONS-1:0] we_vdd,
96+
inout [ WE_NSECTIONS-1:0] we_vddio,
97+
inout [ WE_NSECTIONS-1:0] we_vssio,
98+
inout [WE_NSECTIONS*RINGW-1:0] we_ioring
9599
);
96100

97101
`include "la_iopadring.vh"
@@ -120,24 +124,25 @@ module la_iopadring #( // global settings
120124
.NSECTIONS(NO_NSECTIONS),
121125
.CELLMAP(NO_CELLMAP),
122126
.RINGW(RINGW),
123-
.CFGW(CFGW)
124-
) inorth ( /*AUTOINST*/
125-
// Outputs
126-
.z (no_z), // Templated
127-
// Inouts
128-
.pad (no_pad), // Templated
129-
.aio (no_aio), // Templated
130-
.vss (vss), // Templated
131-
.vdd (no_vdd), // Templated
132-
.vddio (no_vddio), // Templated
133-
.vssio (no_vssio), // Templated
134-
.ioring(no_ioring), // Templated
135-
// Inputs
136-
.a (no_a), // Templated
137-
.ie (no_ie), // Templated
138-
.oe (no_oe), // Templated
139-
.cfg (no_cfg)
140-
); // Templated
127+
.CFGW(CFGW))
128+
inorth (
129+
/*AUTOINST*/
130+
// Outputs
131+
.zp (no_zp), // Templated
132+
.zn (no_zn), // Templated
133+
// Inouts
134+
.pad (no_pad), // Templated
135+
.aio (no_aio), // Templated
136+
.vss (vss), // Templated
137+
.vdd (no_vdd), // Templated
138+
.vddio (no_vddio), // Templated
139+
.vssio (no_vssio), // Templated
140+
.ioring (no_ioring), // Templated
141+
// Inputs
142+
.a (no_a), // Templated
143+
.ie (no_ie), // Templated
144+
.oe (no_oe), // Templated
145+
.cfg (no_cfg)); // Templated
141146

142147
//#####################
143148
// EAST
@@ -149,24 +154,24 @@ module la_iopadring #( // global settings
149154
.NSECTIONS(EA_NSECTIONS),
150155
.CELLMAP(EA_CELLMAP),
151156
.RINGW(RINGW),
152-
.CFGW(CFGW)
153-
) ieast ( /*AUTOINST*/
154-
// Outputs
155-
.z (ea_z), // Templated
156-
// Inouts
157-
.pad (ea_pad), // Templated
158-
.aio (ea_aio), // Templated
159-
.vss (vss), // Templated
160-
.vdd (ea_vdd), // Templated
161-
.vddio (ea_vddio), // Templated
162-
.vssio (ea_vssio), // Templated
163-
.ioring(ea_ioring), // Templated
164-
// Inputs
165-
.a (ea_a), // Templated
166-
.ie (ea_ie), // Templated
167-
.oe (ea_oe), // Templated
168-
.cfg (ea_cfg)
169-
); // Templated
157+
.CFGW(CFGW))
158+
ieast (/*AUTOINST*/
159+
// Outputs
160+
.zp (ea_zp), // Templated
161+
.zn (ea_zn), // Templated
162+
// Inouts
163+
.pad (ea_pad), // Templated
164+
.aio (ea_aio), // Templated
165+
.vss (vss), // Templated
166+
.vdd (ea_vdd), // Templated
167+
.vddio (ea_vddio), // Templated
168+
.vssio (ea_vssio), // Templated
169+
.ioring (ea_ioring), // Templated
170+
// Inputs
171+
.a (ea_a), // Templated
172+
.ie (ea_ie), // Templated
173+
.oe (ea_oe), // Templated
174+
.cfg (ea_cfg)); // Templated
170175

171176
//#####################
172177
// SOUTH
@@ -179,24 +184,24 @@ module la_iopadring #( // global settings
179184
.NSECTIONS(SO_NSECTIONS),
180185
.CELLMAP(SO_CELLMAP),
181186
.RINGW(RINGW),
182-
.CFGW(CFGW)
183-
) isouth ( /*AUTOINST*/
184-
// Outputs
185-
.z (so_z), // Templated
186-
// Inouts
187-
.pad (so_pad), // Templated
188-
.aio (so_aio), // Templated
189-
.vss (vss), // Templated
190-
.vdd (so_vdd), // Templated
191-
.vddio (so_vddio), // Templated
192-
.vssio (so_vssio), // Templated
193-
.ioring(so_ioring), // Templated
194-
// Inputs
195-
.a (so_a), // Templated
196-
.ie (so_ie), // Templated
197-
.oe (so_oe), // Templated
198-
.cfg (so_cfg)
199-
); // Templated
187+
.CFGW(CFGW))
188+
isouth (/*AUTOINST*/
189+
// Outputs
190+
.zp (so_zp), // Templated
191+
.zn (so_zn), // Templated
192+
// Inouts
193+
.pad (so_pad), // Templated
194+
.aio (so_aio), // Templated
195+
.vss (vss), // Templated
196+
.vdd (so_vdd), // Templated
197+
.vddio (so_vddio), // Templated
198+
.vssio (so_vssio), // Templated
199+
.ioring (so_ioring), // Templated
200+
// Inputs
201+
.a (so_a), // Templated
202+
.ie (so_ie), // Templated
203+
.oe (so_oe), // Templated
204+
.cfg (so_cfg)); // Templated
200205

201206
//#####################
202207
// WEST
@@ -209,24 +214,24 @@ module la_iopadring #( // global settings
209214
.NSECTIONS(WE_NSECTIONS),
210215
.CELLMAP(WE_CELLMAP),
211216
.RINGW(RINGW),
212-
.CFGW(CFGW)
213-
) iwest ( /*AUTOINST*/
214-
// Outputs
215-
.z (we_z), // Templated
216-
// Inouts
217-
.pad (we_pad), // Templated
218-
.aio (we_aio), // Templated
219-
.vss (vss), // Templated
220-
.vdd (we_vdd), // Templated
221-
.vddio (we_vddio), // Templated
222-
.vssio (we_vssio), // Templated
223-
.ioring(we_ioring), // Templated
224-
// Inputs
225-
.a (we_a), // Templated
226-
.ie (we_ie), // Templated
227-
.oe (we_oe), // Templated
228-
.cfg (we_cfg)
229-
); // Templated
217+
.CFGW(CFGW))
218+
iwest (/*AUTOINST*/
219+
// Outputs
220+
.zp (we_zp), // Templated
221+
.zn (we_zn), // Templated
222+
// Inouts
223+
.pad (we_pad), // Templated
224+
.aio (we_aio), // Templated
225+
.vss (vss), // Templated
226+
.vdd (we_vdd), // Templated
227+
.vddio (we_vddio), // Templated
228+
.vssio (we_vssio), // Templated
229+
.ioring (we_ioring), // Templated
230+
// Inputs
231+
.a (we_a), // Templated
232+
.ie (we_ie), // Templated
233+
.oe (we_oe), // Templated
234+
.cfg (we_cfg)); // Templated
230235

231236

232237
endmodule // la_iopadring

‎lambdalib/padring/rtl/la_iopadring.vh‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,8 @@ localparam LA_BIDIR = 8'h00;
88
localparam LA_INPUT = 8'h01;
99
localparam LA_ANALOG = 8'h02;
1010
localparam LA_XTAL = 8'h03;
11+
localparam LA_RXDIFF = 8'h04;
12+
localparam LA_TXDIFF = 8'h05;
1113
localparam LA_VDDIO = 8'h08;
1214
localparam LA_VSSIO = 8'h09;
1315
localparam LA_VDD = 8'h0A;

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