File tree Expand file tree Collapse file tree 5 files changed +12
-1
lines changed Expand file tree Collapse file tree 5 files changed +12
-1
lines changed Original file line number Diff line number Diff line change 11from siliconcompiler import Library
22from lambdalib ._common import register_data_source
3+ from lambdalib import stdlib
34
45
56########################
@@ -15,4 +16,6 @@ def setup(chip):
1516
1617 lib .add ('option' , 'ydir' , "lambdalib/auxlib/rtl" )
1718
19+ lib .use (stdlib )
20+
1821 return lib
Original file line number Diff line number Diff line change 11from siliconcompiler import Library
22from lambdalib ._common import register_data_source
3+ from lambdalib import iolib
34
45
56########################
@@ -16,4 +17,6 @@ def setup(chip):
1617 lib .add ('option' , 'idir' , "lambdalib/padring/rtl" )
1718 lib .add ('option' , 'ydir' , "lambdalib/padring/rtl" )
1819
20+ lib .use (iolib )
21+
1922 return lib
Original file line number Diff line number Diff line change 11from siliconcompiler import Library
22from lambdalib ._common import register_data_source
3+ from lambdalib import auxlib
34
45
56########################
@@ -15,4 +16,6 @@ def setup(chip):
1516
1617 lib .add ('option' , 'ydir' , "lambdalib/ramlib/rtl" )
1718
19+ lib .use (auxlib )
20+
1821 return lib
Original file line number Diff line number Diff line change 11from siliconcompiler import Library
22from lambdalib ._common import register_data_source
3+ from lambdalib import stdlib
34
45
56########################
@@ -15,4 +16,6 @@ def setup(chip):
1516
1617 lib .add ('option' , 'ydir' , "lambdalib/vectorlib/rtl" )
1718
19+ lib .use (stdlib )
20+
1821 return lib
Original file line number Diff line number Diff line change 11import pytest
22from siliconcompiler import Chip
33
4- import lambdalib
54from lambdalib import \
65 auxlib , \
76 fpgalib , \
You can’t perform that action at this time.
0 commit comments