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1 | 1 | /***************************************************************************** |
2 | | - * Function: IO differential receiver |
| 2 | + * Function: Digital Differential Receiver IO Cell |
3 | 3 | * Copyright: Lambda Project Authors. All rights Reserved. |
4 | 4 | * License: MIT (see LICENSE file in Lambda repository) |
5 | 5 | * |
6 | 6 | * Docs: |
7 | 7 | * |
8 | | - * This is a generic cell that defines the standard interface of the lambda |
9 | | - * differential IO receiver cell. It is only suitable for FPGA synthesis. |
10 | | - * |
11 | | - * ASIC specific libraries will need to use the TYPE field to select an |
12 | | - * appropriate hardcoded physical cell based on the the process constraints |
13 | | - * and library composition. For example, modern nodes will usually have |
14 | | - * different IP cells for placing cells vertically or horizontally. |
| 8 | + * ../README.md |
15 | 9 | * |
16 | 10 | ****************************************************************************/ |
17 | 11 | module la_iorxdiff |
18 | 12 | #( |
19 | | - parameter TYPE = "DEFAULT", // cell type |
20 | | - parameter SIDE = "NO", // "NO", "SO", "EA", "WE" |
21 | | - parameter CFGW = 16, // width of core config bus |
22 | | - parameter RINGW = 8 // width of io ring |
| 13 | + parameter PROP = "DEFAULT", // cell property |
| 14 | + parameter SIDE = "NO", // "NO", "SO", "EA", "WE" |
| 15 | + parameter CFGW = 16, // width of core config bus |
| 16 | + parameter RINGW = 8 // width of io ring |
23 | 17 | ) |
24 | 18 | (// io pad signals |
25 | | - inout padp, // differential pad input (positive) |
26 | | - inout padn, // differential pad input (negative) |
27 | | - inout vdd, // core supply |
28 | | - inout vss, // core ground |
29 | | - inout vddio, // io supply |
30 | | - inout vssio, // io ground |
| 19 | + inout padp, // differential pad input (positive) |
| 20 | + inout padn, // differential pad input (negative) |
| 21 | + inout vdd, // core supply |
| 22 | + inout vss, // core ground |
| 23 | + inout vddio, // io supply |
| 24 | + inout vssio, // io ground |
31 | 25 | // core facing signals |
32 | | - output zp, // digital output to core (positive) |
33 | | - output zn, // digital output to core (negative) |
34 | | - input ie, // input enable, 1 = active |
35 | | - inout [RINGW-1:0] ioring, // generic io-ring interface |
36 | | - input [ CFGW-1:0] cfg // generic config interface |
| 26 | + output zp, // digital output to core (positive) |
| 27 | + output zn, // digital output to core (negative) |
| 28 | + input ie, // input enable, 1 = active |
| 29 | + inout [RINGW-1:0] ioring, // generic ioring interface |
| 30 | + input [CFGW-1:0] cfg // generic config interface |
37 | 31 | ); |
38 | 32 |
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39 | 33 | // gated differential non inverting buffer |
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