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Merge pull request #104 from siliconcompiler/filesets
Updating lambdalib for new SC design API
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‎.flake8‎

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[flake8]
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max-line-length = 100
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extend-exclude = build,.venv
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extend-ignore =
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extend-ignore =
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per-file-ignores =
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lambdalib/__init__.py:F401

‎.gitignore‎

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#Editor files
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*~
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*~
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.vscod
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#Env
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venv/
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.venv
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# Sim
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*.log
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tmp*
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a.out
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*.vcd
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.venv/
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a.out
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*.vvp
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*.f
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# Byte-compiled / optimized / DLL files
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__pycache__/

‎README.md‎

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# Lambdalib Introduction
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Lambdalib is a modular hardware abstraction library which decouples design from the underlying manufacturing target. Lambdalib defines a set of generic functions that get resolved during the target technology mapping stage.
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Lambdalib is a modular hardware abstraction library which decouples design from the manufacturing target. The project was inspired by the `Lambda` concept invented during the [1978 VLSI revolution by Mead and Conway](https://en.wikipedia.org/wiki/Mead%E2%80%93Conway_VLSI_chip_design_revolution).
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Lambdalib includes the following hardware categories:
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The original single value Lambda approach no longer applies to modern CMOS manufacturing, so Lambdalib has raised the abstraction level to the cell/block level to enable automated porting between compilation targets.
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Lambdalib abstracts away technology specific design modules that cannot be cleanly expressed in technology agnostic RTL Verilog code (eg. synchronizers, analog circuits, io cells, etc.)
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The table below summarizes the categories of cells available.
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| Category | Description |
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|-------------------------------------|---------------------------------------|
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|[stdlib](lambdalib/stdlib/rtl) | Standard cells (inv, nand, ff, ...)
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|[auxlib](lambdalib/auxlib/rtl) | Aux cells can consist of multiple standard cells or physical only cells
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|[auxlib](lambdalib/auxlib/rtl) | Special cells (antenna, decap, clkmux,...)
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|[ramlib](lambdalib/ramlib/rtl) | Memory (single port, dual port, fifo, ...)
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|[iolib](lambdalib/iolib) | IO cells (bidir, vdd, clamp,...)
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|[padring](lambdalib/padring) | Padring generator
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|[vectorlib](lambdalib/vectorlib/rtl) | Vectorized library (mux, isolation)
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|[veclib](lambdalib/veclib/rtl) | Vectorized datapath cells (mux, buf,..)
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|[fpgalib](lambdalib/fpgalib/rtl) | FPGA cells (lut4, ble, clb)
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The [Lambdapdk](https://github.com/siliconcompiler/lambdapdk) repository demonstrates implementation of the Lambdalib interfaces across a number of open source process technologies.
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Lambdalib has been successfully used in multiple tapeouts using [SiliconCompiler](https://github.com/siliconcompiler/siliconcompiler).
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# Installation
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```bash
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git clone https://github.com/zeroasiccorp/lambdalib
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cd lambdalib
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pip install --upgrade pip
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pip install -e .
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```
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# Examples
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## Instantiating a Lambdalib module
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This example shows how to instantiate the Padring module in a top level chip design.
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We could have chosen any module to instantiate (inverter, flip flop, dual port ram...).
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```python
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```
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To convert the design into a gate level netlist using yosys, just run python script
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in the examples folder. A file `chip.vg` will be written to disk in the run directory.
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```bash
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$ python examples/padring/make.py
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```
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## Using SiliconCompiler to target a technology
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```python
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```
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# Project Methodology
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- One verilog module per RTL file
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- One Python module per reusable module
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- Class names are RTL module names with "la_" removed and capitalized
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# License
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[MIT](LICENSE)

‎examples/chip/chip.py‎

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import subprocess
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from siliconcompiler import DesignSchema
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from lambdalib.padring import Padring
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class Chip(DesignSchema):
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def __init__(self):
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name = 'chip'
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super().__init__(name)
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fileset = 'rtl'
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dataroot = f'{name}'
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topmodule = name
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self.set_dataroot(dataroot, __file__)
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self.set_topmodule(topmodule, fileset)
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self.add_file("rtl/chip.v", fileset, dataroot=dataroot)
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self.add_idir('rtl', fileset, dataroot=dataroot)
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# dependencies
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self.add_depfileset(Padring(), depfileset='rtl', fileset='rtl')
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if __name__ == "__main__":
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d = Chip()
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d.write_fileset(f"{d.name}.f", fileset="rtl")
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cmd = ['yosys', '-f', f"{d.name}.f"]
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subprocess.run(cmd, stderr=subprocess.STDOUT, check=True)

‎examples/chip/rtl/chip.v‎

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module chip #(parameter NO_NPINS = 16,
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parameter EA_NPINS = 16,
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parameter WE_NPINS = 16,
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parameter SO_NPINS = 16)
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(
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input VSS,
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input VDD,
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input NVCC,
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input EVCC,
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input WVCC,
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input SVCC,
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inout [NO_NPINS-1:0] NIO,
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inout [EA_NPINS-1:0] EIO,
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inout [WE_NPINS-1:0] WIO,
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inout [SO_NPINS-1:0] SIO
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);
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`include "chip_iomap.vh"
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wire [NO_NSECTIONS*RINGW-1:0] no_ioring;
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wire [EA_NSECTIONS*RINGW-1:0] ea_ioring;
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wire [WE_NSECTIONS*RINGW-1:0] we_ioring;
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wire [SO_NSECTIONS*RINGW-1:0] so_ioring;
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wire [NO_NPINS-1:0] no_rxd;
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wire [EA_NPINS-1:0] ea_rxd;
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wire [WE_NPINS-1:0] we_rxd;
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wire [SO_NPINS-1:0] so_rxd;
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la_padring #(// padring ctrl widths
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.RINGW(RINGW),
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.CFGW(CFGW),
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//north
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.NO_NPINS(NO_NPINS),
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.NO_NCELLS(NO_NCELLS),
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.NO_NSECTIONS(NO_NSECTIONS),
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.NO_CELLMAP(NO_CELLMAP),
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//east
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.EA_NPINS(EA_NPINS),
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.EA_NCELLS(EA_NCELLS),
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.EA_NSECTIONS(EA_NSECTIONS),
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.EA_CELLMAP(EA_CELLMAP),
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//south
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.SO_NPINS(SO_NPINS),
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.SO_NCELLS(SO_NCELLS),
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.SO_NSECTIONS(SO_NSECTIONS),
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.SO_CELLMAP(SO_CELLMAP),
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//west
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.WE_NPINS(WE_NPINS),
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.WE_NCELLS(WE_NCELLS),
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.WE_NSECTIONS(WE_NSECTIONS),
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.WE_CELLMAP(WE_CELLMAP))
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la_padring(// Outputs
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.no_zp (no_rxd[NO_NPINS-1:0]),
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.no_zn (),
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.ea_zp (ea_rxd[EA_NPINS-1:0]),
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.ea_zn (),
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.so_zp (so_rxd[SO_NPINS-1:0]),
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.so_zn (),
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.we_zp (we_rxd[WE_NPINS-1:0]),
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.we_zn (),
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// Inouts
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.vss (VSS),
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.no_pad (NIO),
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.no_aio (),
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.no_vdd (VDD),
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.no_vddio (NVCC),
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.no_vssio (VSS),
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.no_ioring (no_ioring[NO_NSECTIONS*RINGW-1:0]),
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.ea_pad (EIO),
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.ea_aio (),
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.ea_vdd (VDD),
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.ea_vddio (EVCC),
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.ea_vssio (VSS),
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.ea_ioring (ea_ioring[EA_NSECTIONS*RINGW-1:0]),
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.so_pad (SIO),
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.so_aio (),
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.so_vdd (VDD),
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.so_vddio (SVCC),
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.so_vssio (VSS),
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.so_ioring (so_ioring[SO_NSECTIONS*RINGW-1:0]),
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.we_pad (WIO),
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.we_aio (),
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.we_vdd (VDD),
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.we_vddio (WVCC),
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.we_vssio (VSS),
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.we_ioring (we_ioring[WE_NSECTIONS*RINGW-1:0]),
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// Inputs
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.no_a ({NO_NPINS{1'b0}}),
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.no_ie ({NO_NPINS{1'b1}}),
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.no_oe ({NO_NPINS{1'b0}}),
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.no_pe ({NO_NPINS{1'b0}}),
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.no_ps ({NO_NPINS{1'b0}}),
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.no_cfg ({(NO_NPINS*CFGW){1'b0}}),
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.ea_a ({EA_NPINS{1'b0}}),
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.ea_ie ({EA_NPINS{1'b1}}),
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.ea_oe ({EA_NPINS{1'b0}}),
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.ea_pe ({EA_NPINS{1'b0}}),
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.ea_ps ({EA_NPINS{1'b0}}),
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.ea_cfg ({(EA_NPINS*CFGW){1'b0}}),
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.we_a ({WE_NPINS{1'b0}}),
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.we_ie ({WE_NPINS{1'b1}}),
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.we_oe ({WE_NPINS{1'b0}}),
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.we_pe ({WE_NPINS{1'b0}}),
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.we_ps ({WE_NPINS{1'b0}}),
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.we_cfg ({(WE_NPINS*CFGW){1'b0}}),
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.so_a ({SO_NPINS{1'b0}}),
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.so_ie ({SO_NPINS{1'b1}}),
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.so_oe ({SO_NPINS{1'b0}}),
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.so_pe ({SO_NPINS{1'b0}}),
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.so_ps ({SO_NPINS{1'b0}}),
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.so_cfg ({(SO_NPINS*CFGW){1'b0}})
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);
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endmodule

‎examples/chip/rtl/chip_iomap.vh‎

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//########################################################################
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// Common Padring Definitions
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//########################################################################
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`include "la_padring.vh"
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//########################################################################
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// Total number of IO cells in one padring side (including power)
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//########################################################################
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// 16 bidirs
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// 12 power ground
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// 2 cut cells
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// 1 poc
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localparam NCELLS = 31;
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//########################################################################
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// Power sections per side
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//########################################################################
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localparam NSECTIONS = 1;
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//########################################################################
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// Tech specific iolib parameters
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//########################################################################
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// total width of config bus (drive strength, schmitt, ...)
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localparam CFGW = 6;
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// width of bus that goes around ioring
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localparam RINGW = 6;
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//########################################################################
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// CELLMAP[NCELLS*40-1:0] = {PROP, SECTION, CELL, CPIN#, PIN#}
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//########################################################################
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/* The CELLMAP vector specifies the type, order, power rail, and pin
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* connection for each cell placed in a side of the io padring.
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*
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* CELLMAP is used by la_padside which iterates from 0 to NCELLS-1 to
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* instantiate padring cells. The index for that for loop is used
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* to find the power section, pin number, and cell type in the
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* static definition below. The indices of the cells are specified from
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* left to right or top to bottom. The CELLMAP[0] is the first cell
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* placed.
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*
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* All enumerationsa arer defined in the la_iopadring.vh
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*
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* [7:0] PIN# = pin# (order 0-255)
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* [15:8] COMPLEMENT PIN# = pin# (order 0-255)
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* [23:16] CELL = cell type from lambdalib (0-255)
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* [31:24] SECTION = power rail selector (when NSECTIONS>1)
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* [39:32] PROP = cell property (optional)
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*
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*/
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localparam [NCELLS*40-1:0] CELLMAP =
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{{NULL, NULL, LA_CUT, NULL, NULL},
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{NULL, NULL, LA_BIDIR, NULL, PIN15},
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{NULL, NULL, LA_BIDIR, NULL, PIN14},
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{NULL, NULL, LA_BIDIR, NULL, PIN13},
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{NULL, NULL, LA_BIDIR, NULL, PIN12},
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{NULL, NULL, LA_VSS, NULL, NULL},
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{NULL, NULL, LA_VDD, NULL, NULL},
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{NULL, NULL, LA_VDDIO, NULL, NULL},
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{NULL, NULL, LA_VSSIO, NULL, NULL},
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{NULL, NULL, LA_BIDIR, NULL, PIN11},
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{NULL, NULL, LA_BIDIR, NULL, PIN10},
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{NULL, NULL, LA_BIDIR, NULL, PIN9},
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{NULL, NULL, LA_BIDIR, NULL, PIN8},
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{NULL, NULL, LA_VSS, NULL, NULL},
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{NULL, NULL, LA_VDD, NULL, NULL},
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{NULL, NULL, LA_POC, NULL, NULL},
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{NULL, NULL, LA_VDDIO, NULL, NULL},
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{NULL, NULL, LA_VSSIO, NULL, NULL},
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{NULL, NULL, LA_BIDIR, NULL, PIN7},
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{NULL, NULL, LA_BIDIR, NULL, PIN6},
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{NULL, NULL, LA_BIDIR, NULL, PIN5},
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{NULL, NULL, LA_BIDIR, NULL, PIN4},
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{NULL, NULL, LA_VSS, NULL, NULL},
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{NULL, NULL, LA_VDD, NULL, NULL},
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{NULL, NULL, LA_VDDIO, NULL, NULL},
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{NULL, NULL, LA_VSSIO, NULL, NULL},
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{NULL, NULL, LA_BIDIR, NULL, PIN3},
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{NULL, NULL, LA_BIDIR, NULL, PIN2},
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{NULL, NULL, LA_BIDIR, NULL, PIN1},
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{NULL, NULL, LA_BIDIR, NULL, PIN0},
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{NULL, NULL, LA_CUT, NULL, NULL}};
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//########################################################################
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// Symmetrical padring for simplicity (not a restriction)
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//########################################################################
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localparam NO_NCELLS = NCELLS;
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localparam EA_NCELLS = NCELLS;
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localparam WE_NCELLS = NCELLS;
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localparam SO_NCELLS = NCELLS;
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localparam NO_NSECTIONS = NSECTIONS;
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localparam EA_NSECTIONS = NSECTIONS;
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localparam WE_NSECTIONS = NSECTIONS;
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localparam SO_NSECTIONS = NSECTIONS;
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localparam NO_CELLMAP = CELLMAP;
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localparam EA_CELLMAP = CELLMAP;
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localparam WE_CELLMAP = CELLMAP;
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localparam SO_CELLMAP = CELLMAP;

‎examples/sram/rtl/sram.v‎

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module sram();
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// TODO: put in la_spram
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endmodule

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