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aolofssonaolofsson
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Finalizing code cleanup in padring
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‎lambdalib/padring/rtl/la_iopadring.v‎

Lines changed: 173 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -5,23 +5,24 @@
55
*
66
* Documentation:
77
*
8-
* - see "../README.md"
8+
* - See "../README.md" for complete information
99
*
10-
* - Cround (vss) is continuous around the while chip.
10+
* PIN[7:0] = pin number connected to cell
1111
*
12-
* - Default is for ioring to be cut at corners, user must short rings
13-
* at top level in RTl/netlist if abutted ring extends across corners.
12+
* COMP[7:0] = pin number for negative pad for differential cells
1413
*
15-
* - CELLMAP = {SECTION#, PROP, CELL, PIN#}
14+
* CELL[7:0] = cell type (see ./la_padring.vh)
1615
*
17-
* - SECTION specifies which power domain the pin belongs to
16+
* SECTION[7:0] = padring power section number connected to cell
1817
*
19-
* - PIN maps the cell to the pin number
18+
* PROP[7:0] = property passed to technology specific iolib implementation
2019
*
21-
* - CELLTYPE[3:0] specifies the cell type (see la_iopadring.vh)
20+
* Cell Map Example:
2221
*
23-
* - CELLTYPE[7:4] is used by inside lambda cells for selection
22+
* CELLMAP[79:0] = {{NULL, NULL, LA_RXDIFF, PIN_RXN, PIN_RXP}
23+
* {NULL, NULL, LA_BIDIR, NULL, PIN_IO0}}
2424
*
25+
2526
* Testing:
2627
*
2728
* >> iverilog la_iopadring.v -DTB_LA_IOPADRING -y . -y ../../iolib/rtl
@@ -32,24 +33,24 @@
3233

3334
module la_iopadring
3435
#(
35-
parameter CFGW = 8, // width of config bus
36-
parameter RINGW = 8, // width of io ring
37-
parameter NO_NPINS = 1, // IO pins per side
38-
parameter NO_NCELLS = 1, // cells per side
39-
parameter NO_NSECTIONS = 1, // sections per side
40-
parameter NO_CELLMAP = 0, // cell configuration (see above)
41-
parameter EA_NPINS = 1,
42-
parameter EA_NCELLS = 1,
43-
parameter EA_NSECTIONS = 1,
44-
parameter EA_CELLMAP = 0,
45-
parameter SO_NPINS = 1,
46-
parameter SO_NCELLS = 1,
47-
parameter SO_NSECTIONS = 1,
48-
parameter SO_CELLMAP = 0,
49-
parameter WE_NPINS = 1,
50-
parameter WE_NCELLS = 1,
51-
parameter WE_NSECTIONS = 1,
52-
parameter WE_CELLMAP = 0
36+
parameter CFGW = 8, // config width
37+
parameter RINGW = 8, // ioring width
38+
parameter NO_NPINS = 1, // pins per side
39+
parameter NO_NCELLS = 1, // cells per side
40+
parameter NO_NSECTIONS = 1, // sections per side
41+
parameter [NO_NCELLS*40-1:0] NO_CELLMAP = 0, // see ../README.md
42+
parameter EA_NPINS = 1,
43+
parameter EA_NCELLS = 1,
44+
parameter EA_NSECTIONS = 1,
45+
parameter [EA_NCELLS*40-1:0] EA_CELLMAP = 0,
46+
parameter SO_NPINS = 1,
47+
parameter SO_NCELLS = 1,
48+
parameter SO_NSECTIONS = 1,
49+
parameter [SO_NCELLS*40-1:0] SO_CELLMAP = 0,
50+
parameter WE_NPINS = 1,
51+
parameter WE_NCELLS = 1,
52+
parameter WE_NSECTIONS = 1,
53+
parameter [WE_NCELLS*40-1:0] WE_CELLMAP = 0
5354
)
5455
(// CONTINUOUS GROUND
5556
inout vss,
@@ -136,12 +137,12 @@ module la_iopadring
136137

137138
// EAST
138139
la_ioside #(.SIDE("EA"),
139-
.NPINS(EA_NPINS),
140-
.NCELLS(EA_NCELLS),
141-
.NSECTIONS(EA_NSECTIONS),
142-
.CELLMAP(EA_CELLMAP),
143-
.RINGW(RINGW),
144-
.CFGW(CFGW))
140+
.NPINS(EA_NPINS),
141+
.NCELLS(EA_NCELLS),
142+
.NSECTIONS(EA_NSECTIONS),
143+
.CELLMAP(EA_CELLMAP),
144+
.RINGW(RINGW),
145+
.CFGW(CFGW))
145146
ieast (// Outputs
146147
.zp (ea_zp),
147148
.zn (ea_zn),
@@ -212,15 +213,45 @@ module la_iopadring
212213
endmodule
213214

214215
//#####################################################################
215-
// A SIMPLE TESTBENCH (FOR ELABORATION)
216+
// A SIMPLE TESTBENCH
216217
//#####################################################################
217218

218219

219-
`ifdef TB_LA_IOPDADRING
220+
`ifdef TB_LA_IOPADRING
220221
module tb();
221222

222-
localparam PERIOD = 2;
223-
localparam TIMEOUT = PERIOD * 33;
223+
`include "la_iopadring.vh"
224+
225+
parameter PERIOD = 2;
226+
parameter TIMEOUT = PERIOD * 50;
227+
228+
// config
229+
localparam CFGW = 8;
230+
localparam RINGW = 8;
231+
localparam NPINS = 4;
232+
localparam NCELLS = 8;
233+
localparam NSECTIONS = 1;
234+
235+
// pinmap
236+
localparam [7:0] PIN_IO0 = 8'h00;
237+
localparam [7:0] PIN_AN0 = 8'h01;
238+
localparam [7:0] PIN_RXP = 8'h02;
239+
localparam [7:0] PIN_RXN = 8'h03;
240+
localparam NULL = 8'h0;
241+
242+
localparam [40*NPINS-1:0] CELLMAP =
243+
{{NULL, NULL, LA_VSS, NULL, NULL},
244+
{NULL, NULL, LA_BIDIR, NULL, PIN_IO0},
245+
{NULL, NULL, LA_ANALOG, NULL, PIN_AN0},
246+
{NULL, NULL, LA_VDDIO, NULL, NULL},
247+
{NULL, NULL, LA_RXDIFF, PIN_RXN, PIN_RXP},
248+
{NULL, NULL, LA_VSS, NULL, NULL},
249+
{NULL, NULL, LA_VSS, NULL, NULL},
250+
{NULL, NULL, LA_VSS, NULL, NULL}};
251+
252+
253+
reg [NPINS-1:0] stimulus;
254+
wire [NPINS-1:0] driver;
224255

225256
// control block
226257
initial
@@ -232,92 +263,120 @@ module tb();
232263
$finish;
233264
end
234265

235-
// test program
236266
initial
237267
begin
238268
#(1)
239-
nreset = 'b0;
240-
clk = 'b0;
241-
#(1)
242-
$display("---- AND GATE ----");
243-
nreset = 'b1;
244-
lut = 16'h8000; // 4 input and gate
245-
#(PERIOD * 16)
246-
$display("---- OR GATE ----");
247-
lut = 16'hFFFE; // 4 input or gate
269+
stimulus = 'b0;
270+
#(PERIOD * 25)
271+
stimulus = {NPINS{1'b1}};
248272
end
249273

250-
// clk
251-
always
252-
#(PERIOD/2) clk = ~clk;
253-
254-
// counter to cycle through stimulus
255-
always @ (posedge clk or negedge nreset)
256-
if (~nreset)
257-
in <= 'b0;
258-
else
259-
in <= in + 1'b1;
274+
assign driver = stimulus;
260275

261-
always @ (posedge clk)
262-
if (nreset)
263-
$display("lut=%h, in=%b, out=%b", lut, in, out);
276+
/*AUTOWIRE*/
277+
// Beginning of automatic wires (for undeclared instantiated-module outputs)
278+
wire [NSECTIONS*RINGW-1:0] ea_ioring;
279+
wire [NSECTIONS-1:0] ea_vdd;
280+
wire [NSECTIONS-1:0] ea_vddio;
281+
wire [NSECTIONS-1:0] ea_vssio;
282+
wire [NSECTIONS*RINGW-1:0] no_ioring;
283+
wire [NSECTIONS-1:0] no_vdd;
284+
wire [NSECTIONS-1:0] no_vddio;
285+
wire [NSECTIONS-1:0] no_vssio;
286+
wire [NSECTIONS*RINGW-1:0] so_ioring;
287+
wire [NSECTIONS-1:0] so_vdd;
288+
wire [NSECTIONS-1:0] so_vddio;
289+
wire [NSECTIONS-1:0] so_vssio;
290+
wire vss;
291+
wire [NSECTIONS*RINGW-1:0] we_ioring;
292+
wire [NSECTIONS-1:0] we_vdd;
293+
wire [NSECTIONS-1:0] we_vddio;
294+
wire [NSECTIONS-1:0] we_vssio;
295+
// End of automatics
264296

297+
/*la_iopadring AUTO_TEMPLATE (
298+
.\(.*\)_a ({NPINS{1'b0}}),
299+
.\(.*\)_ie ({NPINS{1'b1}}),
300+
.\(.*\)_oe ({NPINS{1'b0}}),
301+
.\(.*\)_cfg ({CFGW*NPINS{1'b0}}),
302+
.\(.*\)_vdd (\1_vdd[NSECTIONS-1:0]),
303+
.\(.*\)_vddio (\1_vddio[NSECTIONS-1:0]),
304+
.\(.*\)_vssio (\1_vssio[NSECTIONS-1:0]),
305+
.\(.*\)_ioring (\1_ioring[NSECTIONS*RINGW-1:0]),
306+
.\(.*\)_z\(.*\) (),
307+
.\(.*\)_aio\(.*\) (),
308+
.\(.*\)_pad (driver[NPINS-1:0]),
309+
);
310+
*/
265311

266312
// dut
267-
la_iopadring
268-
la_iopadring (/*AUTOINST*/
269-
// Outputs
270-
.no_zp (no_zp[NO_NPINS-1:0]),
271-
.no_zn (no_zn[NO_NPINS-1:0]),
272-
.ea_zp (ea_zp[EA_NPINS-1:0]),
273-
.ea_zn (ea_zn[EA_NPINS-1:0]),
274-
.so_zp (so_zp[SO_NPINS-1:0]),
275-
.so_zn (so_zn[SO_NPINS-1:0]),
276-
.we_zp (we_zp[WE_NPINS-1:0]),
277-
.we_zn (we_zn[WE_NPINS-1:0]),
278-
// Inouts
279-
.vss (vss),
280-
.no_pad (no_pad[NO_NPINS-1:0]),
281-
.no_aio (no_aio[NO_NPINS*3-1:0]),
282-
.no_vdd (no_vdd[NO_NSECTIONS-1:0]),
283-
.no_vddio (no_vddio[NO_NSECTIONS-1:0]),
284-
.no_vssio (no_vssio[NO_NSECTIONS-1:0]),
285-
.no_ioring (no_ioring[NO_NSECTIONS*RINGW-1:0]),
286-
.ea_pad (ea_pad[EA_NPINS-1:0]),
287-
.ea_aio (ea_aio[EA_NPINS*3-1:0]),
288-
.ea_vdd (ea_vdd[EA_NSECTIONS-1:0]),
289-
.ea_vddio (ea_vddio[EA_NSECTIONS-1:0]),
290-
.ea_vssio (ea_vssio[EA_NSECTIONS-1:0]),
291-
.ea_ioring (ea_ioring[EA_NSECTIONS*RINGW-1:0]),
292-
.so_pad (so_pad[SO_NPINS-1:0]),
293-
.so_aio (so_aio[SO_NPINS*3-1:0]),
294-
.so_vdd (so_vdd[SO_NSECTIONS-1:0]),
295-
.so_vddio (so_vddio[SO_NSECTIONS-1:0]),
296-
.so_vssio (so_vssio[SO_NSECTIONS-1:0]),
297-
.so_ioring (so_ioring[SO_NSECTIONS*RINGW-1:0]),
298-
.we_pad (we_pad[WE_NPINS-1:0]),
299-
.we_aio (we_aio[WE_NPINS*3-1:0]),
300-
.we_vdd (we_vdd[WE_NSECTIONS-1:0]),
301-
.we_vddio (we_vddio[WE_NSECTIONS-1:0]),
302-
.we_vssio (we_vssio[WE_NSECTIONS-1:0]),
303-
.we_ioring (we_ioring[WE_NSECTIONS*RINGW-1:0]),
304-
// Inputs
305-
.no_a (no_a[NO_NPINS-1:0]),
306-
.no_ie (no_ie[NO_NPINS-1:0]),
307-
.no_oe (no_oe[NO_NPINS-1:0]),
308-
.no_cfg (no_cfg[NO_NPINS*CFGW-1:0]),
309-
.ea_a (ea_a[EA_NPINS-1:0]),
310-
.ea_ie (ea_ie[EA_NPINS-1:0]),
311-
.ea_oe (ea_oe[EA_NPINS-1:0]),
312-
.ea_cfg (ea_cfg[EA_NPINS*CFGW-1:0]),
313-
.so_a (so_a[SO_NPINS-1:0]),
314-
.so_ie (so_ie[SO_NPINS-1:0]),
315-
.so_oe (so_oe[SO_NPINS-1:0]),
316-
.so_cfg (so_cfg[SO_NPINS*CFGW-1:0]),
317-
.we_a (we_a[WE_NPINS-1:0]),
318-
.we_ie (we_ie[WE_NPINS-1:0]),
319-
.we_oe (we_oe[WE_NPINS-1:0]),
320-
.we_cfg (we_cfg[WE_NPINS*CFGW-1:0]));
313+
la_iopadring #(.CFGW(CFGW),
314+
.RINGW(RINGW),
315+
.NO_NPINS(NPINS),
316+
.EA_NPINS(NPINS),
317+
.WE_NPINS(NPINS),
318+
.SO_NPINS(NPINS),
319+
.NO_NCELLS(NCELLS),
320+
.EA_NCELLS(NCELLS),
321+
.WE_NCELLS(NCELLS),
322+
.SO_NCELLS(NCELLS),
323+
.NO_CELLMAP(CELLMAP),
324+
.EA_CELLMAP(CELLMAP),
325+
.WE_CELLMAP(CELLMAP),
326+
.SO_CELLMAP(CELLMAP))
327+
la_iopadring (/*AUTOINST*/
328+
// Outputs
329+
.no_zp (), // Templated
330+
.no_zn (), // Templated
331+
.ea_zp (), // Templated
332+
.ea_zn (), // Templated
333+
.so_zp (), // Templated
334+
.so_zn (), // Templated
335+
.we_zp (), // Templated
336+
.we_zn (), // Templated
337+
// Inouts
338+
.vss (vss),
339+
.no_pad (driver[NPINS-1:0]), // Templated
340+
.no_aio (), // Templated
341+
.no_vdd (no_vdd[NSECTIONS-1:0]), // Templated
342+
.no_vddio (no_vddio[NSECTIONS-1:0]), // Templated
343+
.no_vssio (no_vssio[NSECTIONS-1:0]), // Templated
344+
.no_ioring (no_ioring[NSECTIONS*RINGW-1:0]), // Templated
345+
.ea_pad (driver[NPINS-1:0]), // Templated
346+
.ea_aio (), // Templated
347+
.ea_vdd (ea_vdd[NSECTIONS-1:0]), // Templated
348+
.ea_vddio (ea_vddio[NSECTIONS-1:0]), // Templated
349+
.ea_vssio (ea_vssio[NSECTIONS-1:0]), // Templated
350+
.ea_ioring (ea_ioring[NSECTIONS*RINGW-1:0]), // Templated
351+
.so_pad (driver[NPINS-1:0]), // Templated
352+
.so_aio (), // Templated
353+
.so_vdd (so_vdd[NSECTIONS-1:0]), // Templated
354+
.so_vddio (so_vddio[NSECTIONS-1:0]), // Templated
355+
.so_vssio (so_vssio[NSECTIONS-1:0]), // Templated
356+
.so_ioring (so_ioring[NSECTIONS*RINGW-1:0]), // Templated
357+
.we_pad (driver[NPINS-1:0]), // Templated
358+
.we_aio (), // Templated
359+
.we_vdd (we_vdd[NSECTIONS-1:0]), // Templated
360+
.we_vddio (we_vddio[NSECTIONS-1:0]), // Templated
361+
.we_vssio (we_vssio[NSECTIONS-1:0]), // Templated
362+
.we_ioring (we_ioring[NSECTIONS*RINGW-1:0]), // Templated
363+
// Inputs
364+
.no_a ({NPINS{1'b0}}), // Templated
365+
.no_ie ({NPINS{1'b1}}), // Templated
366+
.no_oe ({NPINS{1'b0}}), // Templated
367+
.no_cfg ({CFGW*NPINS{1'b0}}), // Templated
368+
.ea_a ({NPINS{1'b0}}), // Templated
369+
.ea_ie ({NPINS{1'b1}}), // Templated
370+
.ea_oe ({NPINS{1'b0}}), // Templated
371+
.ea_cfg ({CFGW*NPINS{1'b0}}), // Templated
372+
.so_a ({NPINS{1'b0}}), // Templated
373+
.so_ie ({NPINS{1'b1}}), // Templated
374+
.so_oe ({NPINS{1'b0}}), // Templated
375+
.so_cfg ({CFGW*NPINS{1'b0}}), // Templated
376+
.we_a ({NPINS{1'b0}}), // Templated
377+
.we_ie ({NPINS{1'b1}}), // Templated
378+
.we_oe ({NPINS{1'b0}}), // Templated
379+
.we_cfg ({CFGW*NPINS{1'b0}})); // Templated
321380

322381
endmodule
323382
// Local Variables:

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