From 78f60f51389d1432163f4376e0646fd5d8e272a1 Mon Sep 17 00:00:00 2001 From: tzuchilin Date: Sat, 22 Mar 2025 14:45:54 +0800 Subject: [PATCH] feat: integrate LiteX SoC --- .gitignore | 6 + Makefile | 12 +- cpu/CPU.mk | 13 + cpu/Makefile | 5 + cpu/bare-program/.cargo/config.toml | 10 + cpu/bare-program/.gitignore | 2 + cpu/bare-program/Cargo.lock | 685 ++++++++++++++++++++ cpu/bare-program/Cargo.toml | 15 + cpu/bare-program/Makefile | 3 + cpu/bare-program/memory.x | 10 + cpu/bare-program/src/main.rs | 38 ++ cpu/bare-program/src/print.rs | 67 ++ cpu/bare-program/src/timer.rs | 43 ++ cpu/setup.sh | 14 + cpu/ulx3s-hal/Cargo.lock | 650 +++++++++++++++++++ cpu/ulx3s-hal/Cargo.toml | 17 + cpu/ulx3s-hal/src/build.rs | 1 + cpu/ulx3s-hal/src/device.x | 3 + cpu/ulx3s-hal/src/lib.rs | 963 ++++++++++++++++++++++++++++ cpu/ulx3s-hal/src/ulx3s.svd | 682 ++++++++++++++++++++ flake.nix | 9 + 21 files changed, 3247 insertions(+), 1 deletion(-) create mode 100644 cpu/CPU.mk create mode 100644 cpu/Makefile create mode 100644 cpu/bare-program/.cargo/config.toml create mode 100644 cpu/bare-program/.gitignore create mode 100644 cpu/bare-program/Cargo.lock create mode 100644 cpu/bare-program/Cargo.toml create mode 100644 cpu/bare-program/Makefile create mode 100644 cpu/bare-program/memory.x create mode 100644 cpu/bare-program/src/main.rs create mode 100644 cpu/bare-program/src/print.rs create mode 100644 cpu/bare-program/src/timer.rs create mode 100644 cpu/setup.sh create mode 100644 cpu/ulx3s-hal/Cargo.lock create mode 100644 cpu/ulx3s-hal/Cargo.toml create mode 100644 cpu/ulx3s-hal/src/build.rs create mode 100644 cpu/ulx3s-hal/src/device.x create mode 100644 cpu/ulx3s-hal/src/lib.rs create mode 100644 cpu/ulx3s-hal/src/ulx3s.svd diff --git a/.gitignore b/.gitignore index d251707..ed75d1b 100644 --- a/.gitignore +++ b/.gitignore @@ -10,3 +10,9 @@ metals.sbt .envrc .direnv/ + +lite*/ +litex_setup.py +pythondata*/ +valentyusb/ +migen/ diff --git a/Makefile b/Makefile index 9a15e85..1e96636 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,7 @@ BUILDDIR ?= build +CPUDIR ?= cpu TARGET ?= ulx3s +PORT ?= /dev/ttyUSB0 all: synth @@ -12,7 +14,7 @@ $(BUILDDIR)/Raster.sv: $(shell find src/main/scala -type f) $(BUILDDIR)/%: @mkdir -p $@ -.PHONY: sim +.PHONY: sim cpu sim: $(BUILDDIR)/Raster.sv $(BUILDDIR)/sim @make -C sim run BUILDDIR=$(CURDIR)/$(BUILDDIR)/sim @@ -25,5 +27,13 @@ prog: $(BUILDDIR)/Raster.sv $(BUILDDIR)/$(TARGET) flash: $(BUILDDIR)/Raster.sv $(BUILDDIR)/$(TARGET) @make -C synth/$(TARGET) flash BUILDDIR=$(CURDIR)/$(BUILDDIR)/$(TARGET) +cpu: FORCE + @make -C $(CPUDIR) + +cpu-test: $(CPUDIR)/bare-program + @PORT=$(PORT) make -C $(CPUDIR)/bare-program + clean: @rm -rf $(BUILDDIR) + +FORCE: diff --git a/cpu/CPU.mk b/cpu/CPU.mk new file mode 100644 index 0000000..091f991 --- /dev/null +++ b/cpu/CPU.mk @@ -0,0 +1,13 @@ +TARGET = radiona_ulx3s +DEVICE = LFE5U-85F +SDRAM = W9825G6KH6 +BUS ?= axi-lite +CPU ?= vexriscv +VARIANT ?= minimal+debug + +all: FORCE + @python3 -m litex_boards.targets.$(TARGET) \ + --device $(DEVICE) --sdram-module $(SDRAM) \ + --bus-standard $(BUS) --cpu-type $(CPU) \ + --cpu-variant $(VARIANT) --build --load +FORCE: diff --git a/cpu/Makefile b/cpu/Makefile new file mode 100644 index 0000000..3f38197 --- /dev/null +++ b/cpu/Makefile @@ -0,0 +1,5 @@ +all: FORCE + @bash setup.sh + @make -C litex + +FORCE: diff --git a/cpu/bare-program/.cargo/config.toml b/cpu/bare-program/.cargo/config.toml new file mode 100644 index 0000000..3952887 --- /dev/null +++ b/cpu/bare-program/.cargo/config.toml @@ -0,0 +1,10 @@ +[target.riscv32i-unknown-none-elf] +rustflags = [ + "-C", "link-arg=-Tmemory.x", + "-C", "link-arg=-Tlink.x", + "-C", "linker-plugin-lto", +] + + +[build] +target = "riscv32i-unknown-none-elf" diff --git a/cpu/bare-program/.gitignore b/cpu/bare-program/.gitignore new file mode 100644 index 0000000..5a48dd5 --- /dev/null +++ b/cpu/bare-program/.gitignore @@ -0,0 +1,2 @@ +/target +*.bin \ No newline at end of file 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-0,0 +1,3 @@ +all: src + @cargo objcopy --release -- -O binary program.bin + @litex_term --kernel program.bin $(PORT) diff --git a/cpu/bare-program/memory.x b/cpu/bare-program/memory.x new file mode 100644 index 0000000..243cb65 --- /dev/null +++ b/cpu/bare-program/memory.x @@ -0,0 +1,10 @@ +MEMORY { + sdram : ORIGIN = 0x40000000, LENGTH = 0x00010000 +} + +REGION_ALIAS("REGION_TEXT", sdram); +REGION_ALIAS("REGION_RODATA", sdram); +REGION_ALIAS("REGION_DATA", sdram); +REGION_ALIAS("REGION_BSS", sdram); +REGION_ALIAS("REGION_HEAP", sdram); +REGION_ALIAS("REGION_STACK", sdram); diff --git a/cpu/bare-program/src/main.rs b/cpu/bare-program/src/main.rs new file mode 100644 index 0000000..40faa79 --- /dev/null +++ b/cpu/bare-program/src/main.rs @@ -0,0 +1,38 @@ +#![no_std] +#![no_main] + +extern crate panic_halt; + +use ulx3s_hal; +use riscv_rt::entry; + +mod print; +mod timer; + +use timer::Timer; + +const SYSTEM_CLOCK_FREQUENCY: u32 = 50_000_000; + +#[entry] +fn main() -> ! { + let peripherals = unsafe { ulx3s_hal::Peripherals::steal() }; + + print::print_hardware::set_hardware(peripherals.uart); + let mut timer = Timer::new(peripherals.timer0); + + loop { + print!("Hello LiteX SoC\r\n"); + msleep(&mut timer, 500); + } +} + +fn msleep(timer: &mut Timer, ms: u32) { + timer.disable(); + + timer.reload(0); + timer.load(SYSTEM_CLOCK_FREQUENCY / 1_000 * ms); + + timer.enable(); + + while timer.value() > 0 {} +} diff --git a/cpu/bare-program/src/print.rs b/cpu/bare-program/src/print.rs new file mode 100644 index 0000000..149bd75 --- /dev/null +++ b/cpu/bare-program/src/print.rs @@ -0,0 +1,67 @@ +use ulx3s_hal::Uart; + +pub struct UART { + pub registers: Option, +} + +impl UART { + pub fn putc(&self, c: u8) { + match self.registers.as_ref() { + Some(reg) => unsafe { + while reg.txfull().read().bits() != 0 { + () + } + reg.rxtx().write(|w| w.rxtx().bits(c)); + }, + None => (), + } + } +} + +use core::fmt::{Error, Write}; +impl Write for UART { + fn write_str(&mut self, s: &str) -> Result<(), Error> { + for c in s.bytes() { + self.putc(c); + } + Ok(()) + } +} + +#[macro_use] +#[cfg(not(test))] +pub mod print_hardware { + use crate::print::*; + pub static mut SUPERVISOR_UART: UART = UART { registers: None }; + + pub fn set_hardware(uart: Uart) { + unsafe { + SUPERVISOR_UART.registers = Some(uart); + } + } + + #[macro_export] + macro_rules! print + { + ($($args:tt)+) => ({ + use core::fmt::Write; + unsafe { + let _ = write!(crate::print::print_hardware::SUPERVISOR_UART, $($args)+); + } + }); + } +} + +#[macro_export] +macro_rules! println +{ + () => ({ + print!("\r\n") + }); + ($fmt:expr) => ({ + print!(concat!($fmt, "\r\n")) + }); + ($fmt:expr, $($args:tt)+) => ({ + print!(concat!($fmt, "\r\n"), $($args)+) + }); +} diff --git a/cpu/bare-program/src/timer.rs b/cpu/bare-program/src/timer.rs new file mode 100644 index 0000000..4cdf34a --- /dev/null +++ b/cpu/bare-program/src/timer.rs @@ -0,0 +1,43 @@ +use ulx3s_hal::Timer0; + +pub struct Timer { + registers: Timer0, +} + +impl Timer { + pub fn new(registers: Timer0) -> Self { + Self { registers } + } + + pub fn enable(&mut self) { + unsafe { + self.registers.en().write(|w| w.bits(1)); + } + } + + pub fn disable(&mut self) { + unsafe { + self.registers.en().write(|w| w.bits(0)); + } + } + + pub fn load(&mut self, value: u32) { + unsafe { + self.registers.load().write(|w| w.bits(value)); + } + } + + pub fn reload(&mut self, value: u32) { + unsafe { + self.registers.reload().write(|w| w.bits(value)); + } + } + + pub fn value(&mut self) -> u32 { + unsafe { + self.registers.update_value().write(|w| w.bits(1)); + } + + self.registers.value().read().bits() + } +} diff --git a/cpu/setup.sh b/cpu/setup.sh new file mode 100644 index 0000000..1c9563d --- /dev/null +++ b/cpu/setup.sh @@ -0,0 +1,14 @@ +if [ ! -d "litex" ]; then + # Install LiteX + if [ ! -f "litex_setup.py" ]; then + wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py + chmod +x litex_setup.py + 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a/cpu/ulx3s-hal/Cargo.toml b/cpu/ulx3s-hal/Cargo.toml new file mode 100644 index 0000000..2b25cd2 --- /dev/null +++ b/cpu/ulx3s-hal/Cargo.toml @@ -0,0 +1,17 @@ +[package] +name = "ulx3s-hal" +version = "0.1.0" +edition = "2021" + +[dependencies] +bare-metal = "1.0" +riscv = "0.10" +vcell = "0.1" +riscv-rt = { optional = true, version = "0.14.0" } + +[build-dependencies] +svd2rust = { version = "0.36", default-features = false } + +[features] +default = ["rt"] +rt = ["dep:riscv-rt"] diff --git a/cpu/ulx3s-hal/src/build.rs b/cpu/ulx3s-hal/src/build.rs new file mode 100644 index 0000000..11733ec --- /dev/null +++ b/cpu/ulx3s-hal/src/build.rs @@ -0,0 +1 @@ +# ! [doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] use std :: env ; use std :: fs :: File ; use std :: io :: Write ; use std :: path :: PathBuf ; fn main () { if env :: var_os ("CARGO_FEATURE_RT") . is_some () { let out = & PathBuf :: from (env :: var_os ("OUT_DIR") . unwrap ()) ; File :: create (out . join ("device.x")) . unwrap () . write_all (include_bytes ! ("device.x")) . unwrap () ; println ! ("cargo:rustc-link-search={}" , out . display ()) ; println ! ("cargo:rerun-if-changed=device.x") ; } println ! ("cargo:rerun-if-changed=build.rs") ; } diff --git a/cpu/ulx3s-hal/src/device.x b/cpu/ulx3s-hal/src/device.x new file mode 100644 index 0000000..ceb54ee --- /dev/null +++ b/cpu/ulx3s-hal/src/device.x @@ -0,0 +1,3 @@ +PROVIDE(uart = DefaultHandler); +PROVIDE(timer0 = DefaultHandler); + diff --git a/cpu/ulx3s-hal/src/lib.rs b/cpu/ulx3s-hal/src/lib.rs new file mode 100644 index 0000000..ca2a97a --- /dev/null +++ b/cpu/ulx3s-hal/src/lib.rs @@ -0,0 +1,963 @@ +# ! [doc = "Peripheral access API for SOC microcontrollers (generated using svd2rust v0.36.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.36.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] # ! [allow (non_camel_case_types)] # ! [allow (non_snake_case)] # ! [no_std] # ! [cfg_attr (docsrs , feature (doc_auto_cfg))] +#[allow (unused_imports)] use generic :: * ; +#[doc = r"Common register and bit access and modify traits"] pub mod generic { use core :: marker ; +#[doc = " Generic peripheral accessor"] pub struct Periph < RB , const A : usize > { _marker : marker :: PhantomData < RB > , } unsafe impl < RB , const A : usize > Send for Periph < RB , A > { } impl < RB , const A : usize > Periph < RB , A > { +#[doc = "Pointer to the register block"] pub const PTR : * const RB = A as * const _ ; +#[doc = "Return the pointer to the register block"] +#[inline (always)] pub const fn ptr () -> * const RB { Self :: PTR } +#[doc = " Steal an instance of this peripheral"] +#[doc = ""] +#[doc = " # Safety"] +#[doc = ""] +#[doc = " Ensure that the new instance of the peripheral cannot be used in a way"] +#[doc = " that may race with any existing instances, for example by only"] +#[doc = " accessing read-only or write-only registers, or by consuming the"] +#[doc = " original peripheral and using critical sections to coordinate"] +#[doc = " access between multiple new instances."] +#[doc = ""] +#[doc = " Additionally, other software such as HALs may rely on only one"] +#[doc = " peripheral instance existing to ensure memory safety; ensure"] +#[doc = " no stolen instances are passed to such software."] pub unsafe fn steal () -> Self { Self { _marker : marker :: PhantomData , } } } impl < RB , const A : usize > core :: ops :: Deref for Periph < RB , A > { type Target = RB ; +#[inline (always)] fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] pub trait RawReg : Copy + From < bool > + core :: ops :: BitOr < Output = Self > + core :: ops :: BitAnd < Output = Self > + core :: ops :: BitOrAssign + core :: ops :: BitAndAssign + core :: ops :: Not < Output = Self > + core :: ops :: Shl < u8 , Output = Self > { +#[doc = " Mask for bits of width `WI`"] fn mask < const WI : u8 > () -> Self ; +#[doc = " `0`"] const ZERO : Self ; +#[doc = " `1`"] const ONE : Self ; } macro_rules ! raw_reg { ($ U : ty , $ size : literal , $ mask : ident) => { impl RawReg for $ U { +#[inline (always)] fn mask < const WI : u8 > () -> Self { $ mask ::< WI > () } const ZERO : Self = 0 ; const ONE : Self = 1 ; } const fn $ mask < const WI : u8 > () -> $ U { <$ U >:: MAX >> ($ size - WI) } impl FieldSpec for $ U { type Ux = $ U ; } } ; } raw_reg ! (u8 , 8 , mask_u8) ; raw_reg ! (u16 , 16 , mask_u16) ; raw_reg ! (u32 , 32 , mask_u32) ; raw_reg ! (u64 , 64 , mask_u64) ; +#[doc = " Raw register type"] pub trait RegisterSpec { +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] type Ux : RawReg ; } +#[doc = " Raw field type"] pub trait FieldSpec : Sized { +#[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] type Ux : Copy + core :: fmt :: Debug + PartialEq + From < Self > ; } +#[doc = " Marker for fields with fixed values"] pub trait IsEnum : FieldSpec { } +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] pub trait Readable : RegisterSpec { } +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] pub trait Writable : RegisterSpec { +#[doc = " Is it safe to write any bits to register"] type Safety ; +#[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = Self :: Ux :: ZERO ; +#[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = Self :: Ux :: ZERO ; } +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] pub trait Resettable : RegisterSpec { +#[doc = " Reset value of the register."] const RESET_VALUE : Self :: Ux = Self :: Ux :: ZERO ; +#[doc = " Reset value of the register."] +#[inline (always)] fn reset_value () -> Self :: Ux { Self :: RESET_VALUE } } +#[doc (hidden)] pub mod raw { use super :: { marker , BitM , FieldSpec , RegisterSpec , Unsafe , Writable } ; pub struct R < REG : RegisterSpec > { pub (crate) bits : REG :: Ux , pub (super) _reg : marker :: PhantomData < REG > , } pub struct W < REG : RegisterSpec > { +#[doc = "Writable bits"] pub (crate) bits : REG :: Ux , pub (super) _reg : marker :: PhantomData < REG > , } pub struct FieldReader < FI = u8 > where FI : FieldSpec , { pub (crate) bits : FI :: Ux , _reg : marker :: PhantomData < FI > , } impl < FI : FieldSpec > FieldReader < FI > { +#[doc = " Creates a new instance of the reader."] +#[allow (unused)] +#[inline (always)] pub (crate) const fn new (bits : FI :: Ux) -> Self { Self { bits , _reg : marker :: PhantomData , } } } pub struct BitReader < FI = bool > { pub (crate) bits : bool , _reg : marker :: PhantomData < FI > , } impl < FI > BitReader < FI > { +#[doc = " Creates a new instance of the reader."] +#[allow (unused)] +#[inline (always)] pub (crate) const fn new (bits : bool) -> Self { Self { bits , _reg : marker :: PhantomData , } } } +#[must_use = "after creating `FieldWriter` you need to call field value setting method"] pub struct FieldWriter < 'a , REG , const WI : u8 , FI = u8 , Safety = Unsafe > where REG : Writable + RegisterSpec , FI : FieldSpec , { pub (crate) w : & 'a mut W < REG > , pub (crate) o : u8 , _field : marker :: PhantomData < (FI , Safety) > , } impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , { +#[doc = " Creates a new instance of the writer"] +#[allow (unused)] +#[inline (always)] pub (crate) fn new (w : & 'a mut W < REG > , o : u8) -> Self { Self { w , o , _field : marker :: PhantomData , } } } +#[must_use = "after creating `BitWriter` you need to call bit setting method"] pub struct BitWriter < 'a , REG , FI = bool , M = BitM > where REG : Writable + RegisterSpec , bool : From < FI > , { pub (crate) w : & 'a mut W < REG > , pub (crate) o : u8 , _field : marker :: PhantomData < (FI , M) > , } impl < 'a , REG , FI , M > BitWriter < 'a , REG , FI , M > where REG : Writable + RegisterSpec , bool : From < FI > , { +#[doc = " Creates a new instance of the writer"] +#[allow (unused)] +#[inline (always)] pub (crate) fn new (w : & 'a mut W < REG > , o : u8) -> Self { Self { w , o , _field : marker :: PhantomData , } } } } +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] pub type R < REG > = raw :: R < REG > ; impl < REG : RegisterSpec > R < REG > { +#[doc = " Reads raw bits from register."] +#[inline (always)] pub const fn bits (& self) -> REG :: Ux { self . bits } } impl < REG : RegisterSpec , FI > PartialEq < FI > for R < REG > where REG :: Ux : PartialEq , FI : Copy , REG :: Ux : From < FI > , { +#[inline (always)] fn eq (& self , other : & FI) -> bool { self . bits . eq (& REG :: Ux :: from (* other)) } } +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] pub type W < REG > = raw :: W < REG > ; impl < REG : Writable > W < REG > { +#[doc = " Writes raw bits to the register."] +#[doc = ""] +#[doc = " # Safety"] +#[doc = ""] +#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] +#[inline (always)] pub unsafe fn bits (& mut self , bits : REG :: Ux) -> & mut Self { self . bits = bits ; self } } impl < REG > W < REG > where REG : Writable < Safety = Safe > , { +#[doc = " Writes raw bits to the register."] +#[inline (always)] pub fn set (& mut self , bits : REG :: Ux) -> & mut Self { self . bits = bits ; self } } +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] pub type FieldReader < FI = u8 > = raw :: FieldReader < FI > ; +#[doc = " Bit-wise field reader"] pub type BitReader < FI = bool > = raw :: BitReader < FI > ; impl < FI : FieldSpec > FieldReader < FI > { +#[doc = " Reads raw bits from field."] +#[inline (always)] pub const fn bits (& self) -> FI :: Ux { self . bits } } impl < FI : FieldSpec > core :: fmt :: Debug for FieldReader < FI > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . bits , f) } } impl < FI > PartialEq < FI > for FieldReader < FI > where FI : FieldSpec + Copy , { +#[inline (always)] fn eq (& self , other : & FI) -> bool { self . bits . eq (& FI :: Ux :: from (* other)) } } impl < FI > PartialEq < FI > for BitReader < FI > where FI : Copy , bool : From < FI > , { +#[inline (always)] fn eq (& self , other : & FI) -> bool { self . bits . eq (& bool :: from (* other)) } } impl < FI > BitReader < FI > { +#[doc = " Value of the field as raw bits."] +#[inline (always)] pub const fn bit (& self) -> bool { self . bits } +#[doc = " Returns `true` if the bit is clear (0)."] +#[inline (always)] pub const fn bit_is_clear (& self) -> bool { ! self . bit () } +#[doc = " Returns `true` if the bit is set (1)."] +#[inline (always)] pub const fn bit_is_set (& self) -> bool { self . bit () } } impl < FI > core :: fmt :: Debug for BitReader < FI > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . bits , f) } } +#[doc = " Marker for register/field writers which can take any value of specified width"] pub struct Safe ; +#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] pub struct Unsafe ; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] pub struct Range < const MIN : u64 , const MAX : u64 > ; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] pub struct RangeFrom < const MIN : u64 > ; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] pub struct RangeTo < const MAX : u64 > ; +#[doc = " Write field Proxy"] pub type FieldWriter < 'a , REG , const WI : u8 , FI = u8 , Safety = Unsafe > = raw :: FieldWriter < 'a , REG , WI , FI , Safety > ; impl < REG , const WI : u8 , FI , Safety > FieldWriter < '_ , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , { +#[doc = " Field width"] pub const WIDTH : u8 = WI ; +#[doc = " Field width"] +#[inline (always)] pub const fn width (& self) -> u8 { WI } +#[doc = " Field offset"] +#[inline (always)] pub const fn offset (& self) -> u8 { self . o } } impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , { +#[doc = " Writes raw bits to the field"] +#[doc = ""] +#[doc = " # Safety"] +#[doc = ""] +#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] +#[inline (always)] pub unsafe fn bits (self , value : FI :: Ux) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: mask :: < WI > () << self . o) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: mask :: < WI > ()) << self . o ; self . w } } impl < 'a , REG , const WI : u8 , FI > FieldWriter < 'a , REG , WI , FI , Safe > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , { +#[doc = " Writes raw bits to the field"] +#[inline (always)] pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , const MIN : u64 , const MAX : u64 > FieldWriter < 'a , REG , WI , FI , Range < MIN , MAX > > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , u64 : From < FI :: Ux > , { +#[doc = " Writes raw bits to the field"] +#[inline (always)] pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { { let value = u64 :: from (value) ; assert ! (value >= MIN && value <= MAX) ; } unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , const MIN : u64 > FieldWriter < 'a , REG , WI , FI , RangeFrom < MIN > > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , u64 : From < FI :: Ux > , { +#[doc = " Writes raw bits to the field"] +#[inline (always)] pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { { let value = u64 :: from (value) ; assert ! (value >= MIN) ; } unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , const MAX : u64 > FieldWriter < 'a , REG , WI , FI , RangeTo < MAX > > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , u64 : From < FI :: Ux > , { +#[doc = " Writes raw bits to the field"] +#[inline (always)] pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { { let value = u64 :: from (value) ; assert ! (value <= MAX) ; } unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : IsEnum , REG :: Ux : From < FI :: Ux > , { +#[doc = " Writes `variant` to the field"] +#[inline (always)] pub fn variant (self , variant : FI) -> & 'a mut W < REG > { unsafe { self . bits (FI :: Ux :: from (variant)) } } } macro_rules ! bit_proxy { ($ writer : ident , $ mwv : ident) => { +#[doc (hidden)] pub struct $ mwv ; +#[doc = " Bit-wise write field proxy"] pub type $ writer <'a , REG , FI = bool > = raw :: BitWriter <'a , REG , FI , $ mwv >; impl <'a , REG , FI > $ writer <'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI >, { +#[doc = " Field width"] pub const WIDTH : u8 = 1 ; +#[doc = " Field width"] +#[inline (always)] pub const fn width (& self) -> u8 { Self :: WIDTH } +#[doc = " Field offset"] +#[inline (always)] pub const fn offset (& self) -> u8 { self . o } +#[doc = " Writes bit to the field"] +#[inline (always)] pub fn bit (self , value : bool) -> &'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: ONE << self . o) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: ONE) << self . o ; self . w } +#[doc = " Writes `variant` to the field"] +#[inline (always)] pub fn variant (self , variant : FI) -> &'a mut W < REG > { self . bit (bool :: from (variant)) } } } ; } bit_proxy ! (BitWriter , BitM) ; bit_proxy ! (BitWriter1S , Bit1S) ; bit_proxy ! (BitWriter0C , Bit0C) ; bit_proxy ! (BitWriter1C , Bit1C) ; bit_proxy ! (BitWriter0S , Bit0S) ; bit_proxy ! (BitWriter1T , Bit1T) ; bit_proxy ! (BitWriter0T , Bit0T) ; impl < 'a , REG , FI > BitWriter < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { +#[doc = " Sets the field bit"] +#[inline (always)] pub fn set_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: ONE << self . o ; self . w } +#[doc = " Clears the field bit"] +#[inline (always)] pub fn clear_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: ONE << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1S < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { +#[doc = " Sets the field bit"] +#[inline (always)] pub fn set_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: ONE << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0C < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { +#[doc = " Clears the field bit"] +#[inline (always)] pub fn clear_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: ONE << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1C < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { +#[doc = "Clears the field bit by passing one"] +#[inline (always)] pub fn clear_bit_by_one (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: ONE << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0S < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { +#[doc = "Sets the field bit by passing zero"] +#[inline (always)] pub fn set_bit_by_zero (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: ONE << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1T < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { +#[doc = "Toggle the field bit by passing one"] +#[inline (always)] pub fn toggle_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: ONE << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0T < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { +#[doc = "Toggle the field bit by passing zero"] +#[inline (always)] pub fn toggle_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: ONE << self . o) ; self . w } } +#[doc = " This structure provides volatile access to registers."] +#[repr (transparent)] pub struct Reg < REG : RegisterSpec > { register : vcell :: VolatileCell < REG :: Ux > , _marker : marker :: PhantomData < REG > , } unsafe impl < REG : RegisterSpec > Send for Reg < REG > where REG :: Ux : Send { } impl < REG : RegisterSpec > Reg < REG > { +#[doc = " Returns the underlying memory address of register."] +#[doc = ""] +#[doc = " ```ignore"] +#[doc = " let reg_ptr = periph.reg.as_ptr();"] +#[doc = " ```"] +#[inline (always)] pub fn as_ptr (& self) -> * mut REG :: Ux { self . register . as_ptr () } } impl < REG : Readable > Reg < REG > { +#[doc = " Reads the contents of a `Readable` register."] +#[doc = ""] +#[doc = " You can read the raw contents of a register by using `bits`:"] +#[doc = " ```ignore"] +#[doc = " let bits = periph.reg.read().bits();"] +#[doc = " ```"] +#[doc = " or get the content of a particular field of a register:"] +#[doc = " ```ignore"] +#[doc = " let reader = periph.reg.read();"] +#[doc = " let bits = reader.field1().bits();"] +#[doc = " let flag = reader.field2().bit_is_set();"] +#[doc = " ```"] +#[inline (always)] pub fn read (& self) -> R < REG > { R { bits : self . register . get () , _reg : marker :: PhantomData , } } } impl < REG : Resettable + Writable > Reg < REG > { +#[doc = " Writes the reset value to `Writable` register."] +#[doc = ""] +#[doc = " Resets the register to its initial state."] +#[inline (always)] pub fn reset (& self) { self . register . set (REG :: RESET_VALUE) } +#[doc = " Writes bits to a `Writable` register."] +#[doc = ""] +#[doc = " You can write raw bits into a register:"] +#[doc = " ```ignore"] +#[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] +#[doc = " ```"] +#[doc = " or write only the fields you need:"] +#[doc = " ```ignore"] +#[doc = " periph.reg.write(|w| w"] +#[doc = " .field1().bits(newfield1bits)"] +#[doc = " .field2().set_bit()"] +#[doc = " .field3().variant(VARIANT)"] +#[doc = " );"] +#[doc = " ```"] +#[doc = " or an alternative way of saying the same:"] +#[doc = " ```ignore"] +#[doc = " periph.reg.write(|w| {"] +#[doc = " w.field1().bits(newfield1bits);"] +#[doc = " w.field2().set_bit();"] +#[doc = " w.field3().variant(VARIANT)"] +#[doc = " });"] +#[doc = " ```"] +#[doc = " In the latter case, other fields will be set to their reset value."] +#[inline (always)] pub fn write < F > (& self , f : F) -> REG :: Ux where F : FnOnce (& mut W < REG >) -> & mut W < REG > , { let value = f (& mut W { bits : REG :: RESET_VALUE & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , }) . bits ; self . register . set (value) ; value } +#[doc = " Writes bits to a `Writable` register and produce a value."] +#[doc = ""] +#[doc = " You can write raw bits into a register:"] +#[doc = " ```ignore"] +#[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"] +#[doc = " ```"] +#[doc = " or write only the fields you need:"] +#[doc = " ```ignore"] +#[doc = " periph.reg.write_and(|w| {"] +#[doc = " w.field1().bits(newfield1bits)"] +#[doc = " .field2().set_bit()"] +#[doc = " .field3().variant(VARIANT);"] +#[doc = " });"] +#[doc = " ```"] +#[doc = " or an alternative way of saying the same:"] +#[doc = " ```ignore"] +#[doc = " periph.reg.write_and(|w| {"] +#[doc = " w.field1().bits(newfield1bits);"] +#[doc = " w.field2().set_bit();"] +#[doc = " w.field3().variant(VARIANT);"] +#[doc = " });"] +#[doc = " ```"] +#[doc = " In the latter case, other fields will be set to their reset value."] +#[doc = ""] +#[doc = " Values can be returned from the closure:"] +#[doc = " ```ignore"] +#[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"] +#[doc = " ```"] +#[inline (always)] pub fn from_write < F , T > (& self , f : F) -> T where F : FnOnce (& mut W < REG >) -> T , { let mut writer = W { bits : REG :: RESET_VALUE & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , } ; let result = f (& mut writer) ; self . register . set (writer . bits) ; result } } impl < REG : Writable > Reg < REG > { +#[doc = " Writes 0 to a `Writable` register."] +#[doc = ""] +#[doc = " Similar to `write`, but unused bits will contain 0."] +#[doc = ""] +#[doc = " # Safety"] +#[doc = ""] +#[doc = " Unsafe to use with registers which don't allow to write 0."] +#[inline (always)] pub unsafe fn write_with_zero < F > (& self , f : F) -> REG :: Ux where F : FnOnce (& mut W < REG >) -> & mut W < REG > , { let value = f (& mut W { bits : REG :: Ux :: ZERO , _reg : marker :: PhantomData , }) . bits ; self . register . set (value) ; value } +#[doc = " Writes 0 to a `Writable` register and produces a value."] +#[doc = ""] +#[doc = " Similar to `write`, but unused bits will contain 0."] +#[doc = ""] +#[doc = " # Safety"] +#[doc = ""] +#[doc = " Unsafe to use with registers which don't allow to write 0."] +#[inline (always)] pub unsafe fn from_write_with_zero < F , T > (& self , f : F) -> T where F : FnOnce (& mut W < REG >) -> T , { let mut writer = W { bits : REG :: Ux :: ZERO , _reg : marker :: PhantomData , } ; let result = f (& mut writer) ; self . register . set (writer . bits) ; result } } impl < REG : Readable + Writable > Reg < REG > { +#[doc = " Modifies the contents of the register by reading and then writing it."] +#[doc = ""] +#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] +#[doc = " ```ignore"] +#[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] +#[doc = " r.bits() | 3"] +#[doc = " ) });"] +#[doc = " ```"] +#[doc = " or"] +#[doc = " ```ignore"] +#[doc = " periph.reg.modify(|_, w| w"] +#[doc = " .field1().bits(newfield1bits)"] +#[doc = " .field2().set_bit()"] +#[doc = " .field3().variant(VARIANT)"] +#[doc = " );"] +#[doc = " ```"] +#[doc = " or an alternative way of saying the same:"] +#[doc = " ```ignore"] +#[doc = " periph.reg.modify(|_, w| {"] +#[doc = " w.field1().bits(newfield1bits);"] +#[doc = " w.field2().set_bit();"] +#[doc = " w.field3().variant(VARIANT)"] +#[doc = " });"] +#[doc = " ```"] +#[doc = " Other fields will have the value they had before the call to `modify`."] +#[inline (always)] pub fn modify < F > (& self , f : F) -> REG :: Ux where for < 'w > F : FnOnce (& R < REG > , & 'w mut W < REG >) -> & 'w mut W < REG > , { let bits = self . register . get () ; let value = f (& R { bits , _reg : marker :: PhantomData , } , & mut W { bits : bits & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , } ,) . bits ; self . register . set (value) ; value } +#[doc = " Modifies the contents of the register by reading and then writing it"] +#[doc = " and produces a value."] +#[doc = ""] +#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] +#[doc = " ```ignore"] +#[doc = " let bits = periph.reg.modify(|r, w| {"] +#[doc = " let new_bits = r.bits() | 3;"] +#[doc = " unsafe {"] +#[doc = " w.bits(new_bits);"] +#[doc = " }"] +#[doc = ""] +#[doc = " new_bits"] +#[doc = " });"] +#[doc = " ```"] +#[doc = " or"] +#[doc = " ```ignore"] +#[doc = " periph.reg.modify(|_, w| {"] +#[doc = " w.field1().bits(newfield1bits)"] +#[doc = " .field2().set_bit()"] +#[doc = " .field3().variant(VARIANT);"] +#[doc = " });"] +#[doc = " ```"] +#[doc = " or an alternative way of saying the same:"] +#[doc = " ```ignore"] +#[doc = " periph.reg.modify(|_, w| {"] +#[doc = " w.field1().bits(newfield1bits);"] +#[doc = " w.field2().set_bit();"] +#[doc = " w.field3().variant(VARIANT);"] +#[doc = " });"] +#[doc = " ```"] +#[doc = " Other fields will have the value they had before the call to `modify`."] +#[inline (always)] pub fn from_modify < F , T > (& self , f : F) -> T where for < 'w > F : FnOnce (& R < REG > , & 'w mut W < REG >) -> T , { let bits = self . register . get () ; let mut writer = W { bits : bits & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , } ; let result = f (& R { bits , _reg : marker :: PhantomData , } , & mut writer ,) ; self . register . set (writer . bits) ; result } } impl < REG : Readable > core :: fmt :: Debug for crate :: generic :: Reg < REG > where R < REG > : core :: fmt :: Debug , { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } } +#[cfg (feature = "rt")] extern "C" { fn uart () ; fn timer0 () ; } +#[doc (hidden)] +#[repr (C)] pub union Vector { pub _handler : unsafe extern "C" fn () , pub _reserved : usize , } +#[cfg (feature = "rt")] +#[doc (hidden)] +#[no_mangle] pub static __EXTERNAL_INTERRUPTS : [Vector ; 2] = [Vector { _handler : uart } , Vector { _handler : timer0 } ,] ; +#[doc (hidden)] pub mod interrupt { +#[doc = r"Enumeration of all the interrupts."] +#[derive (Copy , Clone , Debug , PartialEq , Eq)] +#[repr (u16)] pub enum Interrupt { +#[doc = "0 - uart"] uart = 0 , +#[doc = "1 - timer0"] timer0 = 1 , } +#[doc = r" TryFromInterruptError"] +#[derive (Debug , Copy , Clone)] pub struct TryFromInterruptError (()) ; impl Interrupt { +#[doc = r" Attempt to convert a given value into an `Interrupt`"] +#[inline] pub fn try_from (value : u8) -> Result < Self , TryFromInterruptError > { match value { 0 => Ok (Interrupt :: uart) , 1 => Ok (Interrupt :: timer0) , _ => Err (TryFromInterruptError (())) , } } } +#[cfg (feature = "rt")] +#[macro_export] +#[doc = r" Assigns a handler to an interrupt"] +#[doc = r""] +#[doc = r" This macro takes two arguments: the name of an interrupt and the path to the"] +#[doc = r" function that will be used as the handler of that interrupt. That function"] +#[doc = r" must have signature `fn()`."] +#[doc = r""] +#[doc = r" Optionally, a third argument may be used to declare interrupt local data."] +#[doc = r" The handler will have exclusive access to these *local* variables on each"] +#[doc = r" invocation. If the third argument is used then the signature of the handler"] +#[doc = r" function must be `fn(&mut $NAME::Locals)` where `$NAME` is the first argument"] +#[doc = r" passed to the macro."] +#[doc = r""] +#[doc = r" # Example"] +#[doc = r""] +#[doc = r" ``` ignore"] +#[doc = r" interrupt!(TIM2, periodic);"] +#[doc = r""] +#[doc = r" fn periodic() {"] +#[doc = r#" print!(".");"#] +#[doc = r" }"] +#[doc = r""] +#[doc = r" interrupt!(TIM3, tick, locals: {"] +#[doc = r" tick: bool = false;"] +#[doc = r" });"] +#[doc = r""] +#[doc = r" fn tick(locals: &mut TIM3::Locals) {"] +#[doc = r" locals.tick = !locals.tick;"] +#[doc = r""] +#[doc = r" if locals.tick {"] +#[doc = r#" println!("Tick");"#] +#[doc = r" } else {"] +#[doc = r#" println!("Tock");"#] +#[doc = r" }"] +#[doc = r" }"] +#[doc = r" ```"] macro_rules ! interrupt { ($ NAME : ident , $ path : path , locals : { $ ($ lvar : ident : $ lty : ty = $ lval : expr ;) * }) => { +#[allow (non_snake_case)] mod $ NAME { pub struct Locals { $ (pub $ lvar : $ lty ,) * } } +#[allow (non_snake_case)] +#[no_mangle] pub extern "C" fn $ NAME () { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; static mut LOCALS : self :: $ NAME :: Locals = self :: $ NAME :: Locals { $ ($ lvar : $ lval ,) * } ; let f : fn (& mut self :: $ NAME :: Locals) = $ path ; f (unsafe { & mut LOCALS }) ; } } ; ($ NAME : ident , $ path : path) => { +#[allow (non_snake_case)] +#[no_mangle] pub extern "C" fn $ NAME () { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; let f : fn () = $ path ; f () ; } } } } pub use self :: interrupt :: Interrupt ; +#[doc = "CTRL"] pub type Ctrl = crate :: Periph < ctrl :: RegisterBlock , 0xf000_0000 > ; impl core :: fmt :: Debug for Ctrl { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Ctrl") . finish () } } +#[doc = "CTRL"] pub mod ctrl { +#[repr (C)] +#[doc = "Register block"] pub struct RegisterBlock { reset : Reset , scratch : Scratch , bus_errors : BusErrors , } impl RegisterBlock { +#[doc = "0x00 - "] +#[inline (always)] pub const fn reset (& self) -> & Reset { & self . reset } +#[doc = "0x04 - Use this register as a scratch space to verify that software read/write accesses to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 can be used to verify endianness."] +#[inline (always)] pub const fn scratch (& self) -> & Scratch { & self . scratch } +#[doc = "0x08 - Total number of Wishbone bus errors (timeouts) since start."] +#[inline (always)] pub const fn bus_errors (& self) -> & BusErrors { & self . bus_errors } } +#[doc = "RESET (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset`] module"] +#[doc (alias = "RESET")] pub type Reset = crate :: Reg < reset :: ResetSpec > ; +#[doc = ""] pub mod reset { +#[doc = "Register `RESET` reader"] pub type R = crate :: R < ResetSpec > ; +#[doc = "Register `RESET` writer"] pub type W = crate :: W < ResetSpec > ; +#[doc = "Field `soc_rst` reader - Write `1` to this register to reset the full SoC (Pulse Reset)"] pub type SocRstR = crate :: BitReader ; +#[doc = "Field `soc_rst` writer - Write `1` to this register to reset the full SoC (Pulse Reset)"] pub type SocRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `cpu_rst` reader - Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset)"] pub type CpuRstR = crate :: BitReader ; +#[doc = "Field `cpu_rst` writer - Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset)"] pub type CpuRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0 - Write `1` to this register to reset the full SoC (Pulse Reset)"] +#[inline (always)] pub fn soc_rst (& self) -> SocRstR { SocRstR :: new ((self . bits & 1) != 0) } +#[doc = "Bit 1 - Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset)"] +#[inline (always)] pub fn cpu_rst (& self) -> CpuRstR { CpuRstR :: new (((self . bits >> 1) & 1) != 0) } } impl W { +#[doc = "Bit 0 - Write `1` to this register to reset the full SoC (Pulse Reset)"] +#[inline (always)] pub fn soc_rst (& mut self) -> SocRstW < ResetSpec > { SocRstW :: new (self , 0) } +#[doc = "Bit 1 - Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset)"] +#[inline (always)] pub fn cpu_rst (& mut self) -> CpuRstW < ResetSpec > { CpuRstW :: new (self , 1) } } +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ResetSpec ; impl crate :: RegisterSpec for ResetSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`reset::R`](R) reader structure"] impl crate :: Readable for ResetSpec { } +#[doc = "`write(|w| ..)` method takes [`reset::W`](W) writer structure"] impl crate :: Writable for ResetSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets RESET to value 0"] impl crate :: Resettable for ResetSpec { } } +#[doc = "SCRATCH (rw) register accessor: Use this register as a scratch space to verify that software read/write accesses to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 can be used to verify endianness.\n\nYou can [`read`](crate::Reg::read) this register and get [`scratch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scratch`] module"] +#[doc (alias = "SCRATCH")] pub type Scratch = crate :: Reg < scratch :: ScratchSpec > ; +#[doc = "Use this register as a scratch space to verify that software read/write accesses to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 can be used to verify endianness."] pub mod scratch { +#[doc = "Register `SCRATCH` reader"] pub type R = crate :: R < ScratchSpec > ; +#[doc = "Register `SCRATCH` writer"] pub type W = crate :: W < ScratchSpec > ; +#[doc = "Field `scratch` reader - "] pub type ScratchR = crate :: FieldReader < u32 > ; +#[doc = "Field `scratch` writer - "] pub type ScratchW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { +#[doc = "Bits 0:31"] +#[inline (always)] pub fn scratch (& self) -> ScratchR { ScratchR :: new (self . bits) } } impl W { +#[doc = "Bits 0:31"] +#[inline (always)] pub fn scratch (& mut self) -> ScratchW < ScratchSpec > { ScratchW :: new (self , 0) } } +#[doc = "Use this register as a scratch space to verify that software read/write accesses to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 can be used to verify endianness.\n\nYou can [`read`](crate::Reg::read) this register and get [`scratch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ScratchSpec ; impl crate :: RegisterSpec for ScratchSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`scratch::R`](R) reader structure"] impl crate :: Readable for ScratchSpec { } +#[doc = "`write(|w| ..)` method takes [`scratch::W`](W) writer structure"] impl crate :: Writable for ScratchSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets SCRATCH to value 0x1234_5678"] impl crate :: Resettable for ScratchSpec { const RESET_VALUE : u32 = 0x1234_5678 ; } } +#[doc = "BUS_ERRORS (rw) register accessor: Total number of Wishbone bus errors (timeouts) since start.\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_errors::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_errors::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_errors`] module"] +#[doc (alias = "BUS_ERRORS")] pub type BusErrors = crate :: Reg < bus_errors :: BusErrorsSpec > ; +#[doc = "Total number of Wishbone bus errors (timeouts) since start."] pub mod bus_errors { +#[doc = "Register `BUS_ERRORS` reader"] pub type R = crate :: R < BusErrorsSpec > ; +#[doc = "Register `BUS_ERRORS` writer"] pub type W = crate :: W < BusErrorsSpec > ; +#[doc = "Field `bus_errors` reader - "] pub type BusErrorsR = crate :: FieldReader < u32 > ; +#[doc = "Field `bus_errors` writer - "] pub type BusErrorsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { +#[doc = "Bits 0:31"] +#[inline (always)] pub fn bus_errors (& self) -> BusErrorsR { BusErrorsR :: new (self . bits) } } impl W { +#[doc = "Bits 0:31"] +#[inline (always)] pub fn bus_errors (& mut self) -> BusErrorsW < BusErrorsSpec > { BusErrorsW :: new (self , 0) } } +#[doc = "Total number of Wishbone bus errors (timeouts) since start.\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_errors::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_errors::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BusErrorsSpec ; impl crate :: RegisterSpec for BusErrorsSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`bus_errors::R`](R) reader structure"] impl crate :: Readable for BusErrorsSpec { } +#[doc = "`write(|w| ..)` method takes [`bus_errors::W`](W) writer structure"] impl crate :: Writable for BusErrorsSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets BUS_ERRORS to value 0"] impl crate :: Resettable for BusErrorsSpec { } } } +#[doc = "IDENTIFIER_MEM"] pub type IdentifierMem = crate :: Periph < identifier_mem :: RegisterBlock , 0xf000_0800 > ; impl core :: fmt :: Debug for IdentifierMem { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("IdentifierMem") . finish () } } +#[doc = "IDENTIFIER_MEM"] pub mod identifier_mem { +#[repr (C)] +#[doc = "Register block"] pub struct RegisterBlock { identifier_mem : IdentifierMem , } impl RegisterBlock { +#[doc = "0x00 - 8 x 39-bit memory"] +#[inline (always)] pub const fn identifier_mem (& self) -> & IdentifierMem { & self . identifier_mem } } +#[doc = "IDENTIFIER_MEM (rw) register accessor: 8 x 39-bit memory\n\nYou can [`read`](crate::Reg::read) this register and get [`identifier_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`identifier_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@identifier_mem`] module"] +#[doc (alias = "IDENTIFIER_MEM")] pub type IdentifierMem = crate :: Reg < identifier_mem :: IdentifierMemSpec > ; +#[doc = "8 x 39-bit memory"] pub mod identifier_mem { +#[doc = "Register `IDENTIFIER_MEM` reader"] pub type R = crate :: R < IdentifierMemSpec > ; +#[doc = "Register `IDENTIFIER_MEM` writer"] pub type W = crate :: W < IdentifierMemSpec > ; +#[doc = "Field `identifier_mem` reader - "] pub type IdentifierMemR = crate :: FieldReader ; +#[doc = "Field `identifier_mem` writer - "] pub type IdentifierMemW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { +#[doc = "Bits 0:7"] +#[inline (always)] pub fn identifier_mem (& self) -> IdentifierMemR { IdentifierMemR :: new ((self . bits & 0xff) as u8) } } impl W { +#[doc = "Bits 0:7"] +#[inline (always)] pub fn identifier_mem (& mut self) -> IdentifierMemW < IdentifierMemSpec > { IdentifierMemW :: new (self , 0) } } +#[doc = "8 x 39-bit memory\n\nYou can [`read`](crate::Reg::read) this register and get [`identifier_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`identifier_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IdentifierMemSpec ; impl crate :: RegisterSpec for IdentifierMemSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`identifier_mem::R`](R) reader structure"] impl crate :: Readable for IdentifierMemSpec { } +#[doc = "`write(|w| ..)` method takes [`identifier_mem::W`](W) writer structure"] impl crate :: Writable for IdentifierMemSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets IDENTIFIER_MEM to value 0"] impl crate :: Resettable for IdentifierMemSpec { } } } +#[doc = "LEDS"] pub type Leds = crate :: Periph < leds :: RegisterBlock , 0xf000_1000 > ; impl core :: fmt :: Debug for Leds { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Leds") . finish () } } +#[doc = "LEDS"] pub mod leds { +#[repr (C)] +#[doc = "Register block"] pub struct RegisterBlock { out : Out , } impl RegisterBlock { +#[doc = "0x00 - Led Output(s) Control."] +#[inline (always)] pub const fn out (& self) -> & Out { & self . out } } +#[doc = "OUT (rw) register accessor: Led Output(s) Control.\n\nYou can [`read`](crate::Reg::read) this register and get [`out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out`] module"] +#[doc (alias = "OUT")] pub type Out = crate :: Reg < out :: OutSpec > ; +#[doc = "Led Output(s) Control."] pub mod out { +#[doc = "Register `OUT` reader"] pub type R = crate :: R < OutSpec > ; +#[doc = "Register `OUT` writer"] pub type W = crate :: W < OutSpec > ; +#[doc = "Field `out` reader - "] pub type OutR = crate :: FieldReader ; +#[doc = "Field `out` writer - "] pub type OutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { +#[doc = "Bits 0:7"] +#[inline (always)] pub fn out (& self) -> OutR { OutR :: new ((self . bits & 0xff) as u8) } } impl W { +#[doc = "Bits 0:7"] +#[inline (always)] pub fn out (& mut self) -> OutW < OutSpec > { OutW :: new (self , 0) } } +#[doc = "Led Output(s) Control.\n\nYou can [`read`](crate::Reg::read) this register and get [`out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OutSpec ; impl crate :: RegisterSpec for OutSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`out::R`](R) reader structure"] impl crate :: Readable for OutSpec { } +#[doc = "`write(|w| ..)` method takes [`out::W`](W) writer structure"] impl crate :: Writable for OutSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets OUT to value 0"] impl crate :: Resettable for OutSpec { } } } +#[doc = "SDRAM"] pub type Sdram = crate :: Periph < sdram :: RegisterBlock , 0xf000_1800 > ; impl core :: fmt :: Debug for Sdram { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Sdram") . finish () } } +#[doc = "SDRAM"] pub mod sdram { +#[repr (C)] +#[doc = "Register block"] pub struct RegisterBlock { dfii_control : DfiiControl , dfii_pi0_command : DfiiPi0Command , dfii_pi0_command_issue : DfiiPi0CommandIssue , dfii_pi0_address : DfiiPi0Address , dfii_pi0_baddress : DfiiPi0Baddress , dfii_pi0_wrdata : DfiiPi0Wrdata , dfii_pi0_rddata : DfiiPi0Rddata , } impl RegisterBlock { +#[doc = "0x00 - Control DFI signals common to all phases"] +#[inline (always)] pub const fn dfii_control (& self) -> & DfiiControl { & self . dfii_control } +#[doc = "0x04 - Control DFI signals on a single phase"] +#[inline (always)] pub const fn dfii_pi0_command (& self) -> & DfiiPi0Command { & self . dfii_pi0_command } +#[doc = "0x08 - "] +#[inline (always)] pub const fn dfii_pi0_command_issue (& self) -> & DfiiPi0CommandIssue { & self . dfii_pi0_command_issue } +#[doc = "0x0c - DFI address bus"] +#[inline (always)] pub const fn dfii_pi0_address (& self) -> & DfiiPi0Address { & self . dfii_pi0_address } +#[doc = "0x10 - DFI bank address bus"] +#[inline (always)] pub const fn dfii_pi0_baddress (& self) -> & DfiiPi0Baddress { & self . dfii_pi0_baddress } +#[doc = "0x14 - DFI write data bus"] +#[inline (always)] pub const fn dfii_pi0_wrdata (& self) -> & DfiiPi0Wrdata { & self . dfii_pi0_wrdata } +#[doc = "0x18 - DFI read data bus"] +#[inline (always)] pub const fn dfii_pi0_rddata (& self) -> & DfiiPi0Rddata { & self . dfii_pi0_rddata } } +#[doc = "DFII_CONTROL (rw) register accessor: Control DFI signals common to all phases\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfii_control`] module"] +#[doc (alias = "DFII_CONTROL")] pub type DfiiControl = crate :: Reg < dfii_control :: DfiiControlSpec > ; +#[doc = "Control DFI signals common to all phases"] pub mod dfii_control { +#[doc = "Register `DFII_CONTROL` reader"] pub type R = crate :: R < DfiiControlSpec > ; +#[doc = "Register `DFII_CONTROL` writer"] pub type W = crate :: W < DfiiControlSpec > ; +#[doc = "Field `sel` reader - None"] pub type SelR = crate :: BitReader ; +#[doc = "Field `sel` writer - None"] pub type SelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `cke` reader - DFI clock enable bus"] pub type CkeR = crate :: BitReader ; +#[doc = "Field `cke` writer - DFI clock enable bus"] pub type CkeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `odt` reader - DFI on-die termination bus"] pub type OdtR = crate :: BitReader ; +#[doc = "Field `odt` writer - DFI on-die termination bus"] pub type OdtW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `reset_n` reader - DFI clock reset bus"] pub type ResetNR = crate :: BitReader ; +#[doc = "Field `reset_n` writer - DFI clock reset bus"] pub type ResetNW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0 - None"] +#[inline (always)] pub fn sel (& self) -> SelR { SelR :: new ((self . bits & 1) != 0) } +#[doc = "Bit 1 - DFI clock enable bus"] +#[inline (always)] pub fn cke (& self) -> CkeR { CkeR :: new (((self . bits >> 1) & 1) != 0) } +#[doc = "Bit 2 - DFI on-die termination bus"] +#[inline (always)] pub fn odt (& self) -> OdtR { OdtR :: new (((self . bits >> 2) & 1) != 0) } +#[doc = "Bit 3 - DFI clock reset bus"] +#[inline (always)] pub fn reset_n (& self) -> ResetNR { ResetNR :: new (((self . bits >> 3) & 1) != 0) } } impl W { +#[doc = "Bit 0 - None"] +#[inline (always)] pub fn sel (& mut self) -> SelW < DfiiControlSpec > { SelW :: new (self , 0) } +#[doc = "Bit 1 - DFI clock enable bus"] +#[inline (always)] pub fn cke (& mut self) -> CkeW < DfiiControlSpec > { CkeW :: new (self , 1) } +#[doc = "Bit 2 - DFI on-die termination bus"] +#[inline (always)] pub fn odt (& mut self) -> OdtW < DfiiControlSpec > { OdtW :: new (self , 2) } +#[doc = "Bit 3 - DFI clock reset bus"] +#[inline (always)] pub fn reset_n (& mut self) -> ResetNW < DfiiControlSpec > { ResetNW :: new (self , 3) } } +#[doc = "Control DFI signals common to all phases\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DfiiControlSpec ; impl crate :: RegisterSpec for DfiiControlSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`dfii_control::R`](R) reader structure"] impl crate :: Readable for DfiiControlSpec { } +#[doc = "`write(|w| ..)` method takes [`dfii_control::W`](W) writer structure"] impl crate :: Writable for DfiiControlSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets DFII_CONTROL to value 0x01"] impl crate :: Resettable for DfiiControlSpec { const RESET_VALUE : u32 = 0x01 ; } } +#[doc = "DFII_PI0_COMMAND (rw) register accessor: Control DFI signals on a single phase\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_command::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_command::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfii_pi0_command`] module"] +#[doc (alias = "DFII_PI0_COMMAND")] pub type DfiiPi0Command = crate :: Reg < dfii_pi0_command :: DfiiPi0CommandSpec > ; +#[doc = "Control DFI signals on a single phase"] pub mod dfii_pi0_command { +#[doc = "Register `DFII_PI0_COMMAND` reader"] pub type R = crate :: R < DfiiPi0CommandSpec > ; +#[doc = "Register `DFII_PI0_COMMAND` writer"] pub type W = crate :: W < DfiiPi0CommandSpec > ; +#[doc = "Field `cs` reader - DFI chip select bus"] pub type CsR = crate :: BitReader ; +#[doc = "Field `cs` writer - DFI chip select bus"] pub type CsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `we` reader - DFI write enable bus"] pub type WeR = crate :: BitReader ; +#[doc = "Field `we` writer - DFI write enable bus"] pub type WeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `cas` reader - DFI column address strobe bus"] pub type CasR = crate :: BitReader ; +#[doc = "Field `cas` writer - DFI column address strobe bus"] pub type CasW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `ras` reader - DFI row address strobe bus"] pub type RasR = crate :: BitReader ; +#[doc = "Field `ras` writer - DFI row address strobe bus"] pub type RasW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `wren` reader - DFI write data enable bus"] pub type WrenR = crate :: BitReader ; +#[doc = "Field `wren` writer - DFI write data enable bus"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `rden` reader - DFI read data enable bus"] pub type RdenR = crate :: BitReader ; +#[doc = "Field `rden` writer - DFI read data enable bus"] pub type RdenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `cs_top` reader - DFI chip select bus for top half only"] pub type CsTopR = crate :: BitReader ; +#[doc = "Field `cs_top` writer - DFI chip select bus for top half only"] pub type CsTopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `cs_bottom` reader - DFI chip select bus for bottom half only"] pub type CsBottomR = crate :: BitReader ; +#[doc = "Field `cs_bottom` writer - DFI chip select bus for bottom half only"] pub type CsBottomW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0 - DFI chip select bus"] +#[inline (always)] pub fn cs (& self) -> CsR { CsR :: new ((self . bits & 1) != 0) } +#[doc = "Bit 1 - DFI write enable bus"] +#[inline (always)] pub fn we (& self) -> WeR { WeR :: new (((self . bits >> 1) & 1) != 0) } +#[doc = "Bit 2 - DFI column address strobe bus"] +#[inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 2) & 1) != 0) } +#[doc = "Bit 3 - DFI row address strobe bus"] +#[inline (always)] pub fn ras (& self) -> RasR { RasR :: new (((self . bits >> 3) & 1) != 0) } +#[doc = "Bit 4 - DFI write data enable bus"] +#[inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 4) & 1) != 0) } +#[doc = "Bit 5 - DFI read data enable bus"] +#[inline (always)] pub fn rden (& self) -> RdenR { RdenR :: new (((self . bits >> 5) & 1) != 0) } +#[doc = "Bit 6 - DFI chip select bus for top half only"] +#[inline (always)] pub fn cs_top (& self) -> CsTopR { CsTopR :: new (((self . bits >> 6) & 1) != 0) } +#[doc = "Bit 7 - DFI chip select bus for bottom half only"] +#[inline (always)] pub fn cs_bottom (& self) -> CsBottomR { CsBottomR :: new (((self . bits >> 7) & 1) != 0) } } impl W { +#[doc = "Bit 0 - DFI chip select bus"] +#[inline (always)] pub fn cs (& mut self) -> CsW < DfiiPi0CommandSpec > { CsW :: new (self , 0) } +#[doc = "Bit 1 - DFI write enable bus"] +#[inline (always)] pub fn we (& mut self) -> WeW < DfiiPi0CommandSpec > { WeW :: new (self , 1) } +#[doc = "Bit 2 - DFI column address strobe bus"] +#[inline (always)] pub fn cas (& mut self) -> CasW < DfiiPi0CommandSpec > { CasW :: new (self , 2) } +#[doc = "Bit 3 - DFI row address strobe bus"] +#[inline (always)] pub fn ras (& mut self) -> RasW < DfiiPi0CommandSpec > { RasW :: new (self , 3) } +#[doc = "Bit 4 - DFI write data enable bus"] +#[inline (always)] pub fn wren (& mut self) -> WrenW < DfiiPi0CommandSpec > { WrenW :: new (self , 4) } +#[doc = "Bit 5 - DFI read data enable bus"] +#[inline (always)] pub fn rden (& mut self) -> RdenW < DfiiPi0CommandSpec > { RdenW :: new (self , 5) } +#[doc = "Bit 6 - DFI chip select bus for top half only"] +#[inline (always)] pub fn cs_top (& mut self) -> CsTopW < DfiiPi0CommandSpec > { CsTopW :: new (self , 6) } +#[doc = "Bit 7 - DFI chip select bus for bottom half only"] +#[inline (always)] pub fn cs_bottom (& mut self) -> CsBottomW < DfiiPi0CommandSpec > { CsBottomW :: new (self , 7) } } +#[doc = "Control DFI signals on a single phase\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_command::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_command::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DfiiPi0CommandSpec ; impl crate :: RegisterSpec for DfiiPi0CommandSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`dfii_pi0_command::R`](R) reader structure"] impl crate :: Readable for DfiiPi0CommandSpec { } +#[doc = "`write(|w| ..)` method takes [`dfii_pi0_command::W`](W) writer structure"] impl crate :: Writable for DfiiPi0CommandSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets DFII_PI0_COMMAND to value 0"] impl crate :: Resettable for DfiiPi0CommandSpec { } } +#[doc = "DFII_PI0_COMMAND_ISSUE (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_command_issue::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_command_issue::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfii_pi0_command_issue`] module"] +#[doc (alias = "DFII_PI0_COMMAND_ISSUE")] pub type DfiiPi0CommandIssue = crate :: Reg < dfii_pi0_command_issue :: DfiiPi0CommandIssueSpec > ; +#[doc = ""] pub mod dfii_pi0_command_issue { +#[doc = "Register `DFII_PI0_COMMAND_ISSUE` reader"] pub type R = crate :: R < DfiiPi0CommandIssueSpec > ; +#[doc = "Register `DFII_PI0_COMMAND_ISSUE` writer"] pub type W = crate :: W < DfiiPi0CommandIssueSpec > ; +#[doc = "Field `dfii_pi0_command_issue` reader - "] pub type DfiiPi0CommandIssueR = crate :: BitReader ; +#[doc = "Field `dfii_pi0_command_issue` writer - "] pub type DfiiPi0CommandIssueW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0"] +#[inline (always)] pub fn dfii_pi0_command_issue (& self) -> DfiiPi0CommandIssueR { DfiiPi0CommandIssueR :: new ((self . bits & 1) != 0) } } impl W { +#[doc = "Bit 0"] +#[inline (always)] pub fn dfii_pi0_command_issue (& mut self) -> DfiiPi0CommandIssueW < DfiiPi0CommandIssueSpec > { DfiiPi0CommandIssueW :: new (self , 0) } } +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_command_issue::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_command_issue::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DfiiPi0CommandIssueSpec ; impl crate :: RegisterSpec for DfiiPi0CommandIssueSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`dfii_pi0_command_issue::R`](R) reader structure"] impl crate :: Readable for DfiiPi0CommandIssueSpec { } +#[doc = "`write(|w| ..)` method takes [`dfii_pi0_command_issue::W`](W) writer structure"] impl crate :: Writable for DfiiPi0CommandIssueSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets DFII_PI0_COMMAND_ISSUE to value 0"] impl crate :: Resettable for DfiiPi0CommandIssueSpec { } } +#[doc = "DFII_PI0_ADDRESS (rw) register accessor: DFI address bus\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfii_pi0_address`] module"] +#[doc (alias = "DFII_PI0_ADDRESS")] pub type DfiiPi0Address = crate :: Reg < dfii_pi0_address :: DfiiPi0AddressSpec > ; +#[doc = "DFI address bus"] pub mod dfii_pi0_address { +#[doc = "Register `DFII_PI0_ADDRESS` reader"] pub type R = crate :: R < DfiiPi0AddressSpec > ; +#[doc = "Register `DFII_PI0_ADDRESS` writer"] pub type W = crate :: W < DfiiPi0AddressSpec > ; +#[doc = "Field `dfii_pi0_address` reader - "] pub type DfiiPi0AddressR = crate :: FieldReader < u16 > ; +#[doc = "Field `dfii_pi0_address` writer - "] pub type DfiiPi0AddressW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { +#[doc = "Bits 0:12"] +#[inline (always)] pub fn dfii_pi0_address (& self) -> DfiiPi0AddressR { DfiiPi0AddressR :: new ((self . bits & 0x1fff) as u16) } } impl W { +#[doc = "Bits 0:12"] +#[inline (always)] pub fn dfii_pi0_address (& mut self) -> DfiiPi0AddressW < DfiiPi0AddressSpec > { DfiiPi0AddressW :: new (self , 0) } } +#[doc = "DFI address bus\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DfiiPi0AddressSpec ; impl crate :: RegisterSpec for DfiiPi0AddressSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`dfii_pi0_address::R`](R) reader structure"] impl crate :: Readable for DfiiPi0AddressSpec { } +#[doc = "`write(|w| ..)` method takes [`dfii_pi0_address::W`](W) writer structure"] impl crate :: Writable for DfiiPi0AddressSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets DFII_PI0_ADDRESS to value 0"] impl crate :: Resettable for DfiiPi0AddressSpec { } } +#[doc = "DFII_PI0_BADDRESS (rw) register accessor: DFI bank address bus\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_baddress::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_baddress::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfii_pi0_baddress`] module"] +#[doc (alias = "DFII_PI0_BADDRESS")] pub type DfiiPi0Baddress = crate :: Reg < dfii_pi0_baddress :: DfiiPi0BaddressSpec > ; +#[doc = "DFI bank address bus"] pub mod dfii_pi0_baddress { +#[doc = "Register `DFII_PI0_BADDRESS` reader"] pub type R = crate :: R < DfiiPi0BaddressSpec > ; +#[doc = "Register `DFII_PI0_BADDRESS` writer"] pub type W = crate :: W < DfiiPi0BaddressSpec > ; +#[doc = "Field `dfii_pi0_baddress` reader - "] pub type DfiiPi0BaddressR = crate :: FieldReader ; +#[doc = "Field `dfii_pi0_baddress` writer - "] pub type DfiiPi0BaddressW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { +#[doc = "Bits 0:1"] +#[inline (always)] pub fn dfii_pi0_baddress (& self) -> DfiiPi0BaddressR { DfiiPi0BaddressR :: new ((self . bits & 3) as u8) } } impl W { +#[doc = "Bits 0:1"] +#[inline (always)] pub fn dfii_pi0_baddress (& mut self) -> DfiiPi0BaddressW < DfiiPi0BaddressSpec > { DfiiPi0BaddressW :: new (self , 0) } } +#[doc = "DFI bank address bus\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_baddress::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_baddress::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DfiiPi0BaddressSpec ; impl crate :: RegisterSpec for DfiiPi0BaddressSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`dfii_pi0_baddress::R`](R) reader structure"] impl crate :: Readable for DfiiPi0BaddressSpec { } +#[doc = "`write(|w| ..)` method takes [`dfii_pi0_baddress::W`](W) writer structure"] impl crate :: Writable for DfiiPi0BaddressSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets DFII_PI0_BADDRESS to value 0"] impl crate :: Resettable for DfiiPi0BaddressSpec { } } +#[doc = "DFII_PI0_WRDATA (rw) register accessor: DFI write data bus\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_wrdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_wrdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfii_pi0_wrdata`] module"] +#[doc (alias = "DFII_PI0_WRDATA")] pub type DfiiPi0Wrdata = crate :: Reg < dfii_pi0_wrdata :: DfiiPi0WrdataSpec > ; +#[doc = "DFI write data bus"] pub mod dfii_pi0_wrdata { +#[doc = "Register `DFII_PI0_WRDATA` reader"] pub type R = crate :: R < DfiiPi0WrdataSpec > ; +#[doc = "Register `DFII_PI0_WRDATA` writer"] pub type W = crate :: W < DfiiPi0WrdataSpec > ; +#[doc = "Field `dfii_pi0_wrdata` reader - "] pub type DfiiPi0WrdataR = crate :: FieldReader < u16 > ; +#[doc = "Field `dfii_pi0_wrdata` writer - "] pub type DfiiPi0WrdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { +#[doc = "Bits 0:15"] +#[inline (always)] pub fn dfii_pi0_wrdata (& self) -> DfiiPi0WrdataR { DfiiPi0WrdataR :: new ((self . bits & 0xffff) as u16) } } impl W { +#[doc = "Bits 0:15"] +#[inline (always)] pub fn dfii_pi0_wrdata (& mut self) -> DfiiPi0WrdataW < DfiiPi0WrdataSpec > { DfiiPi0WrdataW :: new (self , 0) } } +#[doc = "DFI write data bus\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_wrdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_wrdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DfiiPi0WrdataSpec ; impl crate :: RegisterSpec for DfiiPi0WrdataSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`dfii_pi0_wrdata::R`](R) reader structure"] impl crate :: Readable for DfiiPi0WrdataSpec { } +#[doc = "`write(|w| ..)` method takes [`dfii_pi0_wrdata::W`](W) writer structure"] impl crate :: Writable for DfiiPi0WrdataSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets DFII_PI0_WRDATA to value 0"] impl crate :: Resettable for DfiiPi0WrdataSpec { } } +#[doc = "DFII_PI0_RDDATA (rw) register accessor: DFI read data bus\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_rddata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_rddata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfii_pi0_rddata`] module"] +#[doc (alias = "DFII_PI0_RDDATA")] pub type DfiiPi0Rddata = crate :: Reg < dfii_pi0_rddata :: DfiiPi0RddataSpec > ; +#[doc = "DFI read data bus"] pub mod dfii_pi0_rddata { +#[doc = "Register `DFII_PI0_RDDATA` reader"] pub type R = crate :: R < DfiiPi0RddataSpec > ; +#[doc = "Register `DFII_PI0_RDDATA` writer"] pub type W = crate :: W < DfiiPi0RddataSpec > ; +#[doc = "Field `dfii_pi0_rddata` reader - "] pub type DfiiPi0RddataR = crate :: FieldReader < u16 > ; +#[doc = "Field `dfii_pi0_rddata` writer - "] pub type DfiiPi0RddataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { +#[doc = "Bits 0:15"] +#[inline (always)] pub fn dfii_pi0_rddata (& self) -> DfiiPi0RddataR { DfiiPi0RddataR :: new ((self . bits & 0xffff) as u16) } } impl W { +#[doc = "Bits 0:15"] +#[inline (always)] pub fn dfii_pi0_rddata (& mut self) -> DfiiPi0RddataW < DfiiPi0RddataSpec > { DfiiPi0RddataW :: new (self , 0) } } +#[doc = "DFI read data bus\n\nYou can [`read`](crate::Reg::read) this register and get [`dfii_pi0_rddata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfii_pi0_rddata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DfiiPi0RddataSpec ; impl crate :: RegisterSpec for DfiiPi0RddataSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`dfii_pi0_rddata::R`](R) reader structure"] impl crate :: Readable for DfiiPi0RddataSpec { } +#[doc = "`write(|w| ..)` method takes [`dfii_pi0_rddata::W`](W) writer structure"] impl crate :: Writable for DfiiPi0RddataSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets DFII_PI0_RDDATA to value 0"] impl crate :: Resettable for DfiiPi0RddataSpec { } } } +#[doc = "TIMER0"] pub type Timer0 = crate :: Periph < timer0 :: RegisterBlock , 0xf000_2000 > ; impl core :: fmt :: Debug for Timer0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Timer0") . finish () } } +#[doc = "TIMER0"] pub mod timer0 { +#[repr (C)] +#[doc = "Register block"] pub struct RegisterBlock { load : Load , reload : Reload , en : En , update_value : UpdateValue , value : Value , ev_status : EvStatus , ev_pending : EvPending , ev_enable : EvEnable , } impl RegisterBlock { +#[doc = "0x00 - Load value when Timer is (re-)enabled. In One-Shot mode, the value written to this register specifies the Timer's duration in clock cycles."] +#[inline (always)] pub const fn load (& self) -> & Load { & self . load } +#[doc = "0x04 - Reload value when Timer reaches ``0``. In Periodic mode, the value written to this register specify the Timer's period in clock cycles."] +#[inline (always)] pub const fn reload (& self) -> & Reload { & self . reload } +#[doc = "0x08 - Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set to ``0`` to disable the Timer."] +#[inline (always)] pub const fn en (& self) -> & En { & self . en } +#[doc = "0x0c - Update trigger for the current countdown value. A write to this register latches the current countdown value to ``value`` register."] +#[inline (always)] pub const fn update_value (& self) -> & UpdateValue { & self . update_value } +#[doc = "0x10 - Latched countdown value. This value is updated by writing to ``update_value``."] +#[inline (always)] pub const fn value (& self) -> & Value { & self . value } +#[doc = "0x14 - This register contains the current raw level of the zero event trigger. Writes to this register have no effect."] +#[inline (always)] pub const fn ev_status (& self) -> & EvStatus { & self . ev_status } +#[doc = "0x18 - When a zero event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register."] +#[inline (always)] pub const fn ev_pending (& self) -> & EvPending { & self . ev_pending } +#[doc = "0x1c - This register enables the corresponding zero events. Write a ``0`` to this register to disable individual events."] +#[inline (always)] pub const fn ev_enable (& self) -> & EvEnable { & self . ev_enable } } +#[doc = "LOAD (rw) register accessor: Load value when Timer is (re-)enabled. In One-Shot mode, the value written to this register specifies the Timer's duration in clock cycles.\n\nYou can [`read`](crate::Reg::read) this register and get [`load::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load`] module"] +#[doc (alias = "LOAD")] pub type Load = crate :: Reg < load :: LoadSpec > ; +#[doc = "Load value when Timer is (re-)enabled. In One-Shot mode, the value written to this register specifies the Timer's duration in clock cycles."] pub mod load { +#[doc = "Register `LOAD` reader"] pub type R = crate :: R < LoadSpec > ; +#[doc = "Register `LOAD` writer"] pub type W = crate :: W < LoadSpec > ; +#[doc = "Field `load` reader - "] pub type LoadR = crate :: FieldReader < u32 > ; +#[doc = "Field `load` writer - "] pub type LoadW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { +#[doc = "Bits 0:31"] +#[inline (always)] pub fn load (& self) -> LoadR { LoadR :: new (self . bits) } } impl W { +#[doc = "Bits 0:31"] +#[inline (always)] pub fn load (& mut self) -> LoadW < LoadSpec > { LoadW :: new (self , 0) } } +#[doc = "Load value when Timer is (re-)enabled. In One-Shot mode, the value written to this register specifies the Timer's duration in clock cycles.\n\nYou can [`read`](crate::Reg::read) this register and get [`load::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LoadSpec ; impl crate :: RegisterSpec for LoadSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`load::R`](R) reader structure"] impl crate :: Readable for LoadSpec { } +#[doc = "`write(|w| ..)` method takes [`load::W`](W) writer structure"] impl crate :: Writable for LoadSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets LOAD to value 0"] impl crate :: Resettable for LoadSpec { } } +#[doc = "RELOAD (rw) register accessor: Reload value when Timer reaches ``0``. In Periodic mode, the value written to this register specify the Timer's period in clock cycles.\n\nYou can [`read`](crate::Reg::read) this register and get [`reload::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reload::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reload`] module"] +#[doc (alias = "RELOAD")] pub type Reload = crate :: Reg < reload :: ReloadSpec > ; +#[doc = "Reload value when Timer reaches ``0``. In Periodic mode, the value written to this register specify the Timer's period in clock cycles."] pub mod reload { +#[doc = "Register `RELOAD` reader"] pub type R = crate :: R < ReloadSpec > ; +#[doc = "Register `RELOAD` writer"] pub type W = crate :: W < ReloadSpec > ; +#[doc = "Field `reload` reader - "] pub type ReloadR = crate :: FieldReader < u32 > ; +#[doc = "Field `reload` writer - "] pub type ReloadW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { +#[doc = "Bits 0:31"] +#[inline (always)] pub fn reload (& self) -> ReloadR { ReloadR :: new (self . bits) } } impl W { +#[doc = "Bits 0:31"] +#[inline (always)] pub fn reload (& mut self) -> ReloadW < ReloadSpec > { ReloadW :: new (self , 0) } } +#[doc = "Reload value when Timer reaches ``0``. In Periodic mode, the value written to this register specify the Timer's period in clock cycles.\n\nYou can [`read`](crate::Reg::read) this register and get [`reload::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reload::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ReloadSpec ; impl crate :: RegisterSpec for ReloadSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`reload::R`](R) reader structure"] impl crate :: Readable for ReloadSpec { } +#[doc = "`write(|w| ..)` method takes [`reload::W`](W) writer structure"] impl crate :: Writable for ReloadSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets RELOAD to value 0"] impl crate :: Resettable for ReloadSpec { } } +#[doc = "EN (rw) register accessor: Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set to ``0`` to disable the Timer.\n\nYou can [`read`](crate::Reg::read) this register and get [`en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@en`] module"] +#[doc (alias = "EN")] pub type En = crate :: Reg < en :: EnSpec > ; +#[doc = "Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set to ``0`` to disable the Timer."] pub mod en { +#[doc = "Register `EN` reader"] pub type R = crate :: R < EnSpec > ; +#[doc = "Register `EN` writer"] pub type W = crate :: W < EnSpec > ; +#[doc = "Field `en` reader - "] pub type EnR = crate :: BitReader ; +#[doc = "Field `en` writer - "] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0"] +#[inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } } impl W { +#[doc = "Bit 0"] +#[inline (always)] pub fn en (& mut self) -> EnW < EnSpec > { EnW :: new (self , 0) } } +#[doc = "Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set to ``0`` to disable the Timer.\n\nYou can [`read`](crate::Reg::read) this register and get [`en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EnSpec ; impl crate :: RegisterSpec for EnSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`en::R`](R) reader structure"] impl crate :: Readable for EnSpec { } +#[doc = "`write(|w| ..)` method takes [`en::W`](W) writer structure"] impl crate :: Writable for EnSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets EN to value 0"] impl crate :: Resettable for EnSpec { } } +#[doc = "UPDATE_VALUE (rw) register accessor: Update trigger for the current countdown value. A write to this register latches the current countdown value to ``value`` register.\n\nYou can [`read`](crate::Reg::read) this register and get [`update_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`update_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@update_value`] module"] +#[doc (alias = "UPDATE_VALUE")] pub type UpdateValue = crate :: Reg < update_value :: UpdateValueSpec > ; +#[doc = "Update trigger for the current countdown value. A write to this register latches the current countdown value to ``value`` register."] pub mod update_value { +#[doc = "Register `UPDATE_VALUE` reader"] pub type R = crate :: R < UpdateValueSpec > ; +#[doc = "Register `UPDATE_VALUE` writer"] pub type W = crate :: W < UpdateValueSpec > ; +#[doc = "Field `update_value` reader - "] pub type UpdateValueR = crate :: BitReader ; +#[doc = "Field `update_value` writer - "] pub type UpdateValueW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0"] +#[inline (always)] pub fn update_value (& self) -> UpdateValueR { UpdateValueR :: new ((self . bits & 1) != 0) } } impl W { +#[doc = "Bit 0"] +#[inline (always)] pub fn update_value (& mut self) -> UpdateValueW < UpdateValueSpec > { UpdateValueW :: new (self , 0) } } +#[doc = "Update trigger for the current countdown value. A write to this register latches the current countdown value to ``value`` register.\n\nYou can [`read`](crate::Reg::read) this register and get [`update_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`update_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UpdateValueSpec ; impl crate :: RegisterSpec for UpdateValueSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`update_value::R`](R) reader structure"] impl crate :: Readable for UpdateValueSpec { } +#[doc = "`write(|w| ..)` method takes [`update_value::W`](W) writer structure"] impl crate :: Writable for UpdateValueSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets UPDATE_VALUE to value 0"] impl crate :: Resettable for UpdateValueSpec { } } +#[doc = "VALUE (rw) register accessor: Latched countdown value. This value is updated by writing to ``update_value``.\n\nYou can [`read`](crate::Reg::read) this register and get [`value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`] module"] +#[doc (alias = "VALUE")] pub type Value = crate :: Reg < value :: ValueSpec > ; +#[doc = "Latched countdown value. This value is updated by writing to ``update_value``."] pub mod value { +#[doc = "Register `VALUE` reader"] pub type R = crate :: R < ValueSpec > ; +#[doc = "Register `VALUE` writer"] pub type W = crate :: W < ValueSpec > ; +#[doc = "Field `value` reader - "] pub type ValueR = crate :: FieldReader < u32 > ; +#[doc = "Field `value` writer - "] pub type ValueW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { +#[doc = "Bits 0:31"] +#[inline (always)] pub fn value (& self) -> ValueR { ValueR :: new (self . bits) } } impl W { +#[doc = "Bits 0:31"] +#[inline (always)] pub fn value (& mut self) -> ValueW < ValueSpec > { ValueW :: new (self , 0) } } +#[doc = "Latched countdown value. This value is updated by writing to ``update_value``.\n\nYou can [`read`](crate::Reg::read) this register and get [`value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ValueSpec ; impl crate :: RegisterSpec for ValueSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`value::R`](R) reader structure"] impl crate :: Readable for ValueSpec { } +#[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"] impl crate :: Writable for ValueSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets VALUE to value 0"] impl crate :: Resettable for ValueSpec { } } +#[doc = "EV_STATUS (rw) register accessor: This register contains the current raw level of the zero event trigger. Writes to this register have no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ev_status`] module"] +#[doc (alias = "EV_STATUS")] pub type EvStatus = crate :: Reg < ev_status :: EvStatusSpec > ; +#[doc = "This register contains the current raw level of the zero event trigger. Writes to this register have no effect."] pub mod ev_status { +#[doc = "Register `EV_STATUS` reader"] pub type R = crate :: R < EvStatusSpec > ; +#[doc = "Register `EV_STATUS` writer"] pub type W = crate :: W < EvStatusSpec > ; +#[doc = "Field `zero` reader - Level of the ``zero`` event"] pub type ZeroR = crate :: BitReader ; +#[doc = "Field `zero` writer - Level of the ``zero`` event"] pub type ZeroW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0 - Level of the ``zero`` event"] +#[inline (always)] pub fn zero (& self) -> ZeroR { ZeroR :: new ((self . bits & 1) != 0) } } impl W { +#[doc = "Bit 0 - Level of the ``zero`` event"] +#[inline (always)] pub fn zero (& mut self) -> ZeroW < EvStatusSpec > { ZeroW :: new (self , 0) } } +#[doc = "This register contains the current raw level of the zero event trigger. Writes to this register have no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EvStatusSpec ; impl crate :: RegisterSpec for EvStatusSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`ev_status::R`](R) reader structure"] impl crate :: Readable for EvStatusSpec { } +#[doc = "`write(|w| ..)` method takes [`ev_status::W`](W) writer structure"] impl crate :: Writable for EvStatusSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets EV_STATUS to value 0"] impl crate :: Resettable for EvStatusSpec { } } +#[doc = "EV_PENDING (rw) register accessor: When a zero event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_pending::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_pending::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ev_pending`] module"] +#[doc (alias = "EV_PENDING")] pub type EvPending = crate :: Reg < ev_pending :: EvPendingSpec > ; +#[doc = "When a zero event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register."] pub mod ev_pending { +#[doc = "Register `EV_PENDING` reader"] pub type R = crate :: R < EvPendingSpec > ; +#[doc = "Register `EV_PENDING` writer"] pub type W = crate :: W < EvPendingSpec > ; +#[doc = "Field `zero` reader - `1` if a `zero` event occurred. This Event is triggered on a **falling** edge."] pub type ZeroR = crate :: BitReader ; +#[doc = "Field `zero` writer - `1` if a `zero` event occurred. This Event is triggered on a **falling** edge."] pub type ZeroW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0 - `1` if a `zero` event occurred. This Event is triggered on a **falling** edge."] +#[inline (always)] pub fn zero (& self) -> ZeroR { ZeroR :: new ((self . bits & 1) != 0) } } impl W { +#[doc = "Bit 0 - `1` if a `zero` event occurred. This Event is triggered on a **falling** edge."] +#[inline (always)] pub fn zero (& mut self) -> ZeroW < EvPendingSpec > { ZeroW :: new (self , 0) } } +#[doc = "When a zero event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_pending::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_pending::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EvPendingSpec ; impl crate :: RegisterSpec for EvPendingSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`ev_pending::R`](R) reader structure"] impl crate :: Readable for EvPendingSpec { } +#[doc = "`write(|w| ..)` method takes [`ev_pending::W`](W) writer structure"] impl crate :: Writable for EvPendingSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets EV_PENDING to value 0"] impl crate :: Resettable for EvPendingSpec { } } +#[doc = "EV_ENABLE (rw) register accessor: This register enables the corresponding zero events. Write a ``0`` to this register to disable individual events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ev_enable`] module"] +#[doc (alias = "EV_ENABLE")] pub type EvEnable = crate :: Reg < ev_enable :: EvEnableSpec > ; +#[doc = "This register enables the corresponding zero events. Write a ``0`` to this register to disable individual events."] pub mod ev_enable { +#[doc = "Register `EV_ENABLE` reader"] pub type R = crate :: R < EvEnableSpec > ; +#[doc = "Register `EV_ENABLE` writer"] pub type W = crate :: W < EvEnableSpec > ; +#[doc = "Field `zero` reader - Write a ``1`` to enable the ``zero`` Event"] pub type ZeroR = crate :: BitReader ; +#[doc = "Field `zero` writer - Write a ``1`` to enable the ``zero`` Event"] pub type ZeroW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0 - Write a ``1`` to enable the ``zero`` Event"] +#[inline (always)] pub fn zero (& self) -> ZeroR { ZeroR :: new ((self . bits & 1) != 0) } } impl W { +#[doc = "Bit 0 - Write a ``1`` to enable the ``zero`` Event"] +#[inline (always)] pub fn zero (& mut self) -> ZeroW < EvEnableSpec > { ZeroW :: new (self , 0) } } +#[doc = "This register enables the corresponding zero events. Write a ``0`` to this register to disable individual events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EvEnableSpec ; impl crate :: RegisterSpec for EvEnableSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`ev_enable::R`](R) reader structure"] impl crate :: Readable for EvEnableSpec { } +#[doc = "`write(|w| ..)` method takes [`ev_enable::W`](W) writer structure"] impl crate :: Writable for EvEnableSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets EV_ENABLE to value 0"] impl crate :: Resettable for EvEnableSpec { } } } +#[doc = "UART"] pub type Uart = crate :: Periph < uart :: RegisterBlock , 0xf000_2800 > ; impl core :: fmt :: Debug for Uart { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Uart") . finish () } } +#[doc = "UART"] pub mod uart { +#[repr (C)] +#[doc = "Register block"] pub struct RegisterBlock { rxtx : Rxtx , txfull : Txfull , rxempty : Rxempty , ev_status : EvStatus , ev_pending : EvPending , ev_enable : EvEnable , txempty : Txempty , rxfull : Rxfull , } impl RegisterBlock { +#[doc = "0x00 - "] +#[inline (always)] pub const fn rxtx (& self) -> & Rxtx { & self . rxtx } +#[doc = "0x04 - TX FIFO Full."] +#[inline (always)] pub const fn txfull (& self) -> & Txfull { & self . txfull } +#[doc = "0x08 - RX FIFO Empty."] +#[inline (always)] pub const fn rxempty (& self) -> & Rxempty { & self . rxempty } +#[doc = "0x0c - This register contains the current raw level of the rx event trigger. Writes to this register have no effect."] +#[inline (always)] pub const fn ev_status (& self) -> & EvStatus { & self . ev_status } +#[doc = "0x10 - When a rx event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register."] +#[inline (always)] pub const fn ev_pending (& self) -> & EvPending { & self . ev_pending } +#[doc = "0x14 - This register enables the corresponding rx events. Write a ``0`` to this register to disable individual events."] +#[inline (always)] pub const fn ev_enable (& self) -> & EvEnable { & self . ev_enable } +#[doc = "0x18 - TX FIFO Empty."] +#[inline (always)] pub const fn txempty (& self) -> & Txempty { & self . txempty } +#[doc = "0x1c - RX FIFO Full."] +#[inline (always)] pub const fn rxfull (& self) -> & Rxfull { & self . rxfull } } +#[doc = "RXTX (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`rxtx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxtx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxtx`] module"] +#[doc (alias = "RXTX")] pub type Rxtx = crate :: Reg < rxtx :: RxtxSpec > ; +#[doc = ""] pub mod rxtx { +#[doc = "Register `RXTX` reader"] pub type R = crate :: R < RxtxSpec > ; +#[doc = "Register `RXTX` writer"] pub type W = crate :: W < RxtxSpec > ; +#[doc = "Field `rxtx` reader - "] pub type RxtxR = crate :: FieldReader ; +#[doc = "Field `rxtx` writer - "] pub type RxtxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { +#[doc = "Bits 0:7"] +#[inline (always)] pub fn rxtx (& self) -> RxtxR { RxtxR :: new ((self . bits & 0xff) as u8) } } impl W { +#[doc = "Bits 0:7"] +#[inline (always)] pub fn rxtx (& mut self) -> RxtxW < RxtxSpec > { RxtxW :: new (self , 0) } } +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`rxtx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxtx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RxtxSpec ; impl crate :: RegisterSpec for RxtxSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`rxtx::R`](R) reader structure"] impl crate :: Readable for RxtxSpec { } +#[doc = "`write(|w| ..)` method takes [`rxtx::W`](W) writer structure"] impl crate :: Writable for RxtxSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets RXTX to value 0"] impl crate :: Resettable for RxtxSpec { } } +#[doc = "TXFULL (rw) register accessor: TX FIFO Full.\n\nYou can [`read`](crate::Reg::read) this register and get [`txfull::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfull::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfull`] module"] +#[doc (alias = "TXFULL")] pub type Txfull = crate :: Reg < txfull :: TxfullSpec > ; +#[doc = "TX FIFO Full."] pub mod txfull { +#[doc = "Register `TXFULL` reader"] pub type R = crate :: R < TxfullSpec > ; +#[doc = "Register `TXFULL` writer"] pub type W = crate :: W < TxfullSpec > ; +#[doc = "Field `txfull` reader - "] pub type TxfullR = crate :: BitReader ; +#[doc = "Field `txfull` writer - "] pub type TxfullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0"] +#[inline (always)] pub fn txfull (& self) -> TxfullR { TxfullR :: new ((self . bits & 1) != 0) } } impl W { +#[doc = "Bit 0"] +#[inline (always)] pub fn txfull (& mut self) -> TxfullW < TxfullSpec > { TxfullW :: new (self , 0) } } +#[doc = "TX FIFO Full.\n\nYou can [`read`](crate::Reg::read) this register and get [`txfull::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfull::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TxfullSpec ; impl crate :: RegisterSpec for TxfullSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`txfull::R`](R) reader structure"] impl crate :: Readable for TxfullSpec { } +#[doc = "`write(|w| ..)` method takes [`txfull::W`](W) writer structure"] impl crate :: Writable for TxfullSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets TXFULL to value 0"] impl crate :: Resettable for TxfullSpec { } } +#[doc = "RXEMPTY (rw) register accessor: RX FIFO Empty.\n\nYou can [`read`](crate::Reg::read) this register and get [`rxempty::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxempty::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxempty`] module"] +#[doc (alias = "RXEMPTY")] pub type Rxempty = crate :: Reg < rxempty :: RxemptySpec > ; +#[doc = "RX FIFO Empty."] pub mod rxempty { +#[doc = "Register `RXEMPTY` reader"] pub type R = crate :: R < RxemptySpec > ; +#[doc = "Register `RXEMPTY` writer"] pub type W = crate :: W < RxemptySpec > ; +#[doc = "Field `rxempty` reader - "] pub type RxemptyR = crate :: BitReader ; +#[doc = "Field `rxempty` writer - "] pub type RxemptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0"] +#[inline (always)] pub fn rxempty (& self) -> RxemptyR { RxemptyR :: new ((self . bits & 1) != 0) } } impl W { +#[doc = "Bit 0"] +#[inline (always)] pub fn rxempty (& mut self) -> RxemptyW < RxemptySpec > { RxemptyW :: new (self , 0) } } +#[doc = "RX FIFO Empty.\n\nYou can [`read`](crate::Reg::read) this register and get [`rxempty::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxempty::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RxemptySpec ; impl crate :: RegisterSpec for RxemptySpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`rxempty::R`](R) reader structure"] impl crate :: Readable for RxemptySpec { } +#[doc = "`write(|w| ..)` method takes [`rxempty::W`](W) writer structure"] impl crate :: Writable for RxemptySpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets RXEMPTY to value 0"] impl crate :: Resettable for RxemptySpec { } } +#[doc = "EV_STATUS (rw) register accessor: This register contains the current raw level of the rx event trigger. Writes to this register have no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ev_status`] module"] +#[doc (alias = "EV_STATUS")] pub type EvStatus = crate :: Reg < ev_status :: EvStatusSpec > ; +#[doc = "This register contains the current raw level of the rx event trigger. Writes to this register have no effect."] pub mod ev_status { +#[doc = "Register `EV_STATUS` reader"] pub type R = crate :: R < EvStatusSpec > ; +#[doc = "Register `EV_STATUS` writer"] pub type W = crate :: W < EvStatusSpec > ; +#[doc = "Field `tx` reader - Level of the ``tx`` event"] pub type TxR = crate :: BitReader ; +#[doc = "Field `tx` writer - Level of the ``tx`` event"] pub type TxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `rx` reader - Level of the ``rx`` event"] pub type RxR = crate :: BitReader ; +#[doc = "Field `rx` writer - Level of the ``rx`` event"] pub type RxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0 - Level of the ``tx`` event"] +#[inline (always)] pub fn tx (& self) -> TxR { TxR :: new ((self . bits & 1) != 0) } +#[doc = "Bit 1 - Level of the ``rx`` event"] +#[inline (always)] pub fn rx (& self) -> RxR { RxR :: new (((self . bits >> 1) & 1) != 0) } } impl W { +#[doc = "Bit 0 - Level of the ``tx`` event"] +#[inline (always)] pub fn tx (& mut self) -> TxW < EvStatusSpec > { TxW :: new (self , 0) } +#[doc = "Bit 1 - Level of the ``rx`` event"] +#[inline (always)] pub fn rx (& mut self) -> RxW < EvStatusSpec > { RxW :: new (self , 1) } } +#[doc = "This register contains the current raw level of the rx event trigger. Writes to this register have no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EvStatusSpec ; impl crate :: RegisterSpec for EvStatusSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`ev_status::R`](R) reader structure"] impl crate :: Readable for EvStatusSpec { } +#[doc = "`write(|w| ..)` method takes [`ev_status::W`](W) writer structure"] impl crate :: Writable for EvStatusSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets EV_STATUS to value 0"] impl crate :: Resettable for EvStatusSpec { } } +#[doc = "EV_PENDING (rw) register accessor: When a rx event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_pending::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_pending::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ev_pending`] module"] +#[doc (alias = "EV_PENDING")] pub type EvPending = crate :: Reg < ev_pending :: EvPendingSpec > ; +#[doc = "When a rx event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register."] pub mod ev_pending { +#[doc = "Register `EV_PENDING` reader"] pub type R = crate :: R < EvPendingSpec > ; +#[doc = "Register `EV_PENDING` writer"] pub type W = crate :: W < EvPendingSpec > ; +#[doc = "Field `tx` reader - `1` if a `tx` event occurred. This Event is triggered on a **falling** edge."] pub type TxR = crate :: BitReader ; +#[doc = "Field `tx` writer - `1` if a `tx` event occurred. This Event is triggered on a **falling** edge."] pub type TxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `rx` reader - `1` if a `rx` event occurred. This Event is triggered on a **falling** edge."] pub type RxR = crate :: BitReader ; +#[doc = "Field `rx` writer - `1` if a `rx` event occurred. This Event is triggered on a **falling** edge."] pub type RxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0 - `1` if a `tx` event occurred. This Event is triggered on a **falling** edge."] +#[inline (always)] pub fn tx (& self) -> TxR { TxR :: new ((self . bits & 1) != 0) } +#[doc = "Bit 1 - `1` if a `rx` event occurred. This Event is triggered on a **falling** edge."] +#[inline (always)] pub fn rx (& self) -> RxR { RxR :: new (((self . bits >> 1) & 1) != 0) } } impl W { +#[doc = "Bit 0 - `1` if a `tx` event occurred. This Event is triggered on a **falling** edge."] +#[inline (always)] pub fn tx (& mut self) -> TxW < EvPendingSpec > { TxW :: new (self , 0) } +#[doc = "Bit 1 - `1` if a `rx` event occurred. This Event is triggered on a **falling** edge."] +#[inline (always)] pub fn rx (& mut self) -> RxW < EvPendingSpec > { RxW :: new (self , 1) } } +#[doc = "When a rx event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_pending::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_pending::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EvPendingSpec ; impl crate :: RegisterSpec for EvPendingSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`ev_pending::R`](R) reader structure"] impl crate :: Readable for EvPendingSpec { } +#[doc = "`write(|w| ..)` method takes [`ev_pending::W`](W) writer structure"] impl crate :: Writable for EvPendingSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets EV_PENDING to value 0"] impl crate :: Resettable for EvPendingSpec { } } +#[doc = "EV_ENABLE (rw) register accessor: This register enables the corresponding rx events. Write a ``0`` to this register to disable individual events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ev_enable`] module"] +#[doc (alias = "EV_ENABLE")] pub type EvEnable = crate :: Reg < ev_enable :: EvEnableSpec > ; +#[doc = "This register enables the corresponding rx events. Write a ``0`` to this register to disable individual events."] pub mod ev_enable { +#[doc = "Register `EV_ENABLE` reader"] pub type R = crate :: R < EvEnableSpec > ; +#[doc = "Register `EV_ENABLE` writer"] pub type W = crate :: W < EvEnableSpec > ; +#[doc = "Field `tx` reader - Write a ``1`` to enable the ``tx`` Event"] pub type TxR = crate :: BitReader ; +#[doc = "Field `tx` writer - Write a ``1`` to enable the ``tx`` Event"] pub type TxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; +#[doc = "Field `rx` reader - Write a ``1`` to enable the ``rx`` Event"] pub type RxR = crate :: BitReader ; +#[doc = "Field `rx` writer - Write a ``1`` to enable the ``rx`` Event"] pub type RxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0 - Write a ``1`` to enable the ``tx`` Event"] +#[inline (always)] pub fn tx (& self) -> TxR { TxR :: new ((self . bits & 1) != 0) } +#[doc = "Bit 1 - Write a ``1`` to enable the ``rx`` Event"] +#[inline (always)] pub fn rx (& self) -> RxR { RxR :: new (((self . bits >> 1) & 1) != 0) } } impl W { +#[doc = "Bit 0 - Write a ``1`` to enable the ``tx`` Event"] +#[inline (always)] pub fn tx (& mut self) -> TxW < EvEnableSpec > { TxW :: new (self , 0) } +#[doc = "Bit 1 - Write a ``1`` to enable the ``rx`` Event"] +#[inline (always)] pub fn rx (& mut self) -> RxW < EvEnableSpec > { RxW :: new (self , 1) } } +#[doc = "This register enables the corresponding rx events. Write a ``0`` to this register to disable individual events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ev_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ev_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EvEnableSpec ; impl crate :: RegisterSpec for EvEnableSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`ev_enable::R`](R) reader structure"] impl crate :: Readable for EvEnableSpec { } +#[doc = "`write(|w| ..)` method takes [`ev_enable::W`](W) writer structure"] impl crate :: Writable for EvEnableSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets EV_ENABLE to value 0"] impl crate :: Resettable for EvEnableSpec { } } +#[doc = "TXEMPTY (rw) register accessor: TX FIFO Empty.\n\nYou can [`read`](crate::Reg::read) this register and get [`txempty::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txempty::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txempty`] module"] +#[doc (alias = "TXEMPTY")] pub type Txempty = crate :: Reg < txempty :: TxemptySpec > ; +#[doc = "TX FIFO Empty."] pub mod txempty { +#[doc = "Register `TXEMPTY` reader"] pub type R = crate :: R < TxemptySpec > ; +#[doc = "Register `TXEMPTY` writer"] pub type W = crate :: W < TxemptySpec > ; +#[doc = "Field `txempty` reader - "] pub type TxemptyR = crate :: BitReader ; +#[doc = "Field `txempty` writer - "] pub type TxemptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0"] +#[inline (always)] pub fn txempty (& self) -> TxemptyR { TxemptyR :: new ((self . bits & 1) != 0) } } impl W { +#[doc = "Bit 0"] +#[inline (always)] pub fn txempty (& mut self) -> TxemptyW < TxemptySpec > { TxemptyW :: new (self , 0) } } +#[doc = "TX FIFO Empty.\n\nYou can [`read`](crate::Reg::read) this register and get [`txempty::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txempty::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TxemptySpec ; impl crate :: RegisterSpec for TxemptySpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`txempty::R`](R) reader structure"] impl crate :: Readable for TxemptySpec { } +#[doc = "`write(|w| ..)` method takes [`txempty::W`](W) writer structure"] impl crate :: Writable for TxemptySpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets TXEMPTY to value 0"] impl crate :: Resettable for TxemptySpec { } } +#[doc = "RXFULL (rw) register accessor: RX FIFO Full.\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfull::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfull::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfull`] module"] +#[doc (alias = "RXFULL")] pub type Rxfull = crate :: Reg < rxfull :: RxfullSpec > ; +#[doc = "RX FIFO Full."] pub mod rxfull { +#[doc = "Register `RXFULL` reader"] pub type R = crate :: R < RxfullSpec > ; +#[doc = "Register `RXFULL` writer"] pub type W = crate :: W < RxfullSpec > ; +#[doc = "Field `rxfull` reader - "] pub type RxfullR = crate :: BitReader ; +#[doc = "Field `rxfull` writer - "] pub type RxfullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { +#[doc = "Bit 0"] +#[inline (always)] pub fn rxfull (& self) -> RxfullR { RxfullR :: new ((self . bits & 1) != 0) } } impl W { +#[doc = "Bit 0"] +#[inline (always)] pub fn rxfull (& mut self) -> RxfullW < RxfullSpec > { RxfullW :: new (self , 0) } } +#[doc = "RX FIFO Full.\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfull::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfull::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RxfullSpec ; impl crate :: RegisterSpec for RxfullSpec { type Ux = u32 ; } +#[doc = "`read()` method returns [`rxfull::R`](R) reader structure"] impl crate :: Readable for RxfullSpec { } +#[doc = "`write(|w| ..)` method takes [`rxfull::W`](W) writer structure"] impl crate :: Writable for RxfullSpec { type Safety = crate :: Unsafe ; } +#[doc = "`reset()` method sets RXFULL to value 0"] impl crate :: Resettable for RxfullSpec { } } } +#[no_mangle] static mut DEVICE_PERIPHERALS : bool = false ; +#[doc = r" All the peripherals."] +#[allow (non_snake_case)] pub struct Peripherals { +#[doc = "CTRL"] pub ctrl : Ctrl , +#[doc = "IDENTIFIER_MEM"] pub identifier_mem : IdentifierMem , +#[doc = "LEDS"] pub leds : Leds , +#[doc = "SDRAM"] pub sdram : Sdram , +#[doc = "TIMER0"] pub timer0 : Timer0 , +#[doc = "UART"] pub uart : Uart , } impl Peripherals { +#[doc = r" Returns all the peripherals *once*."] +#[cfg (feature = "critical-section")] +#[inline] pub fn take () -> Option < Self > { critical_section :: with (| _ | { if unsafe { DEVICE_PERIPHERALS } { return None } Some (unsafe { Peripherals :: steal () }) }) } +#[doc = r" Unchecked version of `Peripherals::take`."] +#[doc = r""] +#[doc = r" # Safety"] +#[doc = r""] +#[doc = r" Each of the returned peripherals must be used at most once."] +#[inline] pub unsafe fn steal () -> Self { DEVICE_PERIPHERALS = true ; Peripherals { ctrl : Ctrl :: steal () , identifier_mem : IdentifierMem :: steal () , leds : Leds :: steal () , sdram : Sdram :: steal () , timer0 : Timer0 :: steal () , uart : Uart :: steal () , } } } \ No newline at end of file diff --git a/cpu/ulx3s-hal/src/ulx3s.svd b/cpu/ulx3s-hal/src/ulx3s.svd new file mode 100644 index 0000000..1c3a1f8 --- /dev/null +++ b/cpu/ulx3s-hal/src/ulx3s.svd @@ -0,0 +1,682 @@ + + + + litex + SOC + + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + CTRL + 0xF0000000 + CTRL + + + RESET + 0x0000 + 0x00 + 32 + + + soc_rst + 0 + [0:0] + 0 + + + + cpu_rst + 1 + [1:1] + 1 + + + + + + SCRATCH + + 0x0004 + 0x12345678 + 32 + + + scratch + 31 + [31:0] + 0 + + + + + BUS_ERRORS + + 0x0008 + 0x00 + 32 + + + bus_errors + 31 + [31:0] + 0 + + + + + + 0 + 0xc + registers + + + + IDENTIFIER_MEM + 0xF0000800 + IDENTIFIER_MEM + + + IDENTIFIER_MEM + + 0x0000 + 0x00 + 32 + + + identifier_mem + 7 + [7:0] + 0 + + + + + + 0 + 0x4 + registers + + + + LEDS + 0xF0001000 + LEDS + + + OUT + + 0x0000 + 0x00 + 32 + + + out + 7 + [7:0] + 0 + + + + + + 0 + 0x4 + registers + + + + SDRAM + 0xF0001800 + SDRAM + + + DFII_CONTROL + + 0x0000 + 0x01 + 32 + + + sel + 0 + [0:0] + 0 + + + + cke + 1 + [1:1] + 1 + + + + odt + 2 + [2:2] + 2 + + + + reset_n + 3 + [3:3] + 3 + + + + + + DFII_PI0_COMMAND + + 0x0004 + 0x00 + 32 + + + cs + 0 + [0:0] + 0 + + + + we + 1 + [1:1] + 1 + + + + cas + 2 + [2:2] + 2 + + + + ras + 3 + [3:3] + 3 + + + + wren + 4 + [4:4] + 4 + + + + rden + 5 + [5:5] + 5 + + + + cs_top + 6 + [6:6] + 6 + + + + cs_bottom + 7 + [7:7] + 7 + + + + + + DFII_PI0_COMMAND_ISSUE + 0x0008 + 0x00 + 32 + + + dfii_pi0_command_issue + 0 + [0:0] + 0 + + + + + DFII_PI0_ADDRESS + + 0x000c + 0x00 + 32 + + + dfii_pi0_address + 12 + [12:0] + 0 + + + + + DFII_PI0_BADDRESS + + 0x0010 + 0x00 + 32 + + + dfii_pi0_baddress + 1 + [1:0] + 0 + + + + + DFII_PI0_WRDATA + + 0x0014 + 0x00 + 32 + + + dfii_pi0_wrdata + 15 + [15:0] + 0 + + + + + DFII_PI0_RDDATA + + 0x0018 + 0x00 + 32 + + + dfii_pi0_rddata + 15 + [15:0] + 0 + + + + + + 0 + 0x1c + registers + + + + TIMER0 + 0xF0002000 + TIMER0 + + + LOAD + + 0x0000 + 0x00 + 32 + + + load + 31 + [31:0] + 0 + + + + + RELOAD + + 0x0004 + 0x00 + 32 + + + reload + 31 + [31:0] + 0 + + + + + EN + + 0x0008 + 0x00 + 32 + + + en + 0 + [0:0] + 0 + + + + + UPDATE_VALUE + + 0x000c + 0x00 + 32 + + + update_value + 0 + [0:0] + 0 + + + + + VALUE + + 0x0010 + 0x00 + 32 + + + value + 31 + [31:0] + 0 + + + + + EV_STATUS + + 0x0014 + 0x00 + 32 + + + zero + 0 + [0:0] + 0 + + + + + + EV_PENDING + + 0x0018 + 0x00 + 32 + + + zero + 0 + [0:0] + 0 + + + + + + EV_ENABLE + + 0x001c + 0x00 + 32 + + + zero + 0 + [0:0] + 0 + + + + + + + 0 + 0x20 + registers + + + timer0 + 1 + + + + UART + 0xF0002800 + UART + + + RXTX + 0x0000 + 0x00 + 32 + + + rxtx + 7 + [7:0] + 0 + + + + + TXFULL + + 0x0004 + 0x00 + 32 + + + txfull + 0 + [0:0] + 0 + + + + + RXEMPTY + + 0x0008 + 0x00 + 32 + + + rxempty + 0 + [0:0] + 0 + + + + + EV_STATUS + + 0x000c + 0x00 + 32 + + + tx + 0 + [0:0] + 0 + + + + rx + 1 + [1:1] + 1 + + + + + + EV_PENDING + + 0x0010 + 0x00 + 32 + + + tx + 0 + [0:0] + 0 + + + + rx + 1 + [1:1] + 1 + + + + + + EV_ENABLE + + 0x0014 + 0x00 + 32 + + + tx + 0 + [0:0] + 0 + + + + rx + 1 + [1:1] + 1 + + + + + + TXEMPTY + + 0x0018 + 0x00 + 32 + + + txempty + 0 + [0:0] + 0 + + + + + RXFULL + + 0x001c + 0x00 + 32 + + + rxfull + 0 + [0:0] + 0 + + + + + + 0 + 0x20 + registers + + + uart + 0 + + + + + + + ROM + 0x00000000 + 0x00020000 + + + SRAM + 0x10000000 + 0x00002000 + + + MAIN_RAM + 0x40000000 + 0x02000000 + + + CSR + 0xF0000000 + 0x00010000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/flake.nix b/flake.nix index c5d54ba..811c230 100644 --- a/flake.nix +++ b/flake.nix @@ -21,13 +21,22 @@ { devShells.default = pkgs.mkShell { packages = with pkgs; [ + (python3.withPackages (pk: with pk; [ + meson + sphinx + sphinxcontrib-wavedrom + ])) + libevent + cjson circt fujprog nextpnr sbt scalafmt + rustfmt sdl3 trellis + svd2rust verilator yosys ];