From 563ba3758630e0bf97e032dfaf9f0952478110e2 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Wed, 25 Feb 2026 18:40:26 +0000 Subject: [PATCH] clk/bcm2835: Don't allow "osc" as a parent for "dpi" DPI being a pixel clock needs to be fairly accurate. BCM2711 has changed the oscillator from 19.2MHz to 54MHz, so the current clock manager code thinks that for eg a 32MHz pixel clock it can use the oscillator and a fractional divider. For many displays this isn't acceptable. Add a new option for clock parentage that doesn't permit the oscillator, and use this option for the DPI clock. Signed-off-by: Dave Stevenson --- drivers/clk/bcm/clk-bcm2835.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 6b6f77ba0a796b..d30c3eef52a015 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1637,6 +1637,22 @@ static const char *const bcm2835_clock_per_parents[] = { .parents = bcm2835_clock_per_parents, \ __VA_ARGS__) +static const char *const bcm2835_clock_per_no_osc_parents[] = { + "gnd", + "testdebug0", + "testdebug1", + "plla_per", + "pllc_per", + "plld_per", + "pllh_aux", +}; + +#define REGISTER_PER_NO_OSC_CLK(s, ...) REGISTER_CLK( \ + s, \ + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_no_osc_parents), \ + .parents = bcm2835_clock_per_no_osc_parents, \ + __VA_ARGS__) + /* * Restrict clock sources for the PCM peripheral to the oscillator and * PLLD_PER because other source may have varying rates or be switched @@ -2126,7 +2142,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .div_reg = CM_DFTDIV, .int_bits = 5, .frac_bits = 0), - [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( + [BCM2835_CLOCK_DPI] = REGISTER_PER_NO_OSC_CLK( SOC_ALL, .name = "dpi", .ctl_reg = CM_DPICTL,